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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: acjmyvzDTN3cYJ3RgLbKGteX4jki4nQkRf4YyawX1ZjZ1JVM/QouPVorv3rEde2Nl92HNAQOquJg+7E3VgUaV90af4aPMt2r55geSvNce3/H7Pn4VMr/eP9vAVsNjRukeN0JkBgVllf3HpE5OkPdeHLY98SxOLmF/lnPVhPBmwmaf+WPNTPyDbFI3LahAEichaMfVLRYadSn5VxfqWO/t0XHIXdllcEfQOseZaHh+4TFIEHSWZhZMjt8wzwZvCYaVVmqCxkp53v8SWY+2KPowBQKR/UtNpSGYJfuQFqNnEC+GdH6bBa80A4tSdvCfrNqJ22VU1DcnxcifaNmh6K0W94qYolPkGQsFgkLZIBb1pMb4JKk4b8cW9PrzXEndrGoULA1VeZN9ZkFtR6RYqfqWmCTkKL8ArmJSbxBN0r0NEzZMSqusrY1NjY6lcbzNpTH1OiQvXMT5RY8pWPu5lJKNuqGtwL1lOZAIyUHqykNUyPKqBvfpJC8Iwu1gXm7g+f26jFfSqIa2zCgvxvi4V3gbyoCKLd0ZA8JSGfiJNqV9uog7KFm+ZJF9CqZ5VI2pCy/lfB9rDO9ixb0sM9wIaLGbwFcLpZ2EolXjgq0uM66FDRhfi6jWjpuS0GQFQmhaOdW1a9eCiHc6ZtX0ZX1JkWoGY9R6Xlj+dUPvGXBQuK2rDQEL3APjyvNYKJbigApMoQNPpvFXdEkDXESGgOG6heCepwfO51UvFwrBwtXIVLDDQ8AMiwqJplsV0kcdxR3clCD4YvkoT41Tk1OYvq19yEjTIVy5s6/u+mbbDYHKFD1ThAdK7KwliYS+7kEAWtb1EhWexKSyBwFbkJKDsYKgFY3pq+koYmtLYAV5IvIH5vuJ0RmlWvs65C/f231HQA8+dNNV2HkuQM0O61gnS6KF/HuWI7HlNWm09OGIdbvNMo2sx1FF478BoYC6yhfL2UaIy6Hf70U9MP3jsZ7kh9b3FMkQLofP35pQJPWviwTtOjicqcpLwWz/MksO5IbLQ4gBJVO5c97DdGfE85mOPvagCHiJc0ozrZY1rYUHXNiKIWajSPOIakZQPO5ycr2WDfknznxh30fhd9/glaQ7fzXAO2IIgSaDwBsmejfuuyDJEG86fzE4zqtSiWhziiAov91lgKrtkOilDsT7WGc2cdjio/uKfFcebFePGPHEu/dtIVXMpAdS7Sjrd0OBH5GFLUUOpt7KCf3oTZ5KrqrieBYpaVEJkr50VbyOlytR0Zp7nkBhhjiAFafaAFETxyzS+pprFYKxcV+gsvN1xZVxVLX0GshQJuILRKHM7ZfayZ3QkPC6Y5h4W/KlsAJbPNiym35/lx9WYWTp49T8dKNxqZwCdbhBvAK4teGMhRW75tqhp0XgtE0j2WbC+akHEcE4LarvnaDyAG/QHga90jSmzTfmul1pca03hBTGC7bgh1XhauFM93aw8+OWvPuAF1U7Y1svsgALiZaAIeqKkMJJknpsTd97pmq/478K6bL1H6N9b3KuoKRqWlOllw5fcj6Fzmn/3RK1aO7GNOO1WvjnNxkyzyPPHP5ilvzWVeWN7ELJ1v5ll27KutLX0qYZg59i6aPMKzAEkENH4Di/tSkEgUyF/jtZOMpmn1au4Y+pTTFM2Hqicn6nR4v3NYdCaNaL7kRFP6B6kA5TJ0NX7qA65gsmChp7kWpGGFTh3MiYldh4sSjaZg= X-OriginatorOrg: wolfvision.net X-MS-Exchange-CrossTenant-Network-Message-Id: ece9baeb-56dc-4430-aeb9-08dafdce7445 X-MS-Exchange-CrossTenant-AuthSource: DU0PR08MB9155.eurprd08.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 05:47:18.3879 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e94ec9da-9183-471e-83b3-51baa8eb804f X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uxsKFkoADZBILnwX0zHPUt9Wn9VE9tr83pbkSTrKEn0YEHdODlQnMFtbi0lYUqtfpKLtsiAFfOEcF+jbAF9fWj8rtVk5rR8II+ZIOF3G+XI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5678 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230123_214725_256652_E64FD288 X-CRM114-Status: GOOD ( 13.34 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The variable possible_crtcs is only initialized for primary and overlay planes. Since the VOP2 driver only supports these plane types at the moment, the current code is safe. However, in order to provide a future-proof solution, fix the initialization of the variable. Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Michael Riesch --- v3: - no changes v2: - new patch drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 8cecf81a5ae0..374ef821b453 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2322,10 +2322,11 @@ static int vop2_create_crtc(struct vop2 *vop2) /* change the unused primary window to overlay window */ win->type = DRM_PLANE_TYPE_OVERLAY; } - } - - if (win->type == DRM_PLANE_TYPE_OVERLAY) + } else if (win->type == DRM_PLANE_TYPE_OVERLAY) { possible_crtcs = (1 << nvps) - 1; + } else { + possible_crtcs = 0; + } ret = vop2_plane_init(vop2, win, possible_crtcs); if (ret) { From patchwork Tue Jan 24 05:47:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 13113532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 121ADC38142 for ; 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However, this step has not yet been carried out for the RGB output block. Embed the drm_encoder structure into the rockchip_encoder structure and set the endpoint ID correctly. Signed-off-by: Michael Riesch --- v3: - no changes v2: - use endpoint id from device tree instead of hardcoded value drivers/gpu/drm/rockchip/rockchip_rgb.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 75eb7cca3d82..5971df4302f2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -22,13 +22,11 @@ #include "rockchip_drm_vop.h" #include "rockchip_rgb.h" -#define encoder_to_rgb(c) container_of(c, struct rockchip_rgb, encoder) - struct rockchip_rgb { struct device *dev; struct drm_device *drm_dev; struct drm_bridge *bridge; - struct drm_encoder encoder; + struct rockchip_encoder encoder; struct drm_connector connector; int output_mode; }; @@ -125,7 +123,7 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, return ERR_PTR(ret); } - encoder = &rgb->encoder; + encoder = &rgb->encoder.encoder; encoder->possible_crtcs = drm_crtc_mask(crtc); ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_NONE); @@ -161,6 +159,8 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, goto err_free_encoder; } + rgb->encoder.crtc_endpoint_id = endpoint_id; + ret = drm_connector_attach_encoder(connector, encoder); if (ret < 0) { DRM_DEV_ERROR(drm_dev->dev, @@ -182,6 +182,6 @@ void rockchip_rgb_fini(struct rockchip_rgb *rgb) { drm_panel_bridge_remove(rgb->bridge); drm_connector_cleanup(&rgb->connector); - drm_encoder_cleanup(&rgb->encoder); + drm_encoder_cleanup(&rgb->encoder.encoder); } EXPORT_SYMBOL_GPL(rockchip_rgb_fini); From patchwork Tue Jan 24 05:47:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 13113535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77DD2C38142 for ; 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Received: from DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) by VE1PR08MB5678.eurprd08.prod.outlook.com (2603:10a6:800:1a0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.33; Tue, 24 Jan 2023 05:47:21 +0000 Received: from DU0PR08MB9155.eurprd08.prod.outlook.com ([fe80::4718:6092:e763:4219]) by DU0PR08MB9155.eurprd08.prod.outlook.com ([fe80::4718:6092:e763:4219%2]) with mapi id 15.20.6002.033; Tue, 24 Jan 2023 05:47:21 +0000 From: Michael Riesch To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sandy Huang , David Airlie , Daniel Vetter , Sascha Hauer , Michael Riesch Subject: [PATCH v3 3/6] drm/rockchip: rgb: add video_port parameter to init function Date: Tue, 24 Jan 2023 06:47:03 +0100 Message-Id: <20230124054706.3921383-4-michael.riesch@wolfvision.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230124054706.3921383-1-michael.riesch@wolfvision.net> References: <20230124054706.3921383-1-michael.riesch@wolfvision.net> X-ClientProxiedBy: ZR0P278CA0189.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:44::6) To DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR08MB9155:EE_|VE1PR08MB5678:EE_ X-MS-Office365-Filtering-Correlation-Id: c11522e3-3241-4b4d-9e73-08dafdce75d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add an extra parameter for the video port id to the rockchip_rgb_init function. Signed-off-by: Michael Riesch --- v3: - no changes v2: - no changes drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +- drivers/gpu/drm/rockchip/rockchip_rgb.c | 9 +++++---- drivers/gpu/drm/rockchip/rockchip_rgb.h | 6 ++++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index fa1f4ee6d195..5d18dea5c8d6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -2221,7 +2221,7 @@ static int vop_bind(struct device *dev, struct device *master, void *data) goto err_disable_pm_runtime; if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { - vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); + vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); if (IS_ERR(vop->rgb)) { ret = PTR_ERR(vop->rgb); goto err_disable_pm_runtime; diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 5971df4302f2..c677b71ae516 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -72,7 +72,8 @@ struct drm_encoder_helper_funcs rockchip_rgb_encoder_helper_funcs = { struct rockchip_rgb *rockchip_rgb_init(struct device *dev, struct drm_crtc *crtc, - struct drm_device *drm_dev) + struct drm_device *drm_dev, + int video_port) { struct rockchip_rgb *rgb; struct drm_encoder *encoder; @@ -90,7 +91,7 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, rgb->dev = dev; rgb->drm_dev = drm_dev; - port = of_graph_get_port_by_id(dev->of_node, 0); + port = of_graph_get_port_by_id(dev->of_node, video_port); if (!port) return ERR_PTR(-EINVAL); @@ -103,8 +104,8 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, continue; child_count++; - ret = drm_of_find_panel_or_bridge(dev->of_node, 0, endpoint_id, - &panel, &bridge); + ret = drm_of_find_panel_or_bridge(dev->of_node, video_port, + endpoint_id, &panel, &bridge); if (!ret) { of_node_put(endpoint); break; diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.h b/drivers/gpu/drm/rockchip/rockchip_rgb.h index 27b9635124bc..1bd4e20e91eb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.h +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.h @@ -8,12 +8,14 @@ #ifdef CONFIG_ROCKCHIP_RGB struct rockchip_rgb *rockchip_rgb_init(struct device *dev, struct drm_crtc *crtc, - struct drm_device *drm_dev); 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Tue, 24 Jan 2023 05:47:22 +0000 From: Michael Riesch To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sandy Huang , David Airlie , Daniel Vetter , Sascha Hauer , Michael Riesch Subject: [PATCH v3 4/6] drm/rockchip: vop2: use symmetric function pair vop2_{create,destroy}_crtcs Date: Tue, 24 Jan 2023 06:47:04 +0100 Message-Id: <20230124054706.3921383-5-michael.riesch@wolfvision.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230124054706.3921383-1-michael.riesch@wolfvision.net> References: <20230124054706.3921383-1-michael.riesch@wolfvision.net> X-ClientProxiedBy: ZR0P278CA0189.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:44::6) To DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR08MB9155:EE_|VI1PR08MB10032:EE_ X-MS-Office365-Filtering-Correlation-Id: cc682a86-e116-48f3-0578-08dafdce76ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Also, use a symmetric function pair to create and destroy the CRTCs and the corresponding planes. Signed-off-by: Michael Riesch --- v3: - no changes v2: - no changes drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 374ef821b453..06fcdfa7b885 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2246,7 +2246,7 @@ static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) #define NR_LAYERS 6 -static int vop2_create_crtc(struct vop2 *vop2) +static int vop2_create_crtcs(struct vop2 *vop2) { const struct vop2_data *vop2_data = vop2->data; struct drm_device *drm = vop2->drm; @@ -2372,15 +2372,25 @@ static int vop2_create_crtc(struct vop2 *vop2) return 0; } -static void vop2_destroy_crtc(struct drm_crtc *crtc) +static void vop2_destroy_crtcs(struct vop2 *vop2) { - of_node_put(crtc->port); + struct drm_device *drm = vop2->drm; + struct list_head *crtc_list = &drm->mode_config.crtc_list; + struct list_head *plane_list = &drm->mode_config.plane_list; + struct drm_crtc *crtc, *tmpc; + struct drm_plane *plane, *tmpp; + + list_for_each_entry_safe(plane, tmpp, plane_list, head) + drm_plane_cleanup(plane); /* * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() * references the CRTC. */ - drm_crtc_cleanup(crtc); + list_for_each_entry_safe(crtc, tmpc, crtc_list, head) { + of_node_put(crtc->port); + drm_crtc_cleanup(crtc); + } } static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { @@ -2684,7 +2694,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - ret = vop2_create_crtc(vop2); + ret = vop2_create_crtcs(vop2); if (ret) return ret; @@ -2698,19 +2708,10 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) static void vop2_unbind(struct device *dev, struct device *master, void *data) { struct vop2 *vop2 = dev_get_drvdata(dev); - struct drm_device *drm = vop2->drm; - struct list_head *plane_list = &drm->mode_config.plane_list; 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Tue, 24 Jan 2023 05:47:23 +0000 From: Michael Riesch To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sandy Huang , David Airlie , Daniel Vetter , Sascha Hauer , Michael Riesch Subject: [PATCH v3 5/6] drm/rockchip: vop2: add support for the rgb output block Date: Tue, 24 Jan 2023 06:47:05 +0100 Message-Id: <20230124054706.3921383-6-michael.riesch@wolfvision.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230124054706.3921383-1-michael.riesch@wolfvision.net> References: <20230124054706.3921383-1-michael.riesch@wolfvision.net> X-ClientProxiedBy: ZR0P278CA0189.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:44::6) To DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR08MB9155:EE_|VI1PR08MB10032:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a016dd7-b29f-4535-b0c3-08dafdce7771 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add support for this output block. Signed-off-by: Michael Riesch --- v3: - fix commit messages (still assumed video port 2) - fix condition to make 0 a valid video port v2: - move away from wrong assumption that the RGB block is always connected to video port 2 -> check devicetree to find RGB block drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 06fcdfa7b885..f38ffd0ccd9f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -39,6 +39,7 @@ #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" #include "rockchip_drm_vop2.h" +#include "rockchip_rgb.h" /* * VOP2 architecture @@ -212,6 +213,9 @@ struct vop2 { struct clk *hclk; struct clk *aclk; + /* optional internal rgb encoder */ + struct rockchip_rgb *rgb; + /* must be put at the end of the struct */ struct vop2_win win[]; }; @@ -2393,6 +2397,25 @@ static void vop2_destroy_crtcs(struct vop2 *vop2) } } +static int vop2_find_rgb_encoder(struct vop2 *vop2) +{ + struct device_node *node = vop2->dev->of_node; + struct device_node *endpoint; + int i; + + for (i = 0; i < vop2->data->nr_vps; i++) { + endpoint = of_graph_get_endpoint_by_regs(node, i, + ROCKCHIP_VOP2_EP_RGB0); + if (!endpoint) + continue; + + of_node_put(endpoint); + return i; + } + + return -ENOENT; +} + static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), @@ -2698,11 +2721,29 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; + ret = vop2_find_rgb_encoder(vop2); + if (ret >= 0) { + vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, + vop2->drm, ret); + if (IS_ERR(vop2->rgb)) { + if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { + ret = PTR_ERR(vop2->rgb); + goto err_crtcs; + } + vop2->rgb = NULL; + } + } + rockchip_drm_dma_init_device(vop2->drm, vop2->dev); pm_runtime_enable(&pdev->dev); return 0; + +err_crtcs: + vop2_destroy_crtcs(vop2); + + return ret; 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Add separate nodes for the 16-bit and 18-bit version, respectively. While at it, split off the clock/sync signals from the data signals. The exact mapping of the data pins was discussed here: https://lore.kernel.org/linux-rockchip/f33a0488-528c-99de-3279-3c0346a03fd6@wolfvision.net/T/ Signed-off-by: Michael Riesch --- v3: - no changes v2: - no changes .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi index 8f90c66dd9e9..0a979bfb63d9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -3117,4 +3117,98 @@ tsadc_pin: tsadc-pin { <0 RK_PA1 0 &pcfg_pull_none>; }; }; + + lcdc { + /omit-if-no-ref/ + lcdc_clock: lcdc-clock { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data16: lcdc-data16 { + rockchip,pins = + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data18: lcdc-data18 { + rockchip,pins = + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + };