From patchwork Mon Jan 30 05:13:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 13120413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D237AC54EAA for ; Mon, 30 Jan 2023 05:18:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 30 Jan 2023 05:14:33 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 29 Jan 2023 21:14:29 -0800 From: Souradeep Chowdhury To: Andy Gross , Konrad Dybcio , Bjorn Andersson , "Alex Elder" CC: , , , Sai Prakash Ranjan , Sibi Sankar , "Rajendra Nayak" , , Souradeep Chowdhury Subject: [PATCH V3 1/3] soc: qcom: dcc: Add bootconfig support for DCC Date: Mon, 30 Jan 2023 10:43:55 +0530 Message-ID: <82087136234e84eb0e10f0f168e1edb171e6d692.1675054375.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: evnd_Dct-NUphLge4VTUMiQ2Z_LS2Eib X-Proofpoint-ORIG-GUID: evnd_Dct-NUphLge4VTUMiQ2Z_LS2Eib X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_03,2023-01-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 priorityscore=1501 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300049 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230129_211439_924114_50DAF345 X-CRM114-Status: GOOD ( 27.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bootconfig parser for DCC which is used to configure addresses in DCC during boot time. This is needed to debug crashes that can happen during boot-time. The expected format of a bootconfig file is as follows:- dcc_config { link_list_ { id = items =
, } } Example:- dcc_config { link_list_6 { id = 6 items = R_0x1781005c_1_apb, R_0x1782005c_1_apb } } Signed-off-by: Souradeep Chowdhury --- drivers/soc/qcom/Kconfig | 3 +- drivers/soc/qcom/dcc.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 21c4ce2..d11bda2 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -71,8 +71,9 @@ config QCOM_LLCC Say yes here to enable LLCC slice driver. config QCOM_DCC - tristate "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" + bool "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" depends on ARCH_QCOM || COMPILE_TEST + select BOOT_CONFIG help This option enables driver for Data Capture and Compare engine. DCC driver provides interface to configure DCC block and read back diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c index 5b50d63..93e8f86 100644 --- a/drivers/soc/qcom/dcc.c +++ b/drivers/soc/qcom/dcc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -148,6 +149,18 @@ struct dcc_cfg_loop_attr { bool loop_start; }; +static char *replace_char(char *str, char find, char replace) +{ + char *current_pos = strchr(str, find); + + while (current_pos) { + *current_pos = replace; + current_pos = strchr(current_pos, find); + } + + return str; +} + static inline u32 dcc_list_offset(int version) { return version == 1 ? 0x1c : version == 2 ? 0x2c : 0x34; @@ -1185,13 +1198,62 @@ static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) misc_deregister(&drvdata->sram_dev); } -static int dcc_probe(struct platform_device *pdev) +static int __init dcc_bootconfig_parse(struct dcc_drvdata *drvdata, struct xbc_node *dcc_node) +{ + struct xbc_node *linked_list, *node; + int curr_list, ret; + const char *p; + char *input, *token; + char val[30]; + + xbc_node_for_each_subkey(dcc_node, linked_list) { + p = xbc_node_find_value(linked_list, "id", &node); + if (p) { + ret = kstrtoint(p, 0, &curr_list); + if (ret) + return ret; + } else { + dev_err(drvdata->dev, "List number not specified\n"); + continue; + } + + p = xbc_node_find_value(linked_list, "items", &node); + if (!p) + continue; + xbc_array_for_each_value(node, p) { + strcpy(val, p); + input = replace_char(val, '_', ' '); + token = strsep(&input, " "); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, input, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, input, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, input, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, input, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + return -EINVAL; + } + if (ret) + return ret; + } + dcc_enable(drvdata, curr_list); + } + + return 0; +} + +static int __init dcc_probe(struct platform_device *pdev) { u32 val; int ret = 0, i; struct device *dev = &pdev->dev; struct dcc_drvdata *drvdata; struct resource *res; + struct xbc_node *dcc_node; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) @@ -1263,6 +1325,13 @@ static int dcc_probe(struct platform_device *pdev) dcc_create_debug_dir(drvdata); + dcc_node = xbc_find_node("dcc_config"); + if (dcc_node) { + ret = dcc_bootconfig_parse(drvdata, dcc_node); + if (ret) + dev_err(drvdata->dev, "DCC: Bootconfig parse error.\n"); + } + return 0; } @@ -1287,14 +1356,13 @@ static const struct of_device_id dcc_match_table[] = { MODULE_DEVICE_TABLE(of, dcc_match_table); static struct platform_driver dcc_driver = { - .probe = dcc_probe, .remove = dcc_remove, .driver = { .name = "qcom-dcc", .of_match_table = dcc_match_table, }, }; -module_platform_driver(dcc_driver); +module_platform_driver_probe(dcc_driver, dcc_probe); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); From patchwork Mon Jan 30 05:13:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 13120414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F641C54EED for ; Mon, 30 Jan 2023 05:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 30 Jan 2023 05:14:37 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 29 Jan 2023 21:14:33 -0800 From: Souradeep Chowdhury To: Andy Gross , Konrad Dybcio , Bjorn Andersson , "Alex Elder" CC: , , , Sai Prakash Ranjan , Sibi Sankar , "Rajendra Nayak" , , Souradeep Chowdhury Subject: [PATCH V3 2/3] soc: qcom: dcc: Add CTI-trigger support for DCC Date: Mon, 30 Jan 2023 10:43:56 +0530 Message-ID: <79ca9bbfb988445fda98ec23f4a63c562b07d04b.1675054375.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: H8EoiKRx_WcQh0teTfqygA8g0k0BjFFg X-Proofpoint-ORIG-GUID: H8EoiKRx_WcQh0teTfqygA8g0k0BjFFg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_03,2023-01-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 priorityscore=1501 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300049 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230129_211442_853768_006EAD33 X-CRM114-Status: GOOD ( 30.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CTI trigger is used to enable the Cross trigger interface for DCC. On enabling CTI trigger the dcc software trigger can be done by writing to CTI trig-out. Add the debugfs file ctitrigger which gives the user option to enable ctitrigger for a list. Also add hwtrigger debugfs file which needs to be disabled on enabling the CTI-trigger. Hwtrigger needs to be disabled for components to be able to write to cti-trigout. Signed-off-by: Souradeep Chowdhury --- Documentation/ABI/testing/debugfs-driver-dcc | 16 +++ drivers/soc/qcom/dcc.c | 148 ++++++++++++++++++++++++++- 2 files changed, 160 insertions(+), 4 deletions(-) diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc index 27ed591..6f5d965 100644 --- a/Documentation/ABI/testing/debugfs-driver-dcc +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -125,3 +125,19 @@ Description: on manual or crash induced triggers. Lists must be configured and enabled sequentially, e.g. list 2 can only be enabled when list 1 have so. + +What: /sys/kernel/debug/dcc/.../[list-number]/ctitrigger +Date: January 2023 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + ctitrigger. Ctitrigger can be enabled by writing + a '1' to the file. + +What: /sys/kernel/debug/dcc/.../[list-number]/hwtrigger +Date: January 2023 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + hwtrigger. Hwtrigger can be enabled by writing + a '1' to the file. diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c index 93e8f86..a75b9af 100644 --- a/drivers/soc/qcom/dcc.c +++ b/drivers/soc/qcom/dcc.c @@ -37,6 +37,7 @@ #define DCC_LL_INT_STATUS 0x1c #define DCC_LL_SW_TRIGGER 0x2c #define DCC_LL_BUS_ACCESS_STATUS 0x30 +#define DCC_CTI_TRIG 0x34 /* Default value used if a bit 6 in the HW_INFO register is set. */ #define DCC_FIX_LOOP_OFFSET 16 @@ -115,6 +116,8 @@ struct dcc_config_entry { * @nr_link_list: Total number of linkedlists supported by the DCC configuration * @loop_shift: Loop offset bits range for the addresses * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses + * @cti_bitmap: Bitmap to capture the cti-trigger status of each linked list of addresses + * @hwtrig_bitmap: Bitmap to capture the hwtrig status of each linked list of addresses */ struct dcc_drvdata { void __iomem *base; @@ -132,6 +135,8 @@ struct dcc_drvdata { size_t nr_link_list; u8 loop_shift; unsigned long *enable_bitmap; + unsigned long *cti_bitmap; + unsigned long *hwtrig_bitmap; }; struct dcc_cfg_attr { @@ -213,7 +218,10 @@ static int dcc_sw_trigger(struct dcc_drvdata *drvdata) if (!test_bit(i, drvdata->enable_bitmap)) continue; ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); - tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + if (drvdata->mem_map_ver != 3) + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + else + tmp_ll_cfg = ll_cfg & ~BIT(8); dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); dcc_list_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); @@ -590,6 +598,23 @@ static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) /* 5. Configure trigger */ dcc_list_writel(drvdata, DCC_TRIGGER_MASK, curr_list, DCC_LL_CFG); + if (drvdata->mem_map_ver == 3) { + dcc_list_writel(drvdata, test_bit(curr_list, drvdata->cti_bitmap), curr_list, + DCC_CTI_TRIG); + if (test_bit(curr_list, drvdata->hwtrig_bitmap)) + dcc_list_writel(drvdata, BIT(8), curr_list, DCC_LL_CFG); + else + dcc_list_writel(drvdata, (unsigned int)~BIT(8), curr_list, DCC_LL_CFG); + } else { + if (test_bit(curr_list, drvdata->hwtrig_bitmap)) + dcc_list_writel(drvdata, DCC_TRIGGER_MASK | + test_bit(curr_list, drvdata->cti_bitmap) << 8, + curr_list, DCC_LL_CFG); + else + dcc_list_writel(drvdata, ~DCC_TRIGGER_MASK & + test_bit(curr_list, drvdata->cti_bitmap) << 8, + curr_list, DCC_LL_CFG); + } out_unlock: mutex_unlock(&drvdata->mutex); @@ -1116,6 +1141,110 @@ static const struct file_operations config_fops = { .release = single_release, }; +static ssize_t ctitrigger_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + int curr_list; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + mutex_lock(&drvdata->mutex); + + if (test_bit(curr_list, drvdata->cti_bitmap)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t ctitrigger_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + if (test_bit(curr_list, drvdata->enable_bitmap)) + return -EBUSY; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) + set_bit(curr_list, drvdata->cti_bitmap); + else + clear_bit(curr_list, drvdata->cti_bitmap); + + return count; +} + +static const struct file_operations ctitrigger_fops = { + .read = ctitrigger_read, + .write = ctitrigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t hwtrigger_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + int curr_list; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + mutex_lock(&drvdata->mutex); + + if (test_bit(curr_list, drvdata->hwtrig_bitmap)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t hwtrigger_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + if (test_bit(curr_list, drvdata->enable_bitmap)) + return -EBUSY; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) + set_bit(curr_list, drvdata->hwtrig_bitmap); + else + clear_bit(curr_list, drvdata->hwtrig_bitmap); + + return count; +} + +static const struct file_operations hwtrigger_fops = { + .read = hwtrigger_read, + .write = hwtrigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) { debugfs_remove_recursive(drvdata->dbg_dir); @@ -1145,6 +1274,8 @@ static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) debugfs_create_file("ready", 0400, drvdata->dbg_dir, drvdata, &ready_fops); debugfs_create_file("config_reset", 0200, drvdata->dbg_dir, drvdata, &config_reset_fops); + debugfs_create_file("ctitrigger", 0600, list, drvdata, &ctitrigger_fops); + debugfs_create_file("hwtrigger", 0600, list, drvdata, &hwtrigger_fops); } static ssize_t dcc_sram_read(struct file *file, char __user *data, @@ -1304,18 +1435,27 @@ static int __init dcc_probe(struct platform_device *pdev) mutex_init(&drvdata->mutex); - drvdata->enable_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drvdata->nr_link_list), - sizeof(*drvdata->enable_bitmap), GFP_KERNEL); + drvdata->enable_bitmap = devm_bitmap_alloc(dev, drvdata->nr_link_list, GFP_KERNEL); if (!drvdata->enable_bitmap) return -ENOMEM; + drvdata->cti_bitmap = devm_bitmap_alloc(dev, drvdata->nr_link_list, GFP_KERNEL); + if (!drvdata->cti_bitmap) + return -ENOMEM; + + drvdata->hwtrig_bitmap = devm_bitmap_alloc(dev, drvdata->nr_link_list, GFP_KERNEL); + if (!drvdata->hwtrig_bitmap) + return -ENOMEM; + drvdata->cfg_head = devm_kcalloc(dev, drvdata->nr_link_list, sizeof(*drvdata->cfg_head), GFP_KERNEL); if (!drvdata->cfg_head) return -ENOMEM; - for (i = 0; i < drvdata->nr_link_list; i++) + for (i = 0; i < drvdata->nr_link_list; i++) { INIT_LIST_HEAD(&drvdata->cfg_head[i]); + set_bit(i, drvdata->hwtrig_bitmap); + } ret = dcc_sram_dev_init(drvdata); if (ret) { From patchwork Mon Jan 30 05:13:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 13120419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39105C54EAA for ; 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Mon, 30 Jan 2023 05:14:41 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30U5Efs7004535 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 05:14:41 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 29 Jan 2023 21:14:37 -0800 From: Souradeep Chowdhury To: Andy Gross , Konrad Dybcio , Bjorn Andersson , "Alex Elder" CC: , , , Sai Prakash Ranjan , Sibi Sankar , "Rajendra Nayak" , , Souradeep Chowdhury Subject: [PATCH V3 3/3] soc: qcom: dcc: Add QAD support for DCC Date: Mon, 30 Jan 2023 10:43:57 +0530 Message-ID: <8d9de5e2089b7fc0245a56f5457b443d2042977f.1675054375.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7BFsqGLBFBxm9X8uM7BZ6-w1mRHYVcXG X-Proofpoint-ORIG-GUID: 7BFsqGLBFBxm9X8uM7BZ6-w1mRHYVcXG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_03,2023-01-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300049 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230129_211446_208469_2944D2B9 X-CRM114-Status: GOOD ( 26.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add QAD debugfs file for DCC which can be used to enable/disable the QAD for a list. QAD is used to specify the access control for DCC configurations, on enabling it the access control to dcc configuration space is restricted. On setting the QAD value, the list gets locked out for a particular component and cannot be used by the rest. Signed-off-by: Souradeep Chowdhury --- Documentation/ABI/testing/debugfs-driver-dcc | 8 ++++ drivers/soc/qcom/dcc.c | 68 ++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc index 6f5d965..a3c4657 100644 --- a/Documentation/ABI/testing/debugfs-driver-dcc +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -141,3 +141,11 @@ Description: This debugfs interface is used for enabling the hwtrigger. Hwtrigger can be enabled by writing a '1' to the file. + +What: /sys/kernel/debug/dcc/.../[list-number]/QAD +Date: January 2023 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + QAD. QAD can be enabled by writing a '1' to the + file. diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c index a75b9af..eeeaa8b 100644 --- a/drivers/soc/qcom/dcc.c +++ b/drivers/soc/qcom/dcc.c @@ -38,6 +38,7 @@ #define DCC_LL_SW_TRIGGER 0x2c #define DCC_LL_BUS_ACCESS_STATUS 0x30 #define DCC_CTI_TRIG 0x34 +#define DCC_QAD_OUTPUT 0x38 /* Default value used if a bit 6 in the HW_INFO register is set. */ #define DCC_FIX_LOOP_OFFSET 16 @@ -118,6 +119,7 @@ struct dcc_config_entry { * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses * @cti_bitmap: Bitmap to capture the cti-trigger status of each linked list of addresses * @hwtrig_bitmap: Bitmap to capture the hwtrig status of each linked list of addresses + * @qad_bitmap: Bitmap to capture the qad status of each linked list of addresses */ struct dcc_drvdata { void __iomem *base; @@ -137,6 +139,7 @@ struct dcc_drvdata { unsigned long *enable_bitmap; unsigned long *cti_bitmap; unsigned long *hwtrig_bitmap; + unsigned long *qad_bitmap; }; struct dcc_cfg_attr { @@ -599,6 +602,8 @@ static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) dcc_list_writel(drvdata, DCC_TRIGGER_MASK, curr_list, DCC_LL_CFG); if (drvdata->mem_map_ver == 3) { + dcc_list_writel(drvdata, test_bit(curr_list, drvdata->qad_bitmap), curr_list, + DCC_QAD_OUTPUT); dcc_list_writel(drvdata, test_bit(curr_list, drvdata->cti_bitmap), curr_list, DCC_CTI_TRIG); if (test_bit(curr_list, drvdata->hwtrig_bitmap)) @@ -1245,6 +1250,64 @@ static const struct file_operations hwtrigger_fops = { .llseek = generic_file_llseek, }; +static ssize_t qad_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + int curr_list; + + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + mutex_lock(&drvdata->mutex); + + if (test_bit(curr_list, drvdata->qad_bitmap)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t qad_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + + if (drvdata->mem_map_ver != 3) { + dev_err(drvdata->dev, "QAD is not supported\n"); + return -EINVAL; + } + + if (test_bit(curr_list, drvdata->enable_bitmap)) + return -EBUSY; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) + set_bit(curr_list, drvdata->qad_bitmap); + else + clear_bit(curr_list, drvdata->qad_bitmap); + + return count; +} + +static const struct file_operations qad_fops = { + .read = qad_read, + .write = qad_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) { debugfs_remove_recursive(drvdata->dbg_dir); @@ -1276,6 +1339,7 @@ static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) drvdata, &config_reset_fops); debugfs_create_file("ctitrigger", 0600, list, drvdata, &ctitrigger_fops); debugfs_create_file("hwtrigger", 0600, list, drvdata, &hwtrigger_fops); + debugfs_create_file("QAD", 0600, list, drvdata, &qad_fops); } static ssize_t dcc_sram_read(struct file *file, char __user *data, @@ -1447,6 +1511,10 @@ static int __init dcc_probe(struct platform_device *pdev) if (!drvdata->hwtrig_bitmap) return -ENOMEM; + drvdata->qad_bitmap = devm_bitmap_alloc(dev, drvdata->nr_link_list, GFP_KERNEL); + if (!drvdata->qad_bitmap) + return -ENOMEM; + drvdata->cfg_head = devm_kcalloc(dev, drvdata->nr_link_list, sizeof(*drvdata->cfg_head), GFP_KERNEL); if (!drvdata->cfg_head)