From patchwork Mon Jan 30 20:27:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13121783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 222C1C54EAA for ; Mon, 30 Jan 2023 20:28:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=NTJmdCUQb82mZmDUhC0tpaXQ8okczaqLyXV+t/3bMzM=; b=PTK1Lv092p8rptt5phfg+WQ9FA cV8Su3GMGl+XxLfjOUp31dPPzzUHb6u6BTH32cPH8wtBAZgNhuoLJSELDieErGnzovwgYEBOGSHr1 XKHiWeFrRp3KzZKgr/e5rGyh+V+JP4d0KpVBb7CyynHx/ztt6p2w696YRJsdI2xYD8n2VejWpUChi yXS6jlowi9cFp1cGiNdEhEAOSfI+z4Hr4BRja1lIZv6TixM7AirBwoTraRNMWUR2+7PQp7pZJaFh6 vgUzaxTDCqH1WC0+Ng21YAwixoBH8iFH82m0etnnLoB9LDOB1f7vNp8D3rpErvuJzuxOog8HgqSkl Lcfu8Fvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pMalC-005MCK-Sv; Mon, 30 Jan 2023 20:28:14 +0000 Received: from mail-qt1-x836.google.com ([2607:f8b0:4864:20::836]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pMal9-005MB5-Kl for linux-mediatek@lists.infradead.org; Mon, 30 Jan 2023 20:28:13 +0000 Received: by mail-qt1-x836.google.com with SMTP id j9so11385351qtv.4 for ; Mon, 30 Jan 2023 12:28:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NTJmdCUQb82mZmDUhC0tpaXQ8okczaqLyXV+t/3bMzM=; b=JEMvSA7P4/hJx8magoKFs9RZCvbKWj5HxKUu7ZOjjNM3yG6Qr1wHobXyqioVDJnL5R DNcXEHUk0VE1RAagd/sOma74WfJWfvwq2KgzJ1sVT7DUM1ERjasIQ2ym4P7Fniyq4jWc 8zpvxvn6+6gojLxeAJfWFmL/8KK2jM3tAELQI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NTJmdCUQb82mZmDUhC0tpaXQ8okczaqLyXV+t/3bMzM=; b=xUgYgdxCNFthT2EcAKl2AAt5XrQooalMSfJOsTOWMDeXhlRuKYgjaJ0efs2nNO0l22 ARRnKye5ee6dSviuukF6/Iqqk2l8lUEj+cnpmCpaMvM+ilWYiiHtWtIG60tq8N5XHPhr /WhUHxXRAkpzM/JWKVLxUiwla8sRCwYbf9tm0DLMdDx03C2m215Dt4ezgmP23mjAxvHp rbmdxrnLcYpgvZuPCeSQtXUvLFS7KLIKgSYe1CL28XRASjJ4XgLSvXfY41fbzakqkDN5 4QJ6LzSkRwCPpX2hPUVp34F3GQAvgTqiPYabNyM7ozF3SZKwwR6IYjgt8t7+ZicAz7fG ekHg== X-Gm-Message-State: AO0yUKWCijdFTkX3JhcWCC7rntGg+0oq1xnkAFHYBOrVz1WZ6fynnX9Y AcMWRmdsstRpJCRmJApvQePhjt44W8ING2oj X-Google-Smtp-Source: AK7set9tV3WmNseTCFWLx0QPH2QJDagq2IYaQv2q93buj5E1OcPXwHWpWfj1C0yqTL0l/5wzzdJZbA== X-Received: by 2002:a05:622a:1911:b0:3b8:68fa:afc6 with SMTP id w17-20020a05622a191100b003b868faafc6mr9757041qtc.29.1675110488484; Mon, 30 Jan 2023 12:28:08 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:e3ef:428c:a2ae:5271]) by smtp.gmail.com with ESMTPSA id x124-20020a379582000000b006cbc00db595sm8663123qkd.23.2023.01.30.12.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 12:28:08 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com, daniel@ffwll.ch, daniel@fooishbar.org, greenjustin@chromium.org Subject: [PATCH v4] drm/mediatek: Add support for AR30 and BA30 Date: Mon, 30 Jan 2023 15:27:49 -0500 Message-Id: <20230130202749.1910612-1-greenjustin@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_122811_740579_03EAB9E6 X-CRM114-Status: GOOD ( 18.35 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver. Tested using "modetest -P" on an MT8195. Signed-off-by: Justin Green --- v2: * Rebase and resolve merge conflicts with the AFBC patch. v3: * Moved 10-bit support detection to mtk_disk_ovl.c v4: * Moved formats to mtk_disp_ovl.c and mtk_disp_rdma.c drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 75 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 20 ++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 28 +++----- drivers/gpu/drm/mediatek/mtk_drm_plane.h | 3 +- 8 files changed, 146 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 33e61a136bbc..c292022b8270 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -96,6 +96,8 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +const u32* mtk_ovl_get_formats(struct device *dev); +size_t mtk_ovl_get_num_formats(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); @@ -122,4 +124,6 @@ void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt); void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, struct cmdq_pkt *cmdq_pkt); +const u32* mtk_rdma_get_formats(struct device *dev); +size_t mtk_rdma_get_num_formats(struct device *dev); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 84daeaffab6a..781cd18f94ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,11 +62,45 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) +static const u32 formats_mt8173[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + +static const u32 formats_mt8195[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -73,6 +108,7 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + bool supports_10bit; }; /* @@ -188,6 +224,26 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -216,6 +272,21 @@ unsigned int mtk_ovl_supported_rotations(struct device *dev) DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } +const u32* mtk_ovl_get_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->supports_10bit ? formats_mt8195 : formats_mt8173; +} + +size_t mtk_ovl_get_num_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->supports_10bit ? ARRAY_SIZE(formats_mt8195) + : ARRAY_SIZE(formats_mt8173); +} + int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state) { @@ -302,9 +373,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -388,6 +461,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); } @@ -541,6 +615,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, + .supports_10bit = true, }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 0ec2e4049e07..fb38e54601df 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -54,8 +54,23 @@ #define RDMA_MEM_GMC 0x40402020 +static const u32 formats_mt8173[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_rdma_data { unsigned int fifo_size; + bool supports_10bit; }; /* @@ -262,6 +277,17 @@ void mtk_rdma_layer_config(struct device *dev, unsigned int idx, } +// TODO: Add support for 10 bit mode. +const u32* mtk_rdma_get_formats(struct device *dev) +{ + return formats_mt8173; +} + +size_t mtk_rdma_get_num_formats(struct device *dev) +{ + return ARRAY_SIZE(formats_mt8173); +} + static int mtk_disp_rdma_bind(struct device *dev, struct device *master, void *data) { @@ -372,6 +398,7 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { .fifo_size = 1920, + .supports_10bit = true, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 112615817dcb..2ba01c484228 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -856,7 +856,9 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, BIT(pipe), mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, num_planes), - mtk_ddp_comp_supported_rotations(comp)); + mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_formats(comp), + mtk_ddp_comp_get_num_formats(comp)); if (ret) return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6b6d5335c834..4a4c1928f83d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -359,6 +359,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .layer_config = mtk_ovl_layer_config, .bgclr_in_on = mtk_ovl_bgclr_in_on, .bgclr_in_off = mtk_ovl_bgclr_in_off, + .get_formats = mtk_ovl_get_formats, + .get_num_formats = mtk_ovl_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_postmask = { @@ -381,6 +383,8 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = { .disable_vblank = mtk_rdma_disable_vblank, .layer_nr = mtk_rdma_layer_nr, .layer_config = mtk_rdma_layer_config, + .get_formats = mtk_rdma_get_formats, + .get_num_formats = mtk_rdma_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_ufoe = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2d0052c23dcb..c015b087bac6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -71,6 +71,8 @@ struct mtk_ddp_comp_funcs { void (*bgclr_in_off)(struct device *dev); void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); + const u32* (*get_formats)(struct device *dev); + size_t (*get_num_formats)(struct device *dev); }; struct mtk_ddp_comp { @@ -151,6 +153,24 @@ unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp) return 0; } +static inline +const u32* mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_formats) + return comp->funcs->get_formats(comp->dev); + + return NULL; +} + +static inline +size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_num_formats) + return comp->funcs->get_num_formats(comp->dev); + + return 0; +} + static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->layer_nr) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index d54fbf34b000..fe9ac670f1e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -19,20 +19,6 @@ #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -static const u32 formats[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_BGRX8888, - DRM_FORMAT_BGRA8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_UYVY, - DRM_FORMAT_YUYV, -}; - static const u64 modifiers[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | @@ -315,13 +301,21 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations) + unsigned int supported_rotations, const u32* formats, + size_t num_formats) { int err; + if (!formats || !num_formats) { + DRM_ERROR("no pixel formats for plane\n"); + return -EINVAL; + } + err = drm_universal_plane_init(dev, plane, possible_crtcs, - &mtk_plane_funcs, formats, - ARRAY_SIZE(formats), modifiers, type, NULL); + &mtk_plane_funcs, + formats, num_formats, + modifiers, type, NULL); + if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 8f39011cdbfc..1740ccdeabce 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -48,6 +48,7 @@ to_mtk_plane_state(struct drm_plane_state *state) int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations); + unsigned int supported_rotations, const u32* formats, + size_t num_formats); #endif