From patchwork Fri Feb 3 05:58:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13127013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82E66C61DA4 for ; Fri, 3 Feb 2023 05:59:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNp6d-0005MM-Vq; Fri, 03 Feb 2023 00:59:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNp6c-0005HB-BR for qemu-devel@nongnu.org; Fri, 03 Feb 2023 00:59:26 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNp6a-0003CX-D4 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 00:59:26 -0500 Received: by mail-wr1-x434.google.com with SMTP id r2so3671840wrv.7 for ; Thu, 02 Feb 2023 21:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Pu4CS8ZEwxyDoWSGcKVuwnDbAFzTS1eeQ8iquNKhHg=; b=W9YEVz7ALYGNvrs8tK6HA1zRcAlt7CEecObuEH5o0/WQRsZLhd14jEKmaUq3QsvnGu afU7PsneECjGYfXplcwT3POM68Lzis4Kph1APm0z+maFGQPW3j6oq/IupepWJbW2ekT0 gSljQt2vs+++YclAWlaBcMf4Phd3uLyF08bh6flI/imGp4GzkfJWo/JibnMGHimD+vyE ep4umgNSxf6H/hOTIk51EDHezYjeLT+SNT9ULZnT48Y+PfyOrmubh7mkCS3UDxwVtF5q jeGYfzzmmZ2yz01C5/cOb7zLXWNXfZmfcsotEOjdxDDsl00asgSiFLlbslWxu5c2NlMP QBNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Pu4CS8ZEwxyDoWSGcKVuwnDbAFzTS1eeQ8iquNKhHg=; b=OJldY1JrXduZ1JqkMPJ4xhMxvZeoySphSiZIDFAJhAHVz8tbJQ1prHyRVeKCHk/yY7 wlHniv9t0j62qo1wNU/6SSvjyrQrU3Pt5pdmAapKGyRRhDeYtDzOPE4wXCQH3f3ltiVF 9B+84HKn6XQaW8M3/nS84WUe6Ph4CHa1AhBQn2GOMngrFABi2HKYqrZUQeE6sA+CNOv7 FgZ4tFxLIHSxQQNx6zRQ5r0r+cpJGvDCWOPSdGd7GgBbejnVOO/oYUd0n7AmQLPC8hn7 R1YDDU7cXp2Td/Vc6LfN9as8TwP0LitVF6RV6t3tmaJKxl9fWe1RI0+p1LjvXSy/E81n tA4A== X-Gm-Message-State: AO0yUKX326GWPwMiAbtn4aPTQJBV2Zc2+lKosdOgl+SnyIQHm18ofCym vlWvf81RanByD13h3XFf2H3GUg== X-Google-Smtp-Source: AK7set9ysWSCrhiZlBOiMb2K/6X1HJzfk34winp4HGDHzWoOpvkIIysfwz/HwnZp+HpP84ygeRV18g== X-Received: by 2002:a05:6000:a1a:b0:2bf:e5cc:91c1 with SMTP id co26-20020a0560000a1a00b002bfe5cc91c1mr8388456wrb.52.1675403962959; Thu, 02 Feb 2023 21:59:22 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b002bfbf4c3f9fsm1171694wrb.17.2023.02.02.21.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 21:59:22 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v10 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Fri, 3 Feb 2023 06:58:08 +0100 Message-Id: <20230203055812.257458-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203055812.257458-1-alexghiti@rivosinc.com> References: <20230203055812.257458-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); From patchwork Fri Feb 3 05:58:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13127014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15D79C636CC for ; Fri, 3 Feb 2023 06:00:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNp7x-0006Xx-5C; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id z1-20020a5d4c81000000b002bdd8f12effsm1115081wrs.30.2023.02.02.22.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 22:00:23 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v10 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Fri, 3 Feb 2023 06:58:09 +0100 Message-Id: <20230203055812.257458-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203055812.257458-1-alexghiti@rivosinc.com> References: <20230203055812.257458-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; From patchwork Fri Feb 3 05:58:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13127015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B986C61DA4 for ; Fri, 3 Feb 2023 06:01:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNp8c-0006x8-UZ; Fri, 03 Feb 2023 01:01:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNp8a-0006wM-Ed for qemu-devel@nongnu.org; Fri, 03 Feb 2023 01:01:28 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNp8Y-0004JF-8z for qemu-devel@nongnu.org; Fri, 03 Feb 2023 01:01:28 -0500 Received: by mail-wm1-x329.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso5289133wms.0 for ; Thu, 02 Feb 2023 22:01:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XMDPia3DQWgs9YjKD/wIXB4n4PGGmUJYm65S8iLUMjg=; b=GjItyZic7uat/ejV1HCK1KFi7Oo4vENCuh8P+l18K1QfquttrzpVZB50+pRgKRV3F8 AAIr30gSLX7jwTe7r8FmvotlGcMx1jeIG1tYPqm2JNrnHd40gXeteEeUtXfqCCq21hgZ TJeLLhaQmXNI3CvV/XSt4/g0ekFyYE0xmllMvUvXxdk1MudSD47ZnqT8DfrXZUeevu4g uw2L4TZZx8DVhwhpu7WaqxRcP69bGr+yG64bPNwF8kZ00CaC0ydEX+TDrUXf6EHf2rUz z9EVc2j7QR+Ng3KKuNZebxUYtabRwT61wmwO70x5lITDN0Gqn77x0FCzMBLzltIFbTta wbVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XMDPia3DQWgs9YjKD/wIXB4n4PGGmUJYm65S8iLUMjg=; b=wcqJh+hioZikc06/cxZb9QMa7+lvLUGVrRQonBkyKRTrzEmxSJqbbQG3jpsmDAfSCs 0QrZi+L7eHUl3NvHGBZGemzdROZZmTK5d5pLxygGjue6EwfW+q75mNWb2UBlOdfUgaMg 0C1ZHFwdUuFkrs+L2w9yqBmmNyl07vNkqj/9YfCR35eCx6VbtQbW0n2MRiFMD0XZCCST tVpuezvGlI/ETrvhDMC/ZDwygY0l0jmUP4WS2V7WTJTIxV5BY3cntBTPKi4h8KgARzqE buCIjaMiGKWUrb5TqNBu5F7gUfN7RZGv96OWA1dtaqLafJXPhJpISkNgUNFO8YqjXmeU ulEA== X-Gm-Message-State: AO0yUKWkpgKmgbnlqcEN8ULfc35JXc7Jyqvu2oFoHyLpB33ZlC6OpoAn bIcVo843nwpoyGrNXlHHLIPQlA== X-Google-Smtp-Source: AK7set+beN9KpB/3nOP608vXxiImxg8SiD4ki2HYlTNvQaV4AGXIlCMlFQaBRfV4VQJqQKvg04DUzw== X-Received: by 2002:a05:600c:3b89:b0:3dc:19d1:3c13 with SMTP id n9-20020a05600c3b8900b003dc19d13c13mr8202907wms.12.1675404084803; Thu, 02 Feb 2023 22:01:24 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id bw17-20020a0560001f9100b002be25db0b7bsm1155817wrb.10.2023.02.02.22.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 22:01:24 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry , Bin Meng Subject: [PATCH v10 3/5] riscv: Allow user to set the satp mode Date: Fri, 3 Feb 2023 06:58:10 +0100 Message-Id: <20230203055812.257458-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203055812.257458-1-alexghiti@rivosinc.com> References: <20230203055812.257458-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 215 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 21 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 241 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..56057cf87c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,83 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +#ifndef CONFIG_USER_ONLY +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + } +} +#endif + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +697,87 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +#ifndef CONFIG_USER_ONLY +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map == 0) { + if (cpu->cfg.satp_mode.init == 0) { + /* If unset by the user, we fallback to the default satp mode. */ + set_satp_mode_default_map(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.map |= (1 << i); + } + } +} +#endif + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ +#ifndef CONFIG_USER_ONLY + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +#endif +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1078,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -928,6 +1093,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = satp_map->map & (1 << satp); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + static void riscv_cpu_set_irq(void *opaque, int irq, int level) { RISCVCPU *cpu = RISCV_CPU(opaque); @@ -1091,6 +1302,10 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + +#ifndef CONFIG_USER_ONLY + riscv_add_satp_mode_properties(obj); +#endif } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..df6d9e06e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,10 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + +#ifndef CONFIG_USER_ONLY + RISCVSATPMap satp_mode; +#endif }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +810,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..f9eff3f1e3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; - } else { - return valid_vm_1_10_64[vm & 0xf]; - } + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); + + return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map); } static RISCVException write_mstatus(CPURISCVState *env, int csrno, From patchwork Fri Feb 3 05:58:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13127016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67622C61DA4 for ; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c445100b003dc433355aasm1762707wmn.18.2023.02.02.22.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 22:02:25 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v10 4/5] riscv: Introduce satp mode hw capabilities Date: Fri, 3 Feb 2023 06:58:11 +0100 Message-Id: <20230203055812.257458-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203055812.257458-1-alexghiti@rivosinc.com> References: <20230203055812.257458-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 91 +++++++++++++++++++++++++++++++++------------- target/riscv/cpu.h | 8 +++- 2 files changed, 72 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 56057cf87c..7e9924ede9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -293,18 +293,24 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default_map(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } + +/* Set the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; +} #endif static void riscv_any_cpu_init(Object *obj) @@ -315,6 +321,13 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); +#endif + set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); } @@ -328,6 +341,9 @@ static void rv64_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); +#endif } static void rv64_sifive_u_cpu_init(Object *obj) @@ -335,6 +351,9 @@ static void rv64_sifive_u_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); +#endif } static void rv64_sifive_e_cpu_init(Object *obj) @@ -345,6 +364,9 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } static void rv128_base_cpu_init(Object *obj) @@ -361,6 +383,9 @@ static void rv128_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); +#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -371,6 +396,9 @@ static void rv32_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif } static void rv32_sifive_u_cpu_init(Object *obj) @@ -378,6 +406,9 @@ static void rv32_sifive_u_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif } static void rv32_sifive_e_cpu_init(Object *obj) @@ -388,6 +419,9 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } static void rv32_ibex_cpu_init(Object *obj) @@ -398,6 +432,9 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif cpu->cfg.epmp = true; } @@ -409,6 +446,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } #endif @@ -701,8 +741,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { if (cpu->cfg.satp_mode.init == 0) { @@ -715,9 +756,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * valid_vm_1_10_32/64. */ for (int i = 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -728,37 +770,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } /* Finally expand the map so that all valid modes are set */ - for (int i = satp_mode_max - 1; i >= 0; --i) { - if (valid_vm[i]) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { + if (cpu->cfg.satp_mode.supported & (1 << i)) { cpu->cfg.satp_mode.map |= (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df6d9e06e4..defc5769b5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { From patchwork Fri Feb 3 05:58:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13127021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EFDDC61DA4 for ; Fri, 3 Feb 2023 06:03:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNpAo-0000qF-1v; Fri, 03 Feb 2023 01:03:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNpAY-0000eT-5x for qemu-devel@nongnu.org; Fri, 03 Feb 2023 01:03:33 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNpAW-0004jR-Ho for qemu-devel@nongnu.org; Fri, 03 Feb 2023 01:03:29 -0500 Received: by mail-wm1-x32f.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so3075546wms.1 for ; Thu, 02 Feb 2023 22:03:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l07L9j5mbC+S0Ouimd3iEDbL6jla8YQbRQof+qtKkPE=; b=PxUeGSYiSs01TNKRkQ/kba3SX9s7MVjtBAz8CS1goRcYK05P5WguKta1uBBGo3kzS8 Rkg8+adNr/v/rpYrJ8xSO4lWpNpoYeREDNf6893yh8JIS6tFjxfzrTJAtEd4j5fzIokP vP3+xSncGhgAw5dTpQxJfHDm0zdlMQ2l2JdOZzYr1SOS9fGSCQb4te/Lhm0qgO3Rkpuw ifq8/1BG4rC4isLkntjzjzBWPvnbAiF9/NQc0gZvJdBLg/3mF7ZxfmmW9RPRmSoOFTNQ A6alNpDRh1YqJrFGVChRRZI0S9F8u41gzSl4HtKzCqvlFeSXKbvBnfquMDUA8nMl4Mnr AK9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l07L9j5mbC+S0Ouimd3iEDbL6jla8YQbRQof+qtKkPE=; b=B8JigqI8UItYjPA0TnP9CtybWueuUqiTnm2c+QuN6Ugr2jDm4FZSkO2Nnsb/dQzq2Z 1MFftJew/6lZZKwbPgXSSvqseSjEFAMR6/inCcc08VRmus5jyypRpD5Hp5qr/zvyvpSe EKtT5VN1oCwZCZnXp1ZxE3nHvyry2Jyrq2PR861iq9Nvu4pu2kdcfqmg2YTmkLhZJV4Y l1R/qIDJoSvbCiGPB7K4uVaBpAeL8sB/SMUpSVEa6tClU2ZGxBbEU+n8U/IZgap/+sQa 4RsUnVwr2xAzBu5YSFaLyIx5GQYpVL9HG+NXIzV7q4ndZSxNrWBGlB5qRRbD/7YwlQzV DIQw== X-Gm-Message-State: AO0yUKVZTz1QTw0QW0jNtevxq8K3VG1sZJYD3ouBJkWLUe1M8WgNxaht Cu9yIcoEomcJSY7flQYuIaMnfA== X-Google-Smtp-Source: AK7set9UMNuWKcygQpr4Fyh2lLIQ5KnU+N0GNK/WSZu7GebEuJIcpFjr6X6cHMrpxaVDkU8DcaB6zQ== X-Received: by 2002:a05:600c:4f51:b0:3d1:f16d:5848 with SMTP id m17-20020a05600c4f5100b003d1f16d5848mr8399013wmq.26.1675404206606; Thu, 02 Feb 2023 22:03:26 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id w14-20020a05600c474e00b003dfe57f6f61sm1159131wmo.33.2023.02.02.22.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 22:03:26 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v10 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Fri, 3 Feb 2023 06:58:12 +0100 Message-Id: <20230203055812.257458-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203055812.257458-1-alexghiti@rivosinc.com> References: <20230203055812.257458-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); - } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + satp_mode_max = satp_mode_max_from_map( + s->soc[socket].harts[cpu].cfg.satp_mode.map); + sv_name = g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_bit)); + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); + g_free(sv_name); + name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name);