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Wed, 8 Feb 2023 03:17:15 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:15 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:08 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 1/5] dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq Date: Wed, 8 Feb 2023 16:46:41 +0530 Message-ID: <20230208111645.3863534-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT038:EE_|PH8PR12MB6868:EE_ X-MS-Office365-Filtering-Correlation-Id: 0021138e-f15f-4e10-dbbc-08db09c6112b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:29.7287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0021138e-f15f-4e10-dbbc-08db09c6112b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6868 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jeffy Chen Add device tree support to pass PCIe WAKE# pin information to PCI core driver. To support PCIe WAKE# and PCI irqs, add definition of the optional properties "interrupts" and "interrupt-names". These properties should be defined by the PCIe port to which wake capable Endpoint is connected, so the definition is added under "PCI-PCI Bridge properties" section. Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy Reviewed-by: Rob Herring --- Changes in v14: Move the device tree properties definition to "PCI-PCI Bridge properties" section and also update commit message. Changes in v13: None Changes in v12: Only add irq definitions for PCI devices and rewrite the commit message. Changes in v11: None Changes in v10: None Changes in v9: Add section for PCI devices and rewrite the commit message. Changes in v8: Add optional "pci", and rewrite commit message. Changes in v7: None Changes in v6: None Changes in v5: Move to pci.txt Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..53bd559a7305 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -71,6 +71,14 @@ Optional properties: trusted with relaxed DMA protection, as users could easily attach malicious devices to this port. +- interrupts: Interrupt specifier for each name in interrupt-names. +- interrupt-names: + May contain "wakeup" for PCIe WAKE# interrupt and "pci" for PCI interrupt. + The PCI devices may optionally include an 'interrupts' property that + represents the legacy PCI interrupt. And when we try to specify the PCIe + WAKE# pin, a corresponding 'interrupt-names' property is required to + distinguish them. + Example: pcie@10000000 { From patchwork Wed Feb 8 11:16:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 13132986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73DA9C6379F for ; Wed, 8 Feb 2023 11:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbjBHLTX (ORCPT ); Wed, 8 Feb 2023 06:19:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231161AbjBHLS3 (ORCPT ); Wed, 8 Feb 2023 06:18:29 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on20618.outbound.protection.outlook.com [IPv6:2a01:111:f400:7eab::618]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F11D1EFAD; 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Wed, 8 Feb 2023 03:17:23 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:22 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:15 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 2/5] of/irq: Adjust of_pci_irq parsing for multiple interrupts Date: Wed, 8 Feb 2023 16:46:42 +0530 Message-ID: <20230208111645.3863534-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT102:EE_|DM4PR12MB5962:EE_ X-MS-Office365-Filtering-Correlation-Id: e99e9885-9c41-4aec-3964-08db09c611bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:30.7776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e99e9885-9c41-4aec-3964-08db09c611bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT102.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5962 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jeffy Chen Currently we are considering the first irq as the PCI interrupt pin, but a PCI device may have multiple interrupts(e.g. PCIe WAKE# pin). Only parse the PCI interrupt pin when the irq is unnamed or named as "pci". Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy Reviewed-by: Thierry Reding --- Changes in v14: Address Rob's comment on using of_property_match_string(). Changes in v13: None Changes in v12: None Changes in v11: Address Brian's comments. Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v3: None Changes in v2: None drivers/pci/of.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 196834ed44fe..ff897c40ed71 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -429,9 +429,17 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args * */ dn = pci_device_to_OF_node(pdev); if (dn) { - rc = of_irq_parse_one(dn, 0, out_irq); - if (!rc) - return rc; + int index = 0; + + index = of_property_match_string(dn, "interrupt-names", "pci"); + if (index == -EINVAL) /* Property doesn't exist */ + index = 0; + + if (index >= 0) { + rc = of_irq_parse_one(dn, index, out_irq); + if (!rc) + return rc; + } } /* From patchwork Wed Feb 8 11:16:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 13132988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B48EC64ED8 for ; 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Wed, 8 Feb 2023 03:17:23 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 3/5] PCI / PM: Add support for the PCIe WAKE# signal for OF Date: Wed, 8 Feb 2023 16:46:43 +0530 Message-ID: <20230208111645.3863534-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT025:EE_|PH8PR12MB8430:EE_ X-MS-Office365-Filtering-Correlation-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KBSganwMsDHwq1PLZl82ZCRCuX173DJSDwwjRlWrkaC0wJ+V1n8CVjzbsbzSQJ/CHs9uSSvnUewlcUwCt0MwV2huInIyb9+RdhjI3EhcLfnFh9Gs1NYBTSidyZUADhv0pxd3K6TXvIDa1IRH/BsrlGp40Dt862sGy5wwmCOmmsndApjtMddozBmcTo4bEsVWWgwPHiR6AiXYWHDE0GcdBAkJ1NGgjWMyuWjrHYRFGDgt1dHYVMmG9c5gYPDs7p6kASMW2NomScCXlPqmsoKuEKF4Fb7Mq2j9+ypaykV2oc5kDtZs4kDI+t6v/NCb8SPpfovL6uSJ/Y01NDg/Wue2V6/saw5opr7o9+3mqtpJa7TkSpt7F4XlEo7XE+CTWoCko7nPhg+Rha85Ir6t2fQUXVUrg2KzxE5MImxTP8NJO7SEiXjPQ2KfAWajeAxFdgivZ1Tx4nVIC+tm7yvOziPZJAhE/yzKvfVtXcTSNNMTTVMF0c92V46UIpdVuBCNBmdxwcinxN8SEVIQsyRX5EBsMnapxFGYQENEwmd6NGn3DneCujYcPqC2+GE03nmDaXJ3KhnztfqK1pHZp1rM04dGlcSvE+/Wbq5J3+tIz6uc2Tt1AhFGRVagxFW1+zHDpkXr7gsfFI1MgDnnXhSojgqdqdXeNUoEeUMbMgi+livdPZT8vR7feT4W34MCzqXuF/4UJNdGdo1ZIW6aCVbTpSaifw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(396003)(39860400002)(136003)(346002)(451199018)(46966006)(36840700001)(40470700004)(5660300002)(36756003)(47076005)(7416002)(2906002)(426003)(83380400001)(1076003)(40480700001)(2616005)(356005)(336012)(7636003)(82740400003)(8676002)(36860700001)(70586007)(70206006)(4326008)(110136005)(54906003)(316002)(8936002)(41300700001)(6666004)(107886003)(186003)(82310400005)(26005)(40460700003)(478600001)(7696005)(86362001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:45.4476 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8430 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jeffy Chen Add of_pci_setup_wake_irq() to parse the PCIe WAKE# interrupt from the device tree and set the wake irq. Add of_pci_teardown_wake_irq() to clear the wake irq. Call of_pci_setup_wake_irq() in pci_device_probe() to setup PCIe WAKE# interrupt during PCIe Endpoint enumeration. Enable or disable PCIe WAKE# interrupt in platform_pci_set_wakeup(). Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy --- Changes in v14: pci_platform_pm_ops structure is removed in latest kernel, so dropped pci-of driver. Instead, enable wake in platform_pci_set_wakeup(). Changes in v13: Fix compiler error reported by kbuild test robot Changes in v12: Enable the wake irq in noirq stage to avoid possible irq storm. Changes in v11: Only support 1-per-device PCIe WAKE# pin as suggested. Changes in v10: Use device_set_wakeup_capable() instead of device_set_wakeup_enable(), since dedicated wakeirq will be lost in device_set_wakeup_enable(false). Changes in v9: Fix check error in .cleanup(). Move dedicated wakeirq setup to setup() callback and use device_set_wakeup_enable() to enable/disable. Changes in v8: Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal. Changes in v7: Move PCIE_WAKE handling into pci core. Changes in v6: Fix device_init_wake error handling, and add some comments. Changes in v5: Rebase. Changes in v3: Fix error handling. Changes in v2: Use dev_pm_set_dedicated_wake_irq. drivers/pci/of.c | 49 ++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci-driver.c | 10 ++++++++ drivers/pci/pci.c | 7 ++++++ drivers/pci/pci.h | 8 +++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index ff897c40ed71..1c348e63f175 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -705,3 +706,51 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + struct pci_dev *ppdev; + struct device_node *dn; + int ret, irq; + + /* Get the pci_dev of our parent. Hopefully it's a port. */ + ppdev = pdev->bus->self; + /* Nope, it's a host bridge. */ + if (!ppdev) + return 0; + + dn = pci_device_to_OF_node(ppdev); + if (!dn) + return 0; + + irq = of_irq_get_byname(dn, "wakeup"); + if (irq == -EPROBE_DEFER) { + return irq; + } else if (irq < 0) { + /* Ignore other errors, since a missing wakeup is non-fatal. */ + dev_info(&pdev->dev, "cannot get wakeup interrupt: %d\n", irq); + return 0; + } + + device_init_wakeup(&pdev->dev, true); + + ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, irq); + if (ret < 0) { + dev_err(&pdev->dev, "failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + return ret; + } + + /* Start out disabled to avoid irq storm */ + dev_pm_disable_wake_irq(&pdev->dev); + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_setup_wake_irq); + +void of_pci_teardown_wake_irq(struct pci_dev *pdev) +{ + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); +} +EXPORT_SYMBOL_GPL(of_pci_teardown_wake_irq); diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index d934c27491c4..fca966137fac 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -456,10 +457,17 @@ static int pci_device_probe(struct device *dev) if (error < 0) return error; + error = of_pci_setup_wake_irq(pci_dev); + if (error < 0) { + pcibios_free_irq(pci_dev); + return error; + } + pci_dev_get(pci_dev); error = __pci_device_probe(drv, pci_dev); if (error) { pcibios_free_irq(pci_dev); + of_pci_teardown_wake_irq(pci_dev); pci_dev_put(pci_dev); } @@ -471,6 +479,8 @@ static void pci_device_remove(struct device *dev) struct pci_dev *pci_dev = to_pci_dev(dev); struct pci_driver *drv = pci_dev->driver; + of_pci_teardown_wake_irq(pci_dev); + if (drv->remove) { pm_runtime_get_sync(dev); drv->remove(pci_dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fba95486caaf..332a0b98b6c3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1052,6 +1053,12 @@ static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) if (pci_use_mid_pm()) return PCI_POWER_ERROR; + /* Enable or disable wakeirq if set via device tree. */ + if (enable) + dev_pm_enable_wake_irq(&dev->dev); + else + dev_pm_disable_wake_irq(&dev->dev); + return acpi_pci_wakeup(dev, enable); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 9ed3b5550043..83a2af148631 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -631,6 +631,8 @@ int of_pci_get_max_link_speed(struct device_node *node); u32 of_pci_get_slot_power_limit(struct device_node *node, u8 *slot_power_limit_value, u8 *slot_power_limit_scale); +int of_pci_setup_wake_irq(struct pci_dev *pdev); +void of_pci_teardown_wake_irq(struct pci_dev *pdev); void pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -669,6 +671,12 @@ of_pci_get_slot_power_limit(struct device_node *node, return 0; } +static inline int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + return 0; +} + +static inline void of_pci_teardown_wake_irq(struct pci_dev *pdev) { } static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } From patchwork Wed Feb 8 11:16:44 2023 Content-Type: text/plain; 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Signed-off-by: Manikanta Maddireddy --- Changes in v14: New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Orin. .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 8a9747855d6b..9c89be263141 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2147,6 +2147,17 @@ pcie@14100000 { phys = <&p2u_hsio_3>; phy-names = "p2u-0"; + + pci@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "wakeup"; + }; }; pcie@14160000 { From patchwork Wed Feb 8 11:16:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 13132991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BD32C636CC for ; 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Wed, 8 Feb 2023 03:17:37 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 5/5] soc/tegra: pmc: Add Tegra234 PCIe wake event Date: Wed, 8 Feb 2023 16:46:45 +0530 Message-ID: <20230208111645.3863534-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|SJ2PR12MB7942:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a1fb2df-3a00-4386-98ea-08db09c620d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FPklJNVKITaQVJc/91Oee5OnaVMnBY1AvrHmXGPF6xkfx/+J8Fa04t2qc8/AGmv/ktq1WnaVznLcWMDbvYqDXkSRwKnDTdwJkO+17Ye7w4jSAoRZO38kKvAVDeWGI8IiebO/FAw/xZWF1ttS64Y8ZBlLjRiZxLAlzV8Iphqsjj9Q5w13Fz6H+I4zqEkhtDyngEPvkTqLpQtQgOLT+46amz7lyvYwfn4fCdiGlO2dQJh5Z7jkx0Os6bnqITcnrqrCGWTie0wUgp+YxNTqiW3M+MrWAqZdvHW0Odby2rahGtmd59JEWkLyDV3cZKpNtkMnxGlRtGNBTyuTYLllEiMKpDaZX98KZZMDTcyRfgNFX5AzdaXjExeGDv8GY7U3vu1frVOJpk8RowelXckZfejvEkq4xHT9/UQXBLlWWQO+uNPAanc3EnVjcDeNTXEjBMggIbqOQAtpMIpgzjhnEutPlFQbPuxrR0F8KUW5JpUe9DvI5fiNpPAVYlcTSpfMDEJpketMO6bZCPc6QuQHZNZVqjiankneIkNxGOonXt8pGUHztvyzu95M06tcbU+3H8M073dRTvJRrtNAQVQmzIFUU6Z1oFOauL7up39A/VkwEFfYXdRkSvJcc+fwdLQWcNOoxUQV7/NA1K8+gkV1udDeZ3LnmGNIQdE7cXFFtmT16AARPTsdKx0ueKN7jVyZpyLIJ2T7NO4Kemk8N7+7BhL3GA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(4326008)(70206006)(70586007)(8676002)(36860700001)(336012)(40460700003)(316002)(7636003)(110136005)(54906003)(86362001)(426003)(5660300002)(7416002)(478600001)(356005)(1076003)(26005)(186003)(36756003)(107886003)(6666004)(2906002)(47076005)(4744005)(8936002)(82310400005)(41300700001)(82740400003)(2616005)(7696005)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:56.0004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a1fb2df-3a00-4386-98ea-08db09c620d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7942 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe wake event for the Tegra234 SoC. Signed-off-by: Manikanta Maddireddy --- Changes in v14: New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Orin. drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cf4cfbf9f7c5..139ee853c32b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4225,6 +4225,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_wake_event tegra234_wake_events[] = { + TEGRA_WAKE_GPIO("pcie", 1, 0, TEGRA234_MAIN_GPIO(L, 2)), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_IRQ("rtc", 73, 10), };