From patchwork Mon Jan 28 09:18:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 751B2922 for ; Mon, 28 Jan 2019 09:18:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61E8E29FA5 for ; Mon, 28 Jan 2019 09:18:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 560DD2A3FB; Mon, 28 Jan 2019 09:18:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D7F9C29FA5 for ; Mon, 28 Jan 2019 09:18:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GQIQOcX29zHrgAMqlKtMzUgHE6GZ/VBxy0JmaapgsPs=; b=QaDNWh+oHoUMW3 URcmD5F+t0q38Ck/LX75K8DTjM+LSozvcWuys9z+zDyn2Va4Ty0uygTTgAiExp0sM0r6tAFFFG+9n OAIjgr0UAajSJcI4l7EZ5wVCwGRHnDDXNqRu9oxOdN3yVvMEfhF41Aob/f3ReKriByDym60DEQWsG 0I9085u5DZvBVj3EIYu7TWOtmf1P7uROxCNdvTRvBkQ+j/AE8AMkQ2MD6g4YYoMkxQHKRuscRGQtv efuPprg7IXEwUI1Ss5G/73HyX3kdT0yFP4aiPEX6/4icA65PRPpHUQDCoyhwKNyOsNFqioPDE1KpU F0PrNga5XwT9sNg2156g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1go340-0005mW-3g; Mon, 28 Jan 2019 09:18:44 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1go33k-0005WC-53 for linux-arm-kernel@lists.infradead.org; Mon, 28 Jan 2019 09:18:29 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 28 Jan 2019 01:18:27 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 28 Jan 2019 01:18:27 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 28 Jan 2019 01:18:27 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Jan 2019 09:18:26 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 28 Jan 2019 09:18:27 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 28 Jan 2019 01:18:26 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH V2 1/6] dt-bindings: timer: add Tegra210 timer Date: Mon, 28 Jan 2019 17:18:10 +0800 Message-ID: <20190128091815.7040-2-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128091815.7040-1-josephl@nvidia.com> References: <20190128091815.7040-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548667107; bh=u95jrV41KeNMrvbLIFcQbZKpHTl6eJam1oRyS/T1Xns=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=fLrWpxxNI/705bfxJr75K/pNwthy1Ues+GION8hHfvdSpFGXe8t2dfNIs/QVwqG0e 4HIzm/19DjtUFuDUw2r+5OdkkWKgABUFxRPeAZSOpX2pXrb5DzDQhx5QF8Wo9scQKF eJF1Bk/SPu2PHbB0olmY8y9fTVaKqGvt0qSAUgXvc4iY2xGLbv+Te9jOY62To06hWj nRJOxQ2Cw8QO9RDiNMWW/qkSdqiK2DYs6Tr97vIk21lFSzjn09PeKdiaW5VkY3HX5l EXv+6xhNKKGa2T2sQv21wKVddWsgn3/X+EYhWJtTqZDrAyj1t+Xn49TWeHXvxzvScf 4Gugyi4ybLUqA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190128_011828_280188_57F9B5CC X-CRM114-Status: UNSURE ( 8.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , Daniel Lezcano , linux-kernel@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring --- v2: * list all the interrupts that are supported by tegra210 timers block * add RB tag from Rob. --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; From patchwork Mon Jan 28 09:18:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783447 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8751314E1 for ; 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Mon, 28 Jan 2019 01:18:29 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 28 Jan 2019 01:18:29 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Jan 2019 09:18:29 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Jan 2019 09:18:29 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 28 Jan 2019 09:18:29 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 28 Jan 2019 01:18:28 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH V2 2/6] clocksource: tegra: add Tegra210 timer driver Date: Mon, 28 Jan 2019 17:18:11 +0800 Message-ID: <20190128091815.7040-3-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128091815.7040-1-josephl@nvidia.com> References: <20190128091815.7040-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548667071; bh=LQkzD4L7fxDTilbQ5fRTv11VTT0f+RHS8zQglMq5hEw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=SgBm/qI86FVDAW5FlKLNG1Jat/tsp+/E603L/skbuROx5BRaPPMIYJ71aBOnjkw7H jHOa5mjwhbAi7nWk03ZOv7kIO8i++V+A/iO3DAAERB1gnQp5iExFjyUHKJQ1idzAzr mzmCQPSbSL98GkLd0zs0zqUYpzK7zZcKoYzcYIuHKkKOhMCDcaIxGMTEvQERXz7pAF zqOgh2tpVQCVJlAjQlKsC22pchZ5aCJ8tvNEhJu8cjNxjWCUk50oR2m41+5eR+P9XU GnPRKhjee2esQ5Vd5DK7QWh+GnHWH1F+oXcM+oILg/yJ5XVXNEc8o6qd1iNcM03aLz gTbECOWKHKEIA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190128_011831_043351_5353B905 X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Lezcano , linux-kernel@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Based on the work of Antti P Miettinen Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo --- v2: * add error clean-up code --- drivers/clocksource/Kconfig | 3 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-tegra210.c | 268 +++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 273 insertions(+) create mode 100644 drivers/clocksource/timer-tegra210.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6a81a1..e6e3e64b6320 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -135,6 +135,9 @@ config TEGRA_TIMER help Enables support for the Tegra driver. +config TEGRA210_TIMER + def_bool ARCH_TEGRA_210_SOC + config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cdd210ff89ea..95de59c8a47b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o +obj-$(CONFIG_TEGRA210_TIMER) += timer-tegra210.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra210.c b/drivers/clocksource/timer-tegra210.c new file mode 100644 index 000000000000..477b164e540b --- /dev/null +++ b/drivers/clocksource/timer-tegra210.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static u32 tegra210_timer_freq; +static void __iomem *tegra210_timer_reg_base; +static u32 usec_config; + +#define TIMER_PTV 0x0 +#define TIMER_PTV_EN BIT(31) +#define TIMER_PTV_PER BIT(30) +#define TIMER_PCR 0x4 +#define TIMER_PCR_INTR_CLR BIT(30) +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 + +#define TIMER10_OFFSET 0x90 +#define TIMER10_IRQ_IDX 10 + +#define TIMER_FOR_CPU(cpu) (TIMER10_OFFSET + (cpu) * 8) +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) + +struct tegra210_clockevent { + struct clock_event_device evt; + char name[20]; + void __iomem *reg_base; +}; +#define to_tegra_cevt(p) (container_of(p, struct tegra210_clockevent, evt)) + +static struct tegra210_clockevent __percpu *tegra210_evt; + +static int tegra210_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + writel(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + tevt->reg_base + TIMER_PTV); + + return 0; +} + +static inline void timer_shutdown(struct tegra210_clockevent *tevt) +{ + writel(0, tevt->reg_base + TIMER_PTV); +} + +static int tegra210_timer_shutdown(struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + timer_shutdown(tevt); + + return 0; +} + +static int tegra210_timer_set_periodic(struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + writel(TIMER_PTV_EN | TIMER_PTV_PER | ((tegra210_timer_freq / HZ) - 1), + tevt->reg_base + TIMER_PTV); + + return 0; +} + +static irqreturn_t tegra210_timer_isr(int irq, void *dev_id) +{ + struct tegra210_clockevent *tevt; + + tevt = dev_id; + writel(TIMER_PCR_INTR_CLR, tevt->reg_base + TIMER_PCR); + tevt->evt.event_handler(&tevt->evt); + + return IRQ_HANDLED; +} + +static int tegra210_timer_setup(unsigned int cpu) +{ + struct tegra210_clockevent *tevt = per_cpu_ptr(tegra210_evt, cpu); + + irq_force_affinity(tevt->evt.irq, cpumask_of(cpu)); + enable_irq(tevt->evt.irq); + + clockevents_config_and_register(&tevt->evt, tegra210_timer_freq, + 1, /* min */ + 0x1fffffff); /* 29 bits */ + + return 0; +} + +static int tegra210_timer_stop(unsigned int cpu) +{ + struct tegra210_clockevent *tevt = per_cpu_ptr(tegra210_evt, cpu); + + tevt->evt.set_state_shutdown(&tevt->evt); + disable_irq_nosync(tevt->evt.irq); + + return 0; +} + +static int tegra_timer_suspend(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + void __iomem *reg_base = tegra210_timer_reg_base + + TIMER_FOR_CPU(cpu); + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + } + + return 0; +} + +static void tegra_timer_resume(void) +{ + writel(usec_config, tegra210_timer_reg_base + TIMERUS_USEC_CFG); +} + +static struct syscore_ops tegra_timer_syscore_ops = { + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, +}; + +static int __init tegra210_timer_init(struct device_node *np) +{ + int cpu, ret = 0; + struct tegra210_clockevent *tevt; + struct clk *clk; + + tegra210_evt = alloc_percpu(struct tegra210_clockevent); + if (!tegra210_evt) { + ret = -ENOMEM; + goto out; + } + + tegra210_timer_reg_base = of_iomap(np, 0); + if (!tegra210_timer_reg_base) { + ret = -ENXIO; + goto out_free_mem; + } + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = -EINVAL; + goto out_iounmap; + } + + clk_prepare_enable(clk); + tegra210_timer_freq = clk_get_rate(clk); + + for_each_possible_cpu(cpu) { + tevt = per_cpu_ptr(tegra210_evt, cpu); + tevt->reg_base = tegra210_timer_reg_base + TIMER_FOR_CPU(cpu); + tevt->evt.irq = irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + if (!tevt->evt.irq) { + pr_err("%s: can't map IRQ for CPU%d\n", + __func__, cpu); + ret = -EINVAL; + goto out_clk; + } + + snprintf(tevt->name, ARRAY_SIZE(tevt->name), + "tegra210_timer%d", cpu); + tevt->evt.name = tevt->name; + tevt->evt.cpumask = cpumask_of(cpu); + tevt->evt.set_next_event = tegra210_timer_set_next_event; + tevt->evt.set_state_shutdown = tegra210_timer_shutdown; + tevt->evt.set_state_periodic = tegra210_timer_set_periodic; + tevt->evt.set_state_oneshot = tegra210_timer_shutdown; + tevt->evt.tick_resume = tegra210_timer_shutdown; + tevt->evt.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT; + tevt->evt.rating = 460; + + irq_set_status_flags(tevt->evt.irq, IRQ_NOAUTOEN); + ret = request_irq(tevt->evt.irq, tegra210_timer_isr, + IRQF_TIMER | IRQF_NOBALANCING, + tevt->name, tevt); + if (ret) { + pr_err("%s: cannot setup irq %d for CPU%d\n", + __func__, tevt->evt.irq, cpu); + ret = -EINVAL; + goto out_irq; + } + } + + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (tegra210_timer_freq) { + case 12000000: + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ + break; + case 13000000: + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ + break; + case 19200000: + usec_config = 0x045f; /* (95+1)/(4+1) */ + break; + case 26000000: + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ + break; + default: + ret = -EINVAL; + goto out_irq; + } + + writel(usec_config, tegra210_timer_reg_base + TIMERUS_USEC_CFG); + + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra210_timer_setup, + tegra210_timer_stop); + + register_syscore_ops(&tegra_timer_syscore_ops); + + return ret; + +out_irq: + for_each_possible_cpu(cpu) { + tevt = per_cpu_ptr(tegra210_evt, cpu); + if (tevt->evt.irq) { + free_irq(tevt->evt.irq, tevt); + irq_dispose_mapping(tevt->evt.irq); + } + } +out_clk: + clk_put(clk); +out_iounmap: + iounmap(tegra210_timer_reg_base); +out_free_mem: + free_percpu(tegra210_evt); +out: + return ret; +} + +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_timer_init); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index fd586d0301e7..e78281d07b70 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,6 +121,7 @@ enum cpuhp_state { CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, + CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, From patchwork Mon Jan 28 09:18:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D65B159A for ; Mon, 28 Jan 2019 09:19:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B3DE2A356 for ; Mon, 28 Jan 2019 09:19:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F1D3B2A35A; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Fix timer node to make it work with Tegra210 timer driver. Signed-off-by: Joseph Lo --- v2: * list all the IRQs per each timer channels 0 through 13 * remove compatible string of "nvidia,tegra30-timer" --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b5858b5ea052..2b387364afc3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -384,14 +384,22 @@ }; timer@60005000 { - compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra210-timer"; reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , + interrupts = , + , , , , , - ; + , + , + , + , + , + , + , + ; clocks = <&tegra_car TEGRA210_CLK_TIMER>; clock-names = "timer"; }; From patchwork Mon Jan 28 09:18:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57A90746 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add idle states properties for generic ARM CPU idle driver. This includes a C7 state which is the power down state of CPU cores. Signed-off-by: Joseph Lo --- v2: * add entry-latency-us and exit-latency-us properties Note: This dt patch depends on the DT changes in below series. http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2b387364afc3..75534692604c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1318,24 +1318,43 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&C7>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&C7>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&C7>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&C7>; + }; + + idle-states { + entry-method = "psci"; + + C7: c7 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + entry-latency-us = <250>; + exit-latency-us = <100>; + min-residency-us = <1000>; + wakeup-latency-us = <130>; + idle-state-name = "c7-cpu-powergated"; + status = "disabled"; + }; }; }; From patchwork Mon Jan 28 09:18:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77245922 for ; Mon, 28 Jan 2019 09:19:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 626592A356 for ; Mon, 28 Jan 2019 09:19:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 530772A358; Mon, 28 Jan 2019 09:19:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E40F22A356 for ; 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Mon, 28 Jan 2019 01:18:34 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH V2 5/6] arm64: dts: tegra210-p2180: Enable CPU idle support Date: Mon, 28 Jan 2019 17:18:14 +0800 Message-ID: <20190128091815.7040-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128091815.7040-1-josephl@nvidia.com> References: <20190128091815.7040-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548667076; bh=Hyz+PmmOHZrkiUg6BnM6fDA6KQa95sfUrvDVT4Q3Lps=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=fH5savr79dGNGV6/hglkJDAaGyaPboT5A/oWZCGwqRhDjrvpWcyT1e5tBgSRvhYfG 4vrlSDnJNouM1roDzGi2Ym/H/VsI21vCySSS8GjPyc50IvC6ijzKSAlYh8LjJ2RXi+ 1jx1Mt6uLZwebwiYqK52GQ4PGCAWDszr96/xlDEO4AnXdTeNmlNhOS5J7g629leB4e Xhp6lxwSyU6usdymRxAQTS9+pw2ZgtxtfQVXqYj2mEbw0S5T1L9zowHWzYfdtIW9ZD HcTvSNJ/goP/VQjFo4hkqaz/xrQmHXvmBCKi8rgInvYOrW2zybbBl85AISmmCnD/tD zF37IgIrv+E/w== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190128_011835_662010_AEDBDE3D X-CRM114-Status: UNSURE ( 7.13 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable CPU idle support for Jetson TX1 platform. Signed-off-by: Joseph Lo --- v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 053458a5db55..d1a492c63e96 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -305,6 +305,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + status = "okay"; + }; + }; }; psci { From patchwork Mon Jan 28 09:18:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10783451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B077814E1 for ; Mon, 28 Jan 2019 09:20:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9DBA72A498 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable CPU idle support for Smaug platform. Signed-off-by: Joseph Lo --- v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5a67890cfb7a..da0eb4530acf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1751,6 +1751,13 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + arm,psci-suspend-param = <0x00010007>; + status = "okay"; + }; + }; }; gpio-keys {