From patchwork Fri Feb 17 16:40:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145036 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72291C05027 for ; Fri, 17 Feb 2023 16:40:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kLhaA1HCYcuGgzzlI3S2DcMf7f4xvouwOpZxtXCPw2g=; b=NcyrADJXVNhVm1 rUGtN7ckMJHzI3fNa1CU9C5UquVlgOuwi70imw3DEA91mo7K7x3rTbmSUmInIXPg2uQJprt93cqrf W25TSLgkIeLYb415EeSD++9pC/aA5xM+B6IE11rXXwZux/Lrtv1LRoOg8ojw0gf0drw7FMuK78Ugm OmbTdARn4d0ArjxfAj6EYdDbZlf0XRKZg+qDlYD88QHpE0YdVw6i/Bun25SOjQDe/iDINViSs5XsN y6wsjaERlGo8XM32YIhNuMORi37MZ0g27OUSJ8bD1sa4PEWM1HqK9UPd5iCw/latx54vH37oagOWL l+t0J9tIfIr4+1GCOh/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pT3mz-00F7FT-Sn; Fri, 17 Feb 2023 16:40:49 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pT3mv-00F7Dv-74 for linux-riscv@lists.infradead.org; Fri, 17 Feb 2023 16:40:47 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B0D9261EBC; Fri, 17 Feb 2023 16:40:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95E58C433D2; Fri, 17 Feb 2023 16:40:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1676652044; bh=uqM+5rtlFlEeXSd/1anUI6DmVd10V3MqxkeZ8jvGqac=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YyjGX9s0fUOU95il4oo4Yxn3apt+m5I+pZ0R+kVThA/OZeL2ZvHMydDbh0GDLIYqM 2vC68gXhJCSmmlz5f/04yN5wF5uzLl4Vuu7j+41Q0PS/u7Cw/qbaXJekWuJnxHnL3t CE8xyGoZ1db0PaMJTrmJTkeDEEpm7QUvqOlsQkigofx31jahniDpmjiK1lIEt/stEm 6iql/fle5ABVBSzjNS89m/u8bCQ2khTRM3w5Xox9KSZ4mImQKVZAM2grkB/Y4v6Ymb MI3VnUUorUt/R5q1pico2pJv5lliR00loKesLKziA5R1bttuy+U96ssOfvRcKMNr0w 1ueRrBCmT4fUA== From: Conor Dooley To: Xu Yilun , conor@kernel.org Cc: Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Moritz Fischer , Wu Hao , Tom Rix , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v1 1/6] soc: microchip: mpfs: add a prefix to rx_callback() Date: Fri, 17 Feb 2023 16:40:18 +0000 Message-Id: <20230217164023.14255-2-conor@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230217164023.14255-1-conor@kernel.org> References: <20230217164023.14255-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1311; i=conor.dooley@microchip.com; h=from:subject; bh=RNzEefOhKfQMOBdza8p2YEG5lWs9FX5mqYbHLNGi5xk=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMnv1759mjS3vey3XWWh/u+Eh2vL/2snBJVfX+B9R4LbJWnG fuYTHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhI9xtGhjkCcm2uAefOlN69cmkz85 KXTV/DrvcKr3U9qZHx//aM/S0M//T+ON/84f/YXUf/9lSBmU8rHpj39xZd8dM9sW2zWUKWPxMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230217_084045_328858_332097AD X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add a prefix to the function name to match the rest of the file. Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index 973a748d324c..11616e3c9ac8 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -73,7 +73,7 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct } EXPORT_SYMBOL(mpfs_blocking_transaction); -static void rx_callback(struct mbox_client *client, void *msg) +static void mpfs_sys_controller_rx_callback(struct mbox_client *client, void *msg) { struct mpfs_sys_controller *sys_controller = container_of(client, struct mpfs_sys_controller, client); @@ -119,7 +119,7 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) return -ENOMEM; sys_controller->client.dev = dev; - sys_controller->client.rx_callback = rx_callback; + sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback; sys_controller->client.tx_block = 1U; sys_controller->client.tx_tout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS); From patchwork Fri Feb 17 16:40:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145039 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41F1BC64ED6 for ; Fri, 17 Feb 2023 16:41:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 17 Feb 2023 16:40:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 906D2C433A0; Fri, 17 Feb 2023 16:40:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1676652047; bh=8Pkfc5Vtr1bS1mfUGRyytTI2Goy5iCLpHwo24Vj3Z4Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZopDMN/t/u+V8+JAFkyK6Easm2YKxMfzovzbDhLKTTW2uoA5pibaW9nNphyrlgPz dJ0fJ20e9NpMGoo7A4gTbsCDA9XlNt//MDfR/QQfs6TqzccOPsfWC2JWhmEVadY5lY /8eW3K6sYTTm32hR2LP0uqhZybx1CHfx5zvrwehpKfHTaP+q5vPqwQsmsVcGGLm67g tT5D1SgNpCHUnyRhYhh6dh6dChwNcNqFZ9DvBV6EwVxLwb6dQFiWVlW7ghGkIJmFaz Ipj1QHKjMN5wzFrTSDrcI2hhrUOt7IQGf23kVgVHcrOZSlrS8UOzauNiq+iEkmVlez 4qJe7N94WqvOA== From: Conor Dooley To: Xu Yilun , conor@kernel.org Cc: Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Moritz Fischer , Wu Hao , Tom Rix , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v1 2/6] dt-bindings: soc: microchip: add a property for system controller flash Date: Fri, 17 Feb 2023 16:40:19 +0000 Message-Id: <20230217164023.14255-3-conor@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230217164023.14255-1-conor@kernel.org> References: <20230217164023.14255-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1632; i=conor.dooley@microchip.com; h=from:subject; bh=fTElDZa5UroElstrQ0dzqW+hmPb678nX3XRMkYJvFsI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMnv17498Deyouk5h1zP2z+h8+6vbr/qvOLkvAp5xQ4Lz/CX 0mcXd5SyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAix88yMpz/c+1uxwu1xe8XzvD6o7 9m46nA+kczWkVF1IVXJM3dNi+e4Z/NJD0Wl4fxFZF8+c4Ta/pbGO9NWxbErHfykcLz/RFq6lwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230217_084052_591792_46F985AC X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The system controller "shares" a SPI flash device with a QSPI controller in the MSS. This flash is used to store FPGA bitstreams & other metadata. IAP and Auto Upgrade both write images to this flash that the System Controller will use to re-program the FPGA. Add a phandle property signifying which flash device is connected to the system controller. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../soc/microchip/microchip,mpfs-sys-controller.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml index 04ffee3a7c59..97a7cb74cbf9 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -26,6 +26,16 @@ properties: compatible: const: microchip,mpfs-sys-controller + microchip,bitstream-flash: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + The SPI flash connected to the system controller's QSPI controller. + The system controller may retrieve FPGA bitstreams from this flash to + perform In-Application Programming (IAP) or during device initialisation + for Auto Update. The MSS and system controller have separate QSPI + controllers and this flash is connected to both. Software running in the + MSS can write bitstreams to the flash. + required: - compatible - mboxes From patchwork Fri Feb 17 16:40:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145038 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F1F7C636D6 for ; Fri, 17 Feb 2023 16:41:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4iqeGdDYAVIMks93L4m+5XMpffyXEyvoIdwrx5n/Fc4=; b=GBFjB5pBpZ0WFd pPByiTnLOqV71+OOO0AECQxEkEO/kcq8lcanyXHlPODlHpN9DUdmdQWkac9Mx+3o7ipQ/8ugkm3QF 7ySyvcxzfF5/2EC/A5IvskYcUEzFIJFAQVai9BWxWntsSO0dhmC5zFe/afcQWYOTTcBO/fsSy20zS k6jZFWJ24jcAHg/8hx0RbLTjC/13oLx34Kl4+0mOEQVOXO8VcOWI+68j8Y4FeG1wrYUCXKDCI3mv3 8uW4uSrqbTy44nXixnRmTxVzVWa2q+lonAokHkK3nyvUt8tQ30hIej82g6E+AKEMYY0SFBWuVBz0A IcX0oAiTTshlzm8aHuCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pT3n8-00F7JU-0H; Fri, 17 Feb 2023 16:40:58 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pT3n0-00F7Fb-Nv for linux-riscv@lists.infradead.org; Fri, 17 Feb 2023 16:40:52 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4D97E61F0D; Fri, 17 Feb 2023 16:40:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B645C4339B; Fri, 17 Feb 2023 16:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1676652050; bh=s71zhhs0wecI4Nj/TiJBEe21bHckcl5t2kj31eKsk2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o5dlIZsDSWDbpNjmUXNT8rcYz8bORxiOy20ztT1YlygZebRA6cwJZ0zlH53KP9xL2 LPMUCAIVA/svO57gelYC4fUpHVsQooUFMOTxgXWa79tk2fWJJ97r+tD8t9Dm5nzgNw 8GXP0ExwYEjcPc/cKFTCDmAz19idenfJc09u8vul9BfbIxXE8EqprlA3oUEhniMqyf q194fEcuGqMy2Y/dxmXbDY/9Vjen8KVI7ppHnwqkrHFPqcK7l7oGEp2czGyogtTGMA r+CWKMpmMuFey66/FSkOIlydAp4eBUpoP/StaIuMSwuxec6Ncx4DmMF/70aJ8Tu1lH VYwTs7M+uyosQ== From: Conor Dooley To: Xu Yilun , conor@kernel.org Cc: Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Moritz Fischer , Wu Hao , Tom Rix , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v1 3/6] soc: microchip: mpfs: enable access to the system controller's flash Date: Fri, 17 Feb 2023 16:40:20 +0000 Message-Id: <20230217164023.14255-4-conor@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230217164023.14255-1-conor@kernel.org> References: <20230217164023.14255-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3442; i=conor.dooley@microchip.com; h=from:subject; bh=OKHGlsPAKNTTp6NanBTdt/Ki4XURpI/Var46Ky0xqoU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMnv1769ftcuntsoS4VZu9G6U0llpoLaY6XHgiV3Gvv1dRvu bQvrKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwETmHWX4K/Yxb6tE2OVJ3mZHFsyUTk n9IDXp5KwpC8Tn7WlY9NLDtoCRYbHNZw6xP3NOLFr9Wzxu977bCZdMTtk0xj2zCQiwdNzNyQYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230217_084050_909890_8321E9CB X-CRM114-Status: GOOD ( 20.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming). Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it. Signed-off-by: Conor Dooley --- drivers/soc/microchip/Kconfig | 1 + drivers/soc/microchip/mpfs-sys-controller.c | 20 ++++++++++++++++++++ include/soc/microchip/mpfs.h | 2 ++ 3 files changed, 23 insertions(+) diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index eb656b33156b..9b0fdd95276e 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -1,6 +1,7 @@ config POLARFIRE_SOC_SYS_CTRL tristate "POLARFIRE_SOC_SYS_CTRL" depends on POLARFIRE_SOC_MAILBOX + depends on MTD help This driver adds support for the PolarFire SoC (MPFS) system controller. diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index 11616e3c9ac8..bcbb4bab09e5 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -30,6 +32,7 @@ struct mpfs_sys_controller { struct mbox_client client; struct mbox_chan *chan; struct completion c; + struct mtd_info *flash; struct kref consumers; }; @@ -97,6 +100,12 @@ static void mpfs_sys_controller_put(void *data) kref_put(&sys_controller->consumers, mpfs_sys_controller_delete); } +struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client) +{ + return mpfs_client->flash; +} +EXPORT_SYMBOL(mpfs_sys_controller_get_flash); + static struct platform_device subdevs[] = { { .name = "mpfs-rng", @@ -112,12 +121,23 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mpfs_sys_controller *sys_controller; + struct device_node *np; int i, ret; sys_controller = kzalloc(sizeof(*sys_controller), GFP_KERNEL); if (!sys_controller) return -ENOMEM; + np = of_parse_phandle(dev->of_node, "microchip,bitstream-flash", 0); + if (!np) + goto no_flash; + + sys_controller->flash = of_get_mtd_device_by_node(np); + of_node_put(np); + if (IS_ERR(sys_controller->flash)) + return dev_err_probe(dev, PTR_ERR(sys_controller->flash), "Failed to get flash\n"); + +no_flash: sys_controller->client.dev = dev; sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback; sys_controller->client.tx_block = 1U; diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index f916dcde457f..09722f83b0ca 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -38,6 +38,8 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mp struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); +struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_client); + #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) From patchwork Fri Feb 17 16:40:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145040 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AB79C6379F for ; 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In-Application Programming (IAP) is not ideal for use in Linux, as it will immediately take down the system when requested. Auto Update is preferred, as it will only take affect at device power up*, allowing the OS (and potential applications in AMP) to be shut down gracefully. * Auto Update occurs at device initialisation, which can also be triggered by device reset - possible with the v2023.02 version of the Hart Software Services (HSS) and reference design. Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index bcbb4bab09e5..223eec66edf9 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -114,7 +114,11 @@ static struct platform_device subdevs[] = { { .name = "mpfs-generic-service", .id = -1, - } + }, + { + .name = "mpfs-auto-update", + .id = -1, + }, }; static int mpfs_sys_controller_probe(struct platform_device *pdev) @@ -156,7 +160,6 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sys_controller); - dev_info(&pdev->dev, "Registered MPFS system controller\n"); for (i = 0; i < ARRAY_SIZE(subdevs); i++) { subdevs[i].dev.parent = dev; @@ -164,6 +167,8 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name); } + dev_info(&pdev->dev, "Registered MPFS system controller\n"); + return 0; } From patchwork Fri Feb 17 16:40:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145041 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93B03C636D6 for ; Fri, 17 Feb 2023 16:41:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 17 Feb 2023 16:40:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8475BC43444; Fri, 17 Feb 2023 16:40:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1676652056; bh=Ada5YJvntQNNf8mjai4BiBi5laL09boYhqgifAggSQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oH++hjwqroHKIFxmF/HnsnxHUNBefUvOtOzGRWfyjk3g5O5C4HlXvlQqMjfF4mTtj MNIO3uV96d+6WmPTPJAuEjACZny2Q0P71ip5tuOusdjaO15DsfvSVO30mKv/iGyptl x4oK5StKhzqmaDlFnhtJ/6mLdFfotB5NAKiLI5qhj4oMEAlsDN8/Ma7ckgfLSI9LkR O3C1EzNtg6f6kZXUqnkilmrARmc312ZaryiS4cIQhbaRYTvwUV2IQ08keAmdjnFFBy oTJDX4Ci40ku7kp2I39uUsNuRhzNWOnyjqy4x1HScqJcHhdBZG/JQ1OPjD1H0Xgid0 XmZUqfnv+cG8Q== From: Conor Dooley To: Xu Yilun , conor@kernel.org Cc: Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Moritz Fischer , Wu Hao , Tom Rix , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v1 5/6] fpga: add PolarFire SoC Auto Update support Date: Fri, 17 Feb 2023 16:40:22 +0000 Message-Id: <20230217164023.14255-6-conor@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230217164023.14255-1-conor@kernel.org> References: <20230217164023.14255-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=18671; i=conor.dooley@microchip.com; h=from:subject; bh=5c9FyeDfJ+4rxNjXaNpKTn1QANdTH3UMNxq+UGzUyrc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMnv175l+PRYZsXn5Ulb3itvSAu2UVC6qRv1bWL2lVv1RuvW 39hk0VHKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEN4eIUgImwdzL8j1316fl8j+vp3VvUDy5y8u ud8Xh6Q6T2ki5LkYC6tJWdTowMW9dyu/abSShd2FJiZPnvnu31qbssdmaaBRafY7z1b8sDdgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230217_084057_051165_936E12AC X-CRM114-Status: GOOD ( 34.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add support for Auto Update reprogramming of the FPGA fabric on PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/fpga/Kconfig | 9 + drivers/fpga/Makefile | 1 + drivers/fpga/microchip-auto-update.c | 495 +++++++++++++++++++++++++++ 3 files changed, 505 insertions(+) create mode 100644 drivers/fpga/microchip-auto-update.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 6ce143dafd04..0cdd6978a440 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -257,6 +257,15 @@ config FPGA_M10_BMC_SEC_UPDATE (BMC) and provides support for secure updates for the BMC image, the FPGA image, the Root Entry Hashes, etc. +config FPGA_MGR_MICROCHIP_AUTO_UPDATE + tristate "Microchip PolarFire SoC AUTO UPDATE" + depends on POLARFIRE_SOC_SYS_CTRL + help + FPGA manager driver support for reprogramming PolarFire SoC from + within Linux, using the Auto Upgrade feature of the system controller. + + If built as a module, it will be called microchip-auto-update. + config FPGA_MGR_MICROCHIP_SPI tristate "Microchip Polarfire SPI FPGA manager" depends on SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 72e554b4d2f7..a67903edf976 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o +obj-$(CONFIG_FPGA_MGR_MICROCHIP_AUTO_UPDATE) += microchip-auto-update.o obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o diff --git a/drivers/fpga/microchip-auto-update.c b/drivers/fpga/microchip-auto-update.c new file mode 100644 index 000000000000..d90085f86b8b --- /dev/null +++ b/drivers/fpga/microchip-auto-update.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip Polarfire SoC "Auto Update" FPGA reprogramming. + * + * Documentation of this functionality is available in the "PolarFire® FPGA and + * PolarFire SoC FPGA Programming" User Guide. + * + * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AUTO_UPDATE_DEFAULT_MBOX_OFFSET 0u +#define AUTO_UPDATE_DEFAULT_RESP_OFFSET 0u + +#define AUTO_UPDATE_FEATURE_CMD_OPCODE 0x05u +#define AUTO_UPDATE_FEATURE_CMD_DATA_SIZE 0u +#define AUTO_UPDATE_FEATURE_RESP_SIZE 33u +#define AUTO_UPDATE_FEATURE_CMD_DATA NULL +#define AUTO_UPDATE_FEATURE_ENABLED BIT(5) + +#define AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE 0x22u +#define AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE 0u +#define AUTO_UPDATE_AUTHENTICATE_RESP_SIZE 1u +#define AUTO_UPDATE_AUTHENTICATE_CMD_DATA NULL + +#define AUTO_UPDATE_PROGRAM_CMD_OPCODE 0x46u +#define AUTO_UPDATE_PROGRAM_CMD_DATA_SIZE 0u +#define AUTO_UPDATE_PROGRAM_RESP_SIZE 1u +#define AUTO_UPDATE_PROGRAM_CMD_DATA NULL + +/* + * SPI Flash layout example: + * |------------------------------| 0x0000000 + * | 1 KiB | + * | SPI "directories" | + * |------------------------------| 0x0000400 + * | 1 MiB | + * | Reserved area | + * | Used for bitstream info | + * |------------------------------| 0x0100400 + * | 20 MiB | + * | Golden Image | + * |------------------------------| 0x1500400 + * | 20 MiB | + * | Auto Upgrade Image | + * |------------------------------| 0x2900400 + * | 20 MiB | + * | Reserved for multi-image IAP | + * | Unused for Auto Upgrade | + * |------------------------------| 0x3D00400 + * | ? B | + * | Unused | + * |------------------------------| 0x? + */ +#define AUTO_UPDATE_DIRECTORY_BASE 0u +#define AUTO_UPDATE_DIRECTORY_WIDTH 4u +#define AUTO_UPDATE_GOLDEN_INDEX 0u +#define AUTO_UPDATE_UPGRADE_INDEX 1u +#define AUTO_UPDATE_BLANK_INDEX 2u +#define AUTO_UPDATE_GOLDEN_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_GOLDEN_INDEX) +#define AUTO_UPDATE_UPGRADE_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_UPGRADE_INDEX) +#define AUTO_UPDATE_BLANK_DIRECTORY (AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_BLANK_INDEX) +#define AUTO_UPDATE_DIRECTORY_SIZE SZ_1K +#define AUTO_UPDATE_RESERVED_SIZE SZ_1M +#define AUTO_UPDATE_BITSTREAM_BASE (AUTO_UPDATE_DIRECTORY_SIZE + AUTO_UPDATE_RESERVED_SIZE) + +struct mpfs_auto_update_config { + u8 feature_response_size; +}; + +struct mpfs_auto_update_priv { + struct mpfs_sys_controller *sys_controller; + struct device *dev; + struct fpga_region *region; + struct mpfs_auto_update_config *config; + struct mtd_info *flash; + struct dentry *debugfs_dir; +}; + +static struct device *mpfs_auto_update_debug_dev; + +static enum fpga_mgr_states mpfs_auto_update_state(struct fpga_manager *mgr) +{ + struct mpfs_auto_update_priv *priv = mgr->priv; + struct mpfs_mss_response *response; + struct mpfs_mss_msg *message; + u32 *response_msg; + int ret; + enum fpga_mgr_states rc = FPGA_MGR_STATE_WRITE_INIT_ERR; + + response_msg = devm_kzalloc(priv->dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg), + GFP_KERNEL); + if (!response_msg) + return FPGA_MGR_STATE_WRITE_INIT_ERR; + + response = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_response), GFP_KERNEL); + if (!response) { + rc = FPGA_MGR_STATE_WRITE_INIT_ERR; + goto free_response_msg; + } + + message = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL); + if (!message) { + rc = FPGA_MGR_STATE_WRITE_INIT_ERR; + goto free_response; + } + + /* + * To verify that Auto Update is possible, the "Query Security Service + * Request" is performed. Bit 5 of byte 1 is "UL_Auto Update" & if it is + * set, Auto Update is not possible. + * This service has no command data & does not overload mbox_offset. + * The size of the response varies between PolarFire & PolarFire SoC. + */ + response->resp_msg = response_msg; + response->resp_size = AUTO_UPDATE_FEATURE_RESP_SIZE; + message->cmd_opcode = AUTO_UPDATE_FEATURE_CMD_OPCODE; + message->cmd_data_size = AUTO_UPDATE_FEATURE_CMD_DATA_SIZE; + message->response = response; + message->cmd_data = AUTO_UPDATE_FEATURE_CMD_DATA; + message->mbox_offset = AUTO_UPDATE_DEFAULT_MBOX_OFFSET; + message->resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET; + + ret = mpfs_blocking_transaction(priv->sys_controller, message); + if (ret | response->resp_status) { + rc = FPGA_MGR_STATE_UNKNOWN; + goto free_message; + } + + if (!(response_msg[1] & AUTO_UPDATE_FEATURE_ENABLED)) + rc = FPGA_MGR_STATE_OPERATING; + +free_message: + devm_kfree(priv->dev, message); +free_response: + devm_kfree(priv->dev, response); +free_response_msg: + devm_kfree(priv->dev, response_msg); + + return rc; +} + +static int mpfs_auto_update_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, + const char *buf, size_t count) +{ + /* + * Verifying the Golden Image is idealistic. It will be evaluated + * against the currently programmed image and thus may fail - due to + * either rollback protection (if its an older version than that in use) + * or if the version is the same as that of the in-use image. + * Extracting the information as to why a failure occurred is not + * currently possible due to limitations of the system controller + * driver. If those are fixed, verification of the Golden Image should + * be added here. + */ + return 0; +} + +static int mpfs_auto_update_write(struct fpga_manager *mgr, const char *buf, size_t count) +{ + /* + * No parsing etc of the bitstream is required. The system controller + * will do all of that itself - including verifying that the bitstream + * is valid. + */ + struct mpfs_auto_update_priv *priv = mgr->priv; + struct erase_info erase; + char *buffer; + loff_t directory_address = AUTO_UPDATE_UPGRADE_DIRECTORY; + size_t bytes_written = 0, bytes_read = 0; + size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE; + size_t size_per_bitstream = 0; + u32 image_address; + int ret; + + priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller); + if (!priv->flash) + return -EIO; + + erase_size = round_up(erase_size, (u64)priv->flash->erasesize); + + /* + * We need to calculate if we have enough space in the flash for the + * new image. + * First, chop off the first 1 KiB as it's reserved for the directory. + * The 1 MiB reserved for design info needs to be ignored also. + * All that remains is carved into 3 & rounded down to the erasesize. + * If this is smaller than the image size, we abort. + * There's also no need to consume more than 20 MiB per image. + */ + size_per_bitstream = priv->flash->size - SZ_1K - SZ_1M; + size_per_bitstream = round_down(size_per_bitstream / 3, erase_size); + if (size_per_bitstream > 20 * SZ_1M) + size_per_bitstream = 20 * SZ_1M; + + if (size_per_bitstream < count) { + dev_err(priv->dev, + "flash device has insufficient capacity to store this bitstream\n"); + return -EINVAL; + } + + image_address = AUTO_UPDATE_BITSTREAM_BASE + AUTO_UPDATE_UPGRADE_INDEX * size_per_bitstream; + + buffer = devm_kzalloc(priv->dev, erase_size, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + erase.addr = AUTO_UPDATE_DIRECTORY_BASE; + erase.len = erase_size; + + /* + * We need to write the "SPI DIRECTORY" to the first 1 KiB, telling + * the system controller where to find the actual bitstream. Since + * this is spi-nor, we have to read the first eraseblock, erase that + * portion of the flash, modify the data and then write it back. + */ + ret = mtd_read(priv->flash, AUTO_UPDATE_DIRECTORY_BASE, erase_size, &bytes_read, + (u_char *)buffer); + if (ret) + goto out; + + if (bytes_read != erase_size) { + ret = -EIO; + goto out; + } + + ret = mtd_erase(priv->flash, &erase); + if (ret) + goto out; + + /* + * Populate the image address and then zero out the next directory so + * that the system controller doesn't complain if in "Single Image" + * mode. + */ + memcpy(buffer + AUTO_UPDATE_UPGRADE_DIRECTORY, &image_address, AUTO_UPDATE_DIRECTORY_WIDTH); + memset(buffer + AUTO_UPDATE_BLANK_DIRECTORY, 0x0, AUTO_UPDATE_DIRECTORY_WIDTH); + + dev_info(priv->dev, "Writing the image address (%x) to the flash directory (%llx)\n", + image_address, directory_address); + + ret = mtd_write(priv->flash, 0x0, erase_size, &bytes_written, (u_char *)buffer); + if (ret) + goto out; + + if (bytes_written != erase_size) { + ret = -EIO; + goto out; + } + + /* + * Now the .spi image itself can be written to the flash. Preservation + * of contents here is not important here, unlike the spi "directory" + * which must be RMWed. + */ + erase.len = round_up(count, (size_t)priv->flash->erasesize); + erase.addr = image_address; + + dev_info(priv->dev, "Erasing the flash at address (%x)\n", image_address); + ret = mtd_erase(priv->flash, &erase); + if (ret) + goto out; + + dev_info(priv->dev, "Writing the image to the flash at address (%x)\n", image_address); + ret = mtd_write(priv->flash, (loff_t)image_address, count, &bytes_written, buf); + if (ret) + goto out; + + if (bytes_written != count) + ret = -EIO; + +out: + devm_kfree(priv->dev, buffer); + return ret; +} + +static int mpfs_auto_update_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) +{ + struct mpfs_auto_update_priv *priv = mgr->priv; + struct mpfs_mss_response *response; + struct mpfs_mss_msg *message; + u32 *response_msg; + int ret; + + response_msg = devm_kzalloc(priv->dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg), + GFP_KERNEL); + if (!response_msg) + return -ENOMEM; + + response = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_response), GFP_KERNEL); + if (!response) { + ret = -ENOMEM; + goto free_response_msg; + } + + message = devm_kzalloc(priv->dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL); + if (!message) { + ret = -ENOMEM; + goto free_response; + } + + /* + * The system controller can verify that an image in the flash is valid. + * Rather than duplicate the check in this driver, call the relevant + * service from the system controller instead. + * This service has no command data and no response data. It overloads + * mbox_offset with the image index in the flash's SPI directory where + * the bitstream is located. + */ + response->resp_msg = response_msg; + response->resp_size = AUTO_UPDATE_AUTHENTICATE_RESP_SIZE; + message->cmd_opcode = AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE; + message->cmd_data_size = AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE; + message->response = response; + message->cmd_data = AUTO_UPDATE_AUTHENTICATE_CMD_DATA; + message->mbox_offset = AUTO_UPDATE_UPGRADE_INDEX; + message->resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET; + + dev_info(priv->dev, "Running verification of Upgrade Image\n"); + ret = mpfs_blocking_transaction(priv->sys_controller, message); + if (ret | response->resp_status) { + dev_warn(priv->dev, "Verification of Upgrade Image failed!\n"); + ret = ret ? ret : -EBADMSG; + } + + dev_info(priv->dev, "Verification of Upgrade Image passed!\n"); +// /* +// * If the validation has passed, initiate Auto Update. +// * This service has no command data and no response data. It overloads +// * mbox_offset with the image index in the flash's SPI directory where +// * the bitstream is located. +// * Once we attempt Auto Update either: +// * - it passes and the board reboots +// * - it fails and the board reboots to recover +// * - the system controller aborts and we exit "gracefully". +// * "gracefully" since there is no interrupt produced & it just times +// * out. +// */ +// response->resp_msg = response_msg; +// response->resp_size = AUTO_UPDATE_PROGRAM_RESP_SIZE; +// message->cmd_opcode = AUTO_UPDATE_PROGRAM_CMD_OPCODE; +// message->cmd_data_size = AUTO_UPDATE_PROGRAM_CMD_DATA_SIZE; +// message->response = response; +// message->cmd_data = AUTO_UPDATE_PROGRAM_CMD_DATA; +// message->mbox_offset = 0; //field is ignored +// message->resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET; +// +// dev_info(priv->dev, "Running Auto Update command\n"); +// ret = mpfs_blocking_transaction(priv->sys_controller, message); +// if (ret && ret != -ETIMEDOUT) +// goto out; +// +// /* *remove this for auto update* +// * This return 0 is dead code. Either the Auto Update will fail, or it will pass +// * & the FPGA will be rebooted in which case mpfs_blocking_transaction() +// * will never return and Linux will die. +// */ +// return 0; + + devm_kfree(priv->dev, message); +free_response: + devm_kfree(priv->dev, response); +free_response_msg: + devm_kfree(priv->dev, response_msg); + + return ret; +} + +static const struct fpga_manager_ops mpfs_auto_update_ops = { + .state = mpfs_auto_update_state, + .write_init = mpfs_auto_update_write_init, + .write = mpfs_auto_update_write, + .write_complete = mpfs_auto_update_write_complete, +}; + +static int mpfs_auto_update_run(struct device *dev) +{ + struct fpga_manager *mgr; + struct fpga_image_info *info; + int ret; + + mgr = fpga_mgr_get(dev); + info = fpga_image_info_alloc(dev); + + info->firmware_name = devm_kstrdup(dev, "mpfs_bitstream.spi", GFP_KERNEL); + + ret = fpga_mgr_lock(mgr); + if (ret) + goto free_info; + + ret = fpga_mgr_load(mgr, info); + if (ret) { + dev_err(dev, "Failed to write the bitstream\n"); + goto unlock_mgr; + } + +unlock_mgr: + fpga_mgr_unlock(mgr); +free_info: + fpga_image_info_free(info); + fpga_mgr_put(mgr); + + return ret; +} + +static ssize_t mpfs_auto_update_exec(struct file *file, const char __user *data, size_t count, + loff_t *ppos) +{ + int ret; + + ret = mpfs_auto_update_run(mpfs_auto_update_debug_dev); + if (ret) + dev_err_probe(mpfs_auto_update_debug_dev, ret, "Auto Update failed"); + + return count; +} + +static const struct file_operations mpfs_auto_update_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .write = mpfs_auto_update_exec +}; + +static int mpfs_auto_update_debugfs_setup(struct mpfs_auto_update_priv *priv) +{ + priv->debugfs_dir = debugfs_create_dir("fpga", NULL); + + if(IS_ERR(priv->debugfs_dir)) + return PTR_ERR(priv->debugfs_dir); + + debugfs_create_file("microchip_exec_update", 0200, priv->debugfs_dir, NULL, + &mpfs_auto_update_fops); + + return 0; +} + +static int mpfs_auto_update_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_auto_update_priv *priv; + struct fpga_manager *mgr; + enum fpga_mgr_states state; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->sys_controller = mpfs_sys_controller_get(dev); + if (IS_ERR(priv->sys_controller)) + return dev_err_probe(dev, PTR_ERR(priv->sys_controller), + "Could not register as a sub device of the system controller\n"); + + priv->dev = dev; + platform_set_drvdata(pdev, priv); + + mgr = devm_fpga_mgr_register(dev, "Microchip MPFS Auto Update FPGA Manager", + &mpfs_auto_update_ops, priv); + if (IS_ERR(mgr)) + return dev_err_probe(dev, PTR_ERR(mgr), "Could not register FPGA manager.\n"); + + state = mpfs_auto_update_state(mgr); + if (state != FPGA_MGR_STATE_OPERATING) + return -EIO; + + ret = mpfs_auto_update_debugfs_setup(priv); + if (ret && ret != -ENODEV) + return ret; + + mpfs_auto_update_debug_dev = priv->dev; + + return 0; +} + +static struct platform_driver mpfs_auto_update_driver = { + .driver = { + .name = "mpfs-auto-update", + }, + .probe = mpfs_auto_update_probe, +}; +module_platform_driver(mpfs_auto_update_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming"); From patchwork Fri Feb 17 16:40:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13145042 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DB40C6379F for ; Fri, 17 Feb 2023 16:41:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 17 Feb 2023 16:41:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83AB1C433D2; Fri, 17 Feb 2023 16:40:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1676652059; bh=AjGLCJDaBLeS+ZJn3SLxobc8nrc/IffXtF3vDUxqz3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DJZUfZJnxBBHc7U58XjuoN3nKx5tYwwfWvMR2Th9MWOHCJUNLBLpQTvlzEzhANqBg 9/3/flM25H3zbd4a4lV/1IVmMkTLVbyu7b9/w3JPxK792qbt5lqq0SuCrIOpnocGei JamiHe3RWjCsfJIUVjC1n0pPX2XJWAAyz+hzWt8Po4zzy7bjZRNSU6SZiPc/CK8zz7 vI+i/ytI7wIXaKDnkznja8D9vqq1gl+bAPHa0aLz7zLB3QDf7A0ua7/b5wbo7DCT8P KeYv8P+PWww3Gr8MMYyQp/cgpX5KP8xXe9XvT6LV+mrqLJmnEq3zR2rijr64wboTTS q4hT3s5P+3F1A== From: Conor Dooley To: Xu Yilun , conor@kernel.org Cc: Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Moritz Fischer , Wu Hao , Tom Rix , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v1 6/6] riscv: dts: microchip: add the mpfs' system controller qspi & associated flash Date: Fri, 17 Feb 2023 16:40:23 +0000 Message-Id: <20230217164023.14255-7-conor@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230217164023.14255-1-conor@kernel.org> References: <20230217164023.14255-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3434; i=conor.dooley@microchip.com; h=from:subject; bh=zi1BUMETDrjgTzSYci2/43ZGtuWfx3kHNh6ZsIx3EnU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMnv174taji+aGd1T7v7hmnptxf0/j/+TWbS4esnvu5es1/p zo3bNh2lLAxiHAyyYoosibf7WqTW/3HZ4dzzFmYOKxPIEAYuTgGYSEc7I8Pxv0r/94uLtlyYuI05O9 Mz3lZ6QmVdj3j8kpg5W/b9z4lmZLgfxHNHOGcjq8mVBye2SveKfDypZT6Z64XQxI0XbRZtrGYHAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230217_084102_523187_80D91563 X-CRM114-Status: GOOD ( 17.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The system controller's flash can be accessed via an MSS-exposed QSPI controller sitting, which sits between the mailbox's control & data registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it. The system controller and MSS both have separate QSPI controllers, both of which can access the flash, although the system controller takes priority. Unfortunately, on engineering sample silicon, such as that on Icicle kits, the MSS' QSPI controller cannot write to the flash due to a bug. As a workaround, a QSPI controller can be implemented in the FPGA fabric and the IO routing modified to connect it to the flash in place of the "hard" controller in the MSS. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit.dts | 21 ++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++----- 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 90b261114763..2dae3f8f33f6 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -199,6 +199,27 @@ &syscontroller { status = "okay"; }; +&syscontroller_qspi { + /* + * The flash *is* there, but Icicle kits that have engineering sample + * silicon (write?) access to this flash to non-functional. The system + * controller itself can actually access it, but the MSS cannot write + * an image there. Instantiating a coreQSPI in the fabric & connecting + * it to the flash instead should work though. Pre-production or later + * silicon does not have this issue. + */ + status = "disabled"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 0a9bb84af438..568da2b570c0 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -173,11 +173,6 @@ refclk: mssrefclk { #clock-cells = <0>; }; - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - mboxes = <&mbox 0>; - }; - soc { #address-cells = <2>; #size-cells = <2>; @@ -498,11 +493,28 @@ usb: usb@20201000 { mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>; status = "disabled"; }; + + syscontroller_qspi: spi@37020100 { + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x37020100 0x0 0x100>; + interrupt-parent = <&plic>; + interrupts = <110>; + clocks = <&clkcfg CLK_QSPI>; /* this is probably wrong, consult the docs! */ + status = "disabled"; + }; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; }; };