From patchwork Tue Feb 21 13:16:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13147938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAC20C64EC4 for ; Tue, 21 Feb 2023 13:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233719AbjBUNRJ (ORCPT ); Tue, 21 Feb 2023 08:17:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233908AbjBUNRI (ORCPT ); Tue, 21 Feb 2023 08:17:08 -0500 Received: from wout2-smtp.messagingengine.com (wout2-smtp.messagingengine.com [64.147.123.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68BC129159 for ; Tue, 21 Feb 2023 05:17:07 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id 9C588320093C; Tue, 21 Feb 2023 08:17:06 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 21 Feb 2023 08:17:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1676985426; x=1677071826; bh=6s lN4vS2XuBLOhdr95Q+OkSVr9EalJWOKOThLTuxc0c=; b=QUVph68YzLuEZvQyQE Gl3BXR8kBlt0Oj2e9mqpBzGq7zJOrCzAuvw1bZX3/cSpHVimQdoFk4i18MmsXcs3 koI2HO5dj+6LE8QB2YW1NBIRRUUVCs3zGBHtOOJ9EpgsLPMhNSZ1+eELSP+/JpIk 0JTs5PTAJErqsBGQ51O4mc9STSriAqgfYbUY5kFq9k/ENdgeOMYOSsc46I8G/tKc 2VQi5MEegOUIj+QHuUScehBvvHfq2Dzfgx9A/1bryaikU/wUru8JOJvR82+MNmum 29RjQPptKuzXXzEljmkwONiXYXUrjxBxngM743LMUBi41p8FuMRzSkNkm8ZrcI5M fa+w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1676985426; x=1677071826; bh=6slN4vS2XuBLO hdr95Q+OkSVr9EalJWOKOThLTuxc0c=; b=Odqj77gwMgSmLWonDUE52DlHcBVNJ mppz8XNL8YyscIF0C2KYEZkd/mjTkYDgH15zut4RA8+m+8QUdKRLtJm+yUOJM/tu rE19mCuU0WgQAQdFxa1sbp0Os/m37g3W+stAEZtdB7wB3BecfI36a16rHAHWEVFA uBfVEE2TdXqCCOn0UR7Ell+WL2UXjPuvhUdzzvXw01flE0wCA12qtv8SmuvfbP92 sYhLu3cPhz7XOy6wGhyZCuCWSljzmpJ8N4+RLYPKxmF9rBLlwE41d+hkexASUN+t tXiqxHKEF80vZeCqh7sNb6n6GoD2O7yk+LR94H7U4WfFI+ZhJbtiGzb9Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrudejjedggeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 21 Feb 2023 08:17:05 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, chenhuacai@kernel.org, Jiaxun Yang Subject: [PATCH 1/5] MIPS: Loongson64: Prefix ipi register address pointers with __iomem Date: Tue, 21 Feb 2023 13:16:54 +0000 Message-Id: <20230221131658.5381-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230221131658.5381-1-jiaxun.yang@flygoat.com> References: <20230221131658.5381-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org They are truely mmio pointers, so give them proper prefix. Signed-off-by: Jiaxun Yang --- arch/mips/loongson64/smp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 660e1de4412a..c268c6dd1ef1 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -27,11 +27,11 @@ DEFINE_PER_CPU(int, cpu_state); #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) -static void *ipi_set0_regs[16]; -static void *ipi_clear0_regs[16]; -static void *ipi_status0_regs[16]; -static void *ipi_en0_regs[16]; -static void *ipi_mailbox_buf[16]; +static void __iomem *ipi_set0_regs[16]; +static void __iomem *ipi_clear0_regs[16]; +static void __iomem *ipi_status0_regs[16]; +static void __iomem *ipi_en0_regs[16]; +static void __iomem *ipi_mailbox_buf[16]; static uint32_t core0_c0count[NR_CPUS]; /* read a 32bit value from ipi register */ From patchwork Tue Feb 21 13:16:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13147939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E53C4C6379F for ; Tue, 21 Feb 2023 13:17:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233725AbjBUNRL (ORCPT ); Tue, 21 Feb 2023 08:17:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233049AbjBUNRK (ORCPT ); Tue, 21 Feb 2023 08:17:10 -0500 Received: from wout2-smtp.messagingengine.com (wout2-smtp.messagingengine.com [64.147.123.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FED429159 for ; Tue, 21 Feb 2023 05:17:09 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id A92C03200920; Tue, 21 Feb 2023 08:17:08 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 21 Feb 2023 08:17:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1676985428; x=1677071828; bh=xv FzM+qQXUbgstzOzrk84FAc1qa8gBSZ5nJV4Zouwqo=; b=IyWNRpOHbh+s8U4vxw +vNFNahth9Rt4zPEhdiihgefKsfhHhv2Gwq6S6bIy7zZmc8ed9FBT6GQD5qF1Px9 ggxwBPh21lJ9rfGr6nzgn5mA6bCBnXedh1A7SuzW7JMpQYY/s5+6J/u9xileIC/S /lcMscuUJCKgOUsC/xyWzIWczl54VpqOMIkMJBulUQh1IDXDY+DYHZJ4zEKL/i6R g666d69NqkJKByPM3d7mzDM8ubm8pbzMvegiBDa810Q9XAkGOJpnpIUhuT198LlN AflbU7XRI1pslZHWLgVbFQKPFOkN9tR/B2uDIB4Hwnpo4SKlJVu5lC3TZLaQRw3e /wpg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1676985428; x=1677071828; bh=xvFzM+qQXUbgs tzOzrk84FAc1qa8gBSZ5nJV4Zouwqo=; b=lx71abO67qaI6VdJ2Dnru1IBkemO+ Uf08KToySjYQSiFfSLk8vcPtd8kfQPQzVBJNutCB0nEmZy/BjjOSgEpH6MSGX7iL +9NAtReYASBb+Aoqf2y4nLA6JSnVqQYlZDoUqE6Aw0aBBQ3sSVemv2XPKY+g6jk1 vpEV5JVXwNXcoPdHxdCe58+E0+UUYMs2tY0QKHQ3T62HqwIbtnYr5559za+q44v5 lqR5vLYh4WsT2l5atbboQZLBT1gNB2/o4Y93UXe3K1iTcLsMvDIru5rlYX7d+I62 8AOU1leJgYgUq9TSTrEd6kmcNJsIO1vWGCcQGjnvCgU3II9ebTbVQbdUA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrudejjedggeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 21 Feb 2023 08:17:07 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, chenhuacai@kernel.org, Jiaxun Yang Subject: [PATCH 2/5] MIPS: Loongson64: smp: Use nudge_writes instead of wbflush Date: Tue, 21 Feb 2023 13:16:55 +0000 Message-Id: <20230221131658.5381-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230221131658.5381-1-jiaxun.yang@flygoat.com> References: <20230221131658.5381-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org wbflush here intends to let other cores see the results ASAP, nudge_writes fits this purpose better. Signed-off-by: Jiaxun Yang --- arch/mips/loongson64/smp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index c268c6dd1ef1..e9d91da7fe24 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -42,13 +42,13 @@ static uint32_t core0_c0count[NR_CPUS]; #define loongson3_ipi_write32(action, addr) \ do { \ writel(action, addr); \ - __wbflush(); \ + nudge_writes(); \ } while (0) /* write a 64bit value to ipi register */ #define loongson3_ipi_write64(action, addr) \ do { \ writeq(action, addr); \ - __wbflush(); \ + nudge_writes(); \ } while (0) static u32 (*ipi_read_clear)(int cpu); @@ -418,7 +418,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) c0count = c0count ? c0count : 1; for (i = 1; i < nr_cpu_ids; i++) core0_c0count[i] = c0count; - __wbflush(); /* Let others see the result ASAP */ + nudge_writes(); /* Let others see the result ASAP */ } return IRQ_HANDLED; From patchwork Tue Feb 21 13:16:56 2023 Content-Type: text/plain; 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Tue, 21 Feb 2023 08:17:09 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, chenhuacai@kernel.org, Jiaxun Yang Subject: [PATCH 3/5] MIPS: Loongson64: smp: Correct nudge_writes usage Date: Tue, 21 Feb 2023 13:16:56 +0000 Message-Id: <20230221131658.5381-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230221131658.5381-1-jiaxun.yang@flygoat.com> References: <20230221131658.5381-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Previously every write to SMP regisers are followed by nudge_writes, this incures a huge performance penalty because nudge_writes involves SYNC, which will be globalized on chip. Only set off nudge_writes when we really want other cores to see the result ASAP. Also replace read/write functions to relaxed version because we don't need extra barriers to protect against DMA. Signed-off-by: Jiaxun Yang --- arch/mips/loongson64/smp.c | 38 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index e9d91da7fe24..90c783981197 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -34,23 +34,6 @@ static void __iomem *ipi_en0_regs[16]; static void __iomem *ipi_mailbox_buf[16]; static uint32_t core0_c0count[NR_CPUS]; -/* read a 32bit value from ipi register */ -#define loongson3_ipi_read32(addr) readl(addr) -/* read a 64bit value from ipi register */ -#define loongson3_ipi_read64(addr) readq(addr) -/* write a 32bit value to ipi register */ -#define loongson3_ipi_write32(action, addr) \ - do { \ - writel(action, addr); \ - nudge_writes(); \ - } while (0) -/* write a 64bit value to ipi register */ -#define loongson3_ipi_write64(action, addr) \ - do { \ - writeq(action, addr); \ - nudge_writes(); \ - } while (0) - static u32 (*ipi_read_clear)(int cpu); static void (*ipi_write_action)(int cpu, u32 action); static void (*ipi_write_enable)(int cpu); @@ -136,26 +119,28 @@ static u32 legacy_ipi_read_clear(int cpu) u32 action; /* Load the ipi register to figure out what we're supposed to do */ - action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); + action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]); /* Clear the ipi register to clear the interrupt */ - loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); + writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]); + nudge_writes(); return action; } static void legacy_ipi_write_action(int cpu, u32 action) { - loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); + writel_relaxed((u32)action, ipi_set0_regs[cpu]); + nudge_writes(); } static void legacy_ipi_write_enable(int cpu) { - loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); + writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); } static void legacy_ipi_clear_buf(int cpu) { - loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); + writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); } static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) @@ -171,14 +156,15 @@ static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", cpu, startargs[0], startargs[1], startargs[2]); - loongson3_ipi_write64(startargs[3], + writeq_relaxed(startargs[3], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); - loongson3_ipi_write64(startargs[2], + writeq_relaxed(startargs[2], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); - loongson3_ipi_write64(startargs[1], + writeq_relaxed(startargs[1], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); - loongson3_ipi_write64(startargs[0], + writeq_relaxed(startargs[0], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); + nudge_writes(); } static void csr_ipi_probe(void) From patchwork Tue Feb 21 13:16:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13147941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CAF1C61DA3 for ; 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Tue, 21 Feb 2023 08:17:12 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, chenhuacai@kernel.org, Jiaxun Yang Subject: [PATCH 4/5] MIPS: Loongson64: Remove CPU_HAS_WB Date: Tue, 21 Feb 2023 13:16:57 +0000 Message-Id: <20230221131658.5381-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230221131658.5381-1-jiaxun.yang@flygoat.com> References: <20230221131658.5381-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Q: Do we have really have write buffer A: Yes, on newer Loongson processors there is a "store fill buffer" that will collect *cached* writes, on all Loongson processors AXI crossbar will buffer all writes. Q: Then why do we want to remove CPU_HAS_WB? A: Because CPU_HAS_WB introduces wbflush, which intends to flush all write reuqests to mmio device. We won't be affected by store fill buffer because it won't buffer uncached writes. And a regular memory barrier is sufficient to flush crossbar write buffer. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 1 - arch/mips/loongson64/setup.c | 15 --------------- 2 files changed, 16 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 04a9a3889d75..04b09b82cb76 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -489,7 +489,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 3cd11c2b308b..257038e18779 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -17,20 +16,6 @@ void *loongson_fdt_blob; -static void wbflush_loongson(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void (*__wbflush)(void) = wbflush_loongson; -EXPORT_SYMBOL(__wbflush); - void __init plat_mem_setup(void) { if (loongson_fdt_blob) From patchwork Tue Feb 21 13:16:58 2023 Content-Type: text/plain; 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Tue, 21 Feb 2023 08:17:14 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, chenhuacai@kernel.org, Jiaxun Yang Subject: [PATCH 5/5] MIPS: Loongson64: Opt-out war_io_reorder_wmb Date: Tue, 21 Feb 2023 13:16:58 +0000 Message-Id: <20230221131658.5381-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230221131658.5381-1-jiaxun.yang@flygoat.com> References: <20230221131658.5381-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It is clearly stated on "Loongson 3A3000/3B3000 processor user manual vol 2" that "All access requests using a non-cached algorithm are executed in a blocking order. That is, before the current read request data is returned to the processor, all subsequent requests are blocked and issued; All subsequent requests are blocked until the write request data has been sent or the issued write request has not received a write reply from the final receiver." Which means uncached read/write is strongly ordered. So we won't need this workaround. This option was introduced when we add initial support for GS464E, it looks like a misinterpretation of another section in the manual saying we need barriers to ensure MMIO order against DMA requests. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index d727e07ed3f0..9b611770c261 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr); #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier()