From patchwork Wed Feb 22 03:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B731C64EC7 for ; Wed, 22 Feb 2023 03:04:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231465AbjBVDEx (ORCPT ); Tue, 21 Feb 2023 22:04:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231400AbjBVDEv (ORCPT ); Tue, 21 Feb 2023 22:04:51 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8C3422793; Tue, 21 Feb 2023 19:04:46 -0800 (PST) X-UUID: a4a28f3eb25d11eda06fc9ecc4dadd91-20230222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sZ+Ho6D3GzcqC75fnBa9IEq7DWgGM+MATdvdfGh6gAg=; b=dXNZFT09h0UEv6hngZCaT5JNdrxtewTeHC2MCUKZvAj6QEIdvZkjF9MnsC+DRI/nZO/P6xisTu/BzobNOmD5AgfuTnCKYsIaPPRRGanMcpYasxP7U4NsHWDtyrHkZhCVXnOfCvyPTmmVZQzNIV6AgYmX9+Mb3K2iSZdcGwqnx5U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:78d92be7-0454-494d-a46a-51d0712973ec,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:25b5999,CLOUDID:c9bfbcf3-ddba-41c3-91d9-10eeade8eac7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: a4a28f3eb25d11eda06fc9ecc4dadd91-20230222 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 694651841; Wed, 22 Feb 2023 11:04:38 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:37 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 1/7] scsi: ufs: core: Fix mcq tag calcualtion Date: Wed, 22 Feb 2023 11:04:18 +0800 Message-ID: <20230222030427.957-2-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Transfer command descriptor is allocated in ufshcd_memory_alloc() and referenced by transfer request descriptor with stride size sizeof_utp_transfer_cmd_desc() instead of sizeof(struct utp_transfer_cmd_desc). Consequently, computing tag by address offset should also refer to the same stride. Signed-off-by: Po-Wen Kao Reviewed-by: Bart Van Assche Reviewed-by: Manivannan Sadhasivam Reviewed-by: Stanley Chu reviewed-by:  Ziqi Chen --- drivers/ufs/core/ufs-mcq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 31df052fbc41..3a27fa4b0024 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -265,7 +265,7 @@ static int ufshcd_mcq_get_tag(struct ufs_hba *hba, addr = (le64_to_cpu(cqe->command_desc_base_addr) & CQE_UCD_BA) - hba->ucdl_dma_addr; - return div_u64(addr, sizeof(struct utp_transfer_cmd_desc)); + return div_u64(addr, sizeof_utp_transfer_cmd_desc(hba)); } static void ufshcd_mcq_process_cqe(struct ufs_hba *hba, From patchwork Wed Feb 22 03:04:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CED1C61DA3 for ; Wed, 22 Feb 2023 03:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231494AbjBVDE5 (ORCPT ); Tue, 21 Feb 2023 22:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231442AbjBVDEw (ORCPT ); Tue, 21 Feb 2023 22:04:52 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80A982312B; Tue, 21 Feb 2023 19:04:47 -0800 (PST) X-UUID: a5b382a2b25d11ed945fc101203acc17-20230222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=m3eXF39txh6c76bLHqw0R93HCRiA2dN4IhRPifLF9Y8=; b=NM3R6POx7pkBtV09ssyCBqybtdwSOT9wMUjbWXIZ1vv3cfMNt6MQq4hY9y3xPtm5qIEsgA0AkRf7Iqjv+r6Lb7WRlGaLO0XIuNcE/mks12qKaeOoaU5o756V0+VV+MvCEptS6TFa8YzVMxX+yHTuBHyuphdNyhQ7ZOH7I4e2ywQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:9cae7ae7-d2fd-497b-9bc9-0b986ada741d,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.20,REQID:9cae7ae7-d2fd-497b-9bc9-0b986ada741d,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:25b5999,CLOUDID:a3452fb1-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230222110443GGJHAGCY,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: a5b382a2b25d11ed945fc101203acc17-20230222 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1983994696; Wed, 22 Feb 2023 11:04:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:38 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 2/7] scsi: ufs: core: Rename symbols Date: Wed, 22 Feb 2023 11:04:19 +0800 Message-ID: <20230222030427.957-3-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org To avoid confusion, sizeof_utp_transfer_cmd_desc() is renamed to ufshcd_get_ucd_size(). Signed-off-by: Po-Wen Kao Reviewed-by: Stanley Chu reviewed-by:  Ziqi Chen Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufs-mcq.c | 2 +- drivers/ufs/core/ufshcd.c | 8 ++++---- include/ufs/ufshcd.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 3a27fa4b0024..a39746b2a8be 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -265,7 +265,7 @@ static int ufshcd_mcq_get_tag(struct ufs_hba *hba, addr = (le64_to_cpu(cqe->command_desc_base_addr) & CQE_UCD_BA) - hba->ucdl_dma_addr; - return div_u64(addr, sizeof_utp_transfer_cmd_desc(hba)); + return div_u64(addr, ufshcd_get_ucd_size(hba)); } static void ufshcd_mcq_process_cqe(struct ufs_hba *hba, diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 3b3cf78d3b10..81c9f07ebfc8 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2823,10 +2823,10 @@ static void ufshcd_map_queues(struct Scsi_Host *shost) static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) { struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + - i * sizeof_utp_transfer_cmd_desc(hba); + i * ufshcd_get_ucd_size(hba); struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + - i * sizeof_utp_transfer_cmd_desc(hba); + i * ufshcd_get_ucd_size(hba); u16 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); @@ -3735,7 +3735,7 @@ static int ufshcd_memory_alloc(struct ufs_hba *hba) size_t utmrdl_size, utrdl_size, ucdl_size; /* Allocate memory for UTP command descriptors */ - ucdl_size = sizeof_utp_transfer_cmd_desc(hba) * hba->nutrs; + ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, ucdl_size, &hba->ucdl_dma_addr, @@ -3835,7 +3835,7 @@ static void ufshcd_host_memory_configure(struct ufs_hba *hba) prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); - cmd_desc_size = sizeof_utp_transfer_cmd_desc(hba); + cmd_desc_size = ufshcd_get_ucd_size(hba); cmd_desc_dma_addr = hba->ucdl_dma_addr; for (i = 0; i < hba->nutrs; i++) { diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index ed9e3d5addb3..8f79cca449e1 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1136,7 +1136,7 @@ static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) #endif -static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) +static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) { return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); } From patchwork Wed Feb 22 03:04:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FD9CC677F1 for ; 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Wed, 22 Feb 2023 11:04:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:39 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 3/7] scsi: ufs: core: Fix mcq nr_hw_queues Date: Wed, 22 Feb 2023 11:04:20 +0800 Message-ID: <20230222030427.957-4-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Need to add one to MAXQ to obtain number of hardware queue. Signed-off-by: Po-Wen Kao Reviewed-by: Stanley Chu Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufs-mcq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index a39746b2a8be..5d5bc0bc6e88 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -150,7 +150,7 @@ static int ufshcd_mcq_config_nr_queues(struct ufs_hba *hba) u32 hba_maxq, rem, tot_queues; struct Scsi_Host *host = hba->host; - hba_maxq = FIELD_GET(MAX_QUEUE_SUP, hba->mcq_capabilities); + hba_maxq = FIELD_GET(MAX_QUEUE_SUP, hba->mcq_capabilities) + 1 ; tot_queues = UFS_MCQ_NUM_DEV_CMD_QUEUES + read_queues + poll_queues + rw_queues; From patchwork Wed Feb 22 03:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52E0FC64EC7 for ; Wed, 22 Feb 2023 03:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230424AbjBVDE7 (ORCPT ); Tue, 21 Feb 2023 22:04:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231418AbjBVDEx (ORCPT ); Tue, 21 Feb 2023 22:04:53 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E91E32313B; Tue, 21 Feb 2023 19:04:49 -0800 (PST) X-UUID: a6d0ecceb25d11eda06fc9ecc4dadd91-20230222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nQ1FI+tZAutpfgYwGq8uJe/0tKi1xigqaET55cH0i18=; b=n7L0jHbvXc6KR79OOT0ES2APw3aba7Fa0oA7e59H4ATGvXV9bo1kFdGKcD50mYap7B6GlmDBUIMQjj8axa3T9Y9o6VPz9+pMEFG67fd+Q/kgeVJBwtTh+XuJoKj4EwLuDuC8rmZhG8/gJ+U646tIVa/CowEpgC0qBup/wEGIlQw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:a43d1e02-80e8-4257-b57d-52f4a73d6184,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:25b5999,CLOUDID:d5452fb1-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: a6d0ecceb25d11eda06fc9ecc4dadd91-20230222 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1563489553; Wed, 22 Feb 2023 11:04:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:40 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 4/7] scsi: ufs: core: Add hwq print for debug Date: Wed, 22 Feb 2023 11:04:21 +0800 Message-ID: <20230222030427.957-5-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Introduce hwq printing function for debug purpose. - ufshcd_mcq_print_hwqs() Signed-off-by: Po-Wen Kao --- drivers/ufs/core/ufs-mcq.c | 32 +++++++++++++++++++++++++++++++- drivers/ufs/core/ufshcd-priv.h | 9 +++++++++ drivers/ufs/core/ufshcd.c | 18 +++++++++++------- include/ufs/ufshci.h | 12 ++++++++++++ 4 files changed, 63 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 5d5bc0bc6e88..d1ff3ccd2085 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -23,7 +23,6 @@ #define MAX_DEV_CMD_ENTRIES 2 #define MCQ_CFG_MAC_MASK GENMASK(16, 8) -#define MCQ_QCFG_SIZE 0x40 #define MCQ_ENTRY_SIZE_IN_DWORD 8 #define CQE_UCD_BA GENMASK_ULL(63, 7) @@ -75,6 +74,13 @@ module_param_cb(poll_queues, &poll_queue_count_ops, &poll_queues, 0644); MODULE_PARM_DESC(poll_queues, "Number of poll queues used for r/w. Default value is 1"); +static const int mcq_opr_size[] = { + MCQ_SQD_SIZE, + MCQ_SQIS_SIZE, + MCQ_CQD_SIZE, + MCQ_CQIS_SIZE, +}; + /** * ufshcd_mcq_config_mac - Set the #Max Activ Cmds. * @hba: per adapter instance @@ -237,6 +243,30 @@ static void __iomem *mcq_opr_base(struct ufs_hba *hba, return opr->base + opr->stride * i; } +void ufshcd_mcq_print_hwqs(struct ufs_hba *hba, unsigned long bitmap) +{ + int id, i; + char prefix[15]; + + if (!is_mcq_enabled(hba)) + return; + + for_each_set_bit(id, &bitmap, hba->nr_hw_queues) { + snprintf(prefix, sizeof(prefix), "q%d SQCFG: ", id); + ufshcd_hex_dump(prefix, + hba->mcq_base + MCQ_QCFG_SIZE * id, MCQ_QCFG_SQ_SIZE); + + snprintf(prefix, sizeof(prefix), "q%d CQCFG: ", id); + ufshcd_hex_dump(prefix, + hba->mcq_base + MCQ_QCFG_SIZE * id + MCQ_QCFG_SQ_SIZE, MCQ_QCFG_CQ_SIZE); + + for (i = 0; i < OPR_MAX ; i++) { + snprintf(prefix, sizeof(prefix), "q%d OPR%d: ", id, i); + ufshcd_hex_dump(prefix, mcq_opr_base(hba, i, id), mcq_opr_size[i]); + } + } +} + u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i) { return readl(mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIS); diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 529f8507a5e4..13534a9a6d0a 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -6,6 +6,14 @@ #include #include +#define ufshcd_hex_dump(prefix_str, buf, len) do { \ + size_t __len = (len); \ + print_hex_dump(KERN_ERR, prefix_str, \ + __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ + 16, 4, buf, __len, false); \ +} while (0) + + static inline bool ufshcd_is_user_access_allowed(struct ufs_hba *hba) { return !hba->shutting_down; @@ -65,6 +73,7 @@ void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, struct cq_entry *cqe); int ufshcd_mcq_init(struct ufs_hba *hba); int ufshcd_mcq_decide_queue_depth(struct ufs_hba *hba); +void ufshcd_mcq_print_hwqs(struct ufs_hba *hba, unsigned long bitmap); int ufshcd_mcq_memory_alloc(struct ufs_hba *hba); void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 81c9f07ebfc8..a15a5a78160c 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -135,13 +135,6 @@ MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from U _ret; \ }) -#define ufshcd_hex_dump(prefix_str, buf, len) do { \ - size_t __len = (len); \ - print_hex_dump(KERN_ERR, prefix_str, \ - __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ - 16, 4, buf, __len, false); \ -} while (0) - int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, const char *prefix) { @@ -536,6 +529,8 @@ static void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt) { const struct ufshcd_lrb *lrbp; + struct ufs_hw_queue *hwq; + struct scsi_cmnd *cmd; int prdt_length; int tag; @@ -574,7 +569,16 @@ void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt) if (pr_prdt) ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, ufshcd_sg_entry_size(hba) * prdt_length); + + if (is_mcq_enabled(hba)) { + cmd = lrbp->cmd; + if (!cmd) + return; + hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); + ufshcd_mcq_print_hwqs(hba, 1 << hwq->id); + } } + } static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 11424bb03814..027a2e884f89 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -185,6 +185,18 @@ static inline u32 ufshci_version(u32 major, u32 minor) CRYPTO_ENGINE_FATAL_ERROR |\ UIC_LINK_LOST) +/* MCQ size */ +#define MCQ_QCFG_SIZE 0x40 +#define MCQ_QCFG_SQ_SIZE 0x20 +#define MCQ_QCFG_CQ_SIZE 0x20 + +enum { + MCQ_SQD_SIZE = 0x14, + MCQ_SQIS_SIZE = 0x08, + MCQ_CQD_SIZE = 0x08, + MCQ_CQIS_SIZE = 0x0C, +}; + /* HCS - Host Controller Status 30h */ #define DEVICE_PRESENT 0x1 #define UTP_TRANSFER_REQ_LIST_READY 0x2 From patchwork Wed Feb 22 03:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14886C64EC7 for ; Wed, 22 Feb 2023 03:05:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231496AbjBVDE6 (ORCPT ); Tue, 21 Feb 2023 22:04:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231445AbjBVDEx (ORCPT ); Tue, 21 Feb 2023 22:04:53 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9DFA22036; Tue, 21 Feb 2023 19:04:48 -0800 (PST) X-UUID: a6d33ae2b25d11eda06fc9ecc4dadd91-20230222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uUPi2ZSWfI++WL4hrgAmgPLvqEWeMq/jBrseBDMZg3Q=; b=W7+Mvh4egeHNkYxFjHyr/EEN0+RinaUhKJVszCXaztiIujB3NM78Buc8zHEEtmzmAx+km9N7V31AUpUn1yD7kbkPevGt4Ko7f6mTGAryxl1zY2+dW64OQCx1nfQFDG2AzAR3f+D8yF5GZ4XyK70MdQxsSrxDroFY8G/oun2zpFs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:ae3d4f4a-5780-464a-ba01-e1bc70497e84,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:25b5999,CLOUDID:369f4e26-564d-42d9-9875-7c868ee415ec,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: a6d33ae2b25d11eda06fc9ecc4dadd91-20230222 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1315282765; Wed, 22 Feb 2023 11:04:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:41 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 5/7] scsi: ufs: core: Remove redundant check Date: Wed, 22 Feb 2023 11:04:22 +0800 Message-ID: <20230222030427.957-6-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org is_mcq_supported() already check on use_mcq_mode. Signed-off-by: Po-Wen Kao Reviewed-by: Stanley Chu reviewed-by:  Ziqi Chen --- drivers/ufs/core/ufshcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index a15a5a78160c..21e3bf5d8f08 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8548,7 +8548,7 @@ static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) hba->scsi_host_added = true; } /* MCQ may be disabled if ufshcd_alloc_mcq() fails */ - if (is_mcq_supported(hba) && use_mcq_mode) + if (is_mcq_supported(hba)) ufshcd_config_mcq(hba); } From patchwork Wed Feb 22 03:04:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13148674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36079C61DA3 for ; Wed, 22 Feb 2023 03:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231520AbjBVDFB (ORCPT ); Tue, 21 Feb 2023 22:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229884AbjBVDEz (ORCPT ); Tue, 21 Feb 2023 22:04:55 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13AEB2313C; Tue, 21 Feb 2023 19:04:49 -0800 (PST) X-UUID: a7ef488ab25d11ed945fc101203acc17-20230222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5wNgkfU0gfaGyQfCQ6XlpXp67iExe5GxmfD+aZq/3ac=; b=Z5frGqSe+snUYq9g0Q9G/UfkVg/7BnespghAMjqhZoHUr+ScY/EQ8d9pv9lZBCxlN0TIgcWDPsh8nKaAUK/ZTnAmkvmQn36KSOjlnext3uKfV2nyZIGPG0J0JPy5rMOAu/6X3PVV3s+IGCvNVC9RmJwmr4nyDRQH5cYciqkdNwo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:c48f32a0-d3fb-4e7f-bb48-eb85c03fc810,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.20,REQID:c48f32a0-d3fb-4e7f-bb48-eb85c03fc810,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:25b5999,CLOUDID:2b462fb1-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230222110445BQVTN36P,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: a7ef488ab25d11ed945fc101203acc17-20230222 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1985632930; Wed, 22 Feb 2023 11:04:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 22 Feb 2023 11:04:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:42 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , Subject: [PATCH v2 6/7] scsi: ufs: core: Export symbols for MTK driver module Date: Wed, 22 Feb 2023 11:04:23 +0800 Message-ID: <20230222030427.957-7-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Export - ufshcd_mcq_config_mac - ufshcd_mcq_make_queues_operational - ufshcd_mcq_read_cqis - ufshcd_disable_intr Signed-off-by: Po-Wen Kao Reviewed-by: Stanley Chu --- drivers/ufs/core/ufs-mcq.c | 3 +++ drivers/ufs/core/ufshcd-priv.h | 2 -- drivers/ufs/core/ufshcd.c | 3 ++- include/ufs/ufshcd.h | 6 ++++++ 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index d1ff3ccd2085..ae67ab90bd29 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -98,6 +98,7 @@ void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds) val |= FIELD_PREP(MCQ_CFG_MAC_MASK, max_active_cmds); ufshcd_writel(hba, val, REG_UFS_MCQ_CFG); } +EXPORT_SYMBOL_GPL(ufshcd_mcq_config_mac); /** * ufshcd_mcq_req_to_hwq - find the hardware queue on which the @@ -271,6 +272,7 @@ u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i) { return readl(mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIS); } +EXPORT_SYMBOL_GPL(ufshcd_mcq_read_cqis); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i) { @@ -401,6 +403,7 @@ void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba) MCQ_CFG_n(REG_SQATTR, i)); } } +EXPORT_SYMBOL_GPL(ufshcd_mcq_make_queues_operational); void ufshcd_mcq_enable_esi(struct ufs_hba *hba) { diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 13534a9a6d0a..1c83a6bc88b7 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -75,8 +75,6 @@ int ufshcd_mcq_init(struct ufs_hba *hba); int ufshcd_mcq_decide_queue_depth(struct ufs_hba *hba); void ufshcd_mcq_print_hwqs(struct ufs_hba *hba, unsigned long bitmap); int ufshcd_mcq_memory_alloc(struct ufs_hba *hba); -void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); -void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); void ufshcd_mcq_select_mcq_mode(struct ufs_hba *hba); u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 21e3bf5d8f08..a0848a8e2e6f 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2567,7 +2567,7 @@ static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) * @hba: per adapter instance * @intrs: interrupt bits */ -static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) +void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) { u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); @@ -2583,6 +2583,7 @@ static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); } +EXPORT_SYMBOL_GPL(ufshcd_disable_intr); /** * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 8f79cca449e1..d4dc7bcec127 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1230,6 +1230,7 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) int ufshcd_alloc_host(struct device *, struct ufs_hba **); void ufshcd_dealloc_host(struct ufs_hba *); +void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs); int ufshcd_hba_enable(struct ufs_hba *hba); int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); int ufshcd_link_recovery(struct ufs_hba *hba); @@ -1242,9 +1243,14 @@ void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); void ufshcd_hba_stop(struct ufs_hba *hba); void ufshcd_schedule_eh_work(struct ufs_hba *hba); + +void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); +u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); + unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, struct ufs_hw_queue *hwq); +void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); void ufshcd_mcq_enable_esi(struct ufs_hba *hba); void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); From patchwork Wed Feb 22 03:04:24 2023 Content-Type: text/plain; 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Wed, 22 Feb 2023 11:04:44 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 22 Feb 2023 11:04:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 22 Feb 2023 11:04:43 +0800 From: Po-Wen Kao To: , , , , Stanley Chu , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , Subject: [PATCH v2 7/7] scsi: ufs: mtk-host: Add MCQ support for MTK platform Date: Wed, 22 Feb 2023 11:04:24 +0800 Message-ID: <20230222030427.957-8-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230222030427.957-1-powen.kao@mediatek.com> References: <20230222030427.957-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Changes - Implement vops and setup irq - Fix pm flow under mcq mode Signed-off-by: Po-Wen Kao --- drivers/ufs/host/ufs-mediatek.c | 193 +++++++++++++++++++++++++++++++- drivers/ufs/host/ufs-mediatek.h | 33 ++++++ 2 files changed, 224 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 21d9b047539f..162bbde675aa 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -30,6 +30,14 @@ #define CREATE_TRACE_POINTS #include "ufs-mediatek-trace.h" +static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq); +static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba); + +#define MAX_SUPP_MAC 64 +#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200) + +static unsigned int mtk_mcq_irq[UFSHCD_MAX_Q_NR]; + static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = { { .wmanufacturerid = UFS_ANY_VENDOR, .model = UFS_ANY_MODEL, @@ -843,6 +851,19 @@ static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba) } } +static void ufs_mtk_init_interrupt(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + int i; + + host->mcq_nr_intr = UFSHCD_MAX_Q_NR; + + for (i = 0; i < host->mcq_nr_intr; i++) { + host->mcq_intr_info[i].hba = hba; + host->mcq_intr_info[i].intr = mtk_mcq_irq[i]; + } +} + /** * ufs_mtk_init - find other essential mmio bases * @hba: host controller instance @@ -879,6 +900,8 @@ static int ufs_mtk_init(struct ufs_hba *hba) /* Initialize host capability */ ufs_mtk_init_host_caps(hba); + ufs_mtk_init_interrupt(hba); + err = ufs_mtk_bind_mphy(hba); if (err) goto out_variant_clear; @@ -1174,7 +1197,16 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) else return err; - err = ufshcd_make_hba_operational(hba); + if (!hba->mcq_enabled) + err = ufshcd_make_hba_operational(hba); + else { + ufs_mtk_config_mcq(hba, false); + ufshcd_mcq_make_queues_operational(hba); + ufshcd_mcq_config_mac(hba, hba->nutrs); + ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, + REG_UFS_MEM_CFG); + } + if (err) return err; @@ -1361,6 +1393,12 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10); } + /* + * Disable MCQ_CQ_EVENT interrupt. + * Use CQ Tail Entry Push Status instead. + */ + ufshcd_disable_intr(hba, MCQ_CQ_EVENT_STATUS); + /* * Decide waiting time before gating reference clock and * after ungating reference clock according to vendors' @@ -1498,6 +1536,116 @@ static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up, return 0; } +static int ufs_mtk_get_hba_mac(struct ufs_hba *hba) +{ + return MAX_SUPP_MAC; +} + +static int ufs_mtk_op_runtime_config(struct ufs_hba *hba) +{ + struct ufshcd_mcq_opr_info_t *opr; + int i; + + for (i = 0; i < OPR_MAX; i++) { + opr = &hba->mcq_opr[i]; + opr->stride = REG_UFS_MCQ_STRIDE; + } + + hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS; + + hba->mcq_opr[OPR_SQD].base = hba->mmio_base + REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].base = hba->mmio_base + REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].base = hba->mmio_base + REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].base = hba->mmio_base + REG_UFS_MTK_CQIS; + + return 0; +} + +static int ufs_mtk_mcq_config_resource(struct ufs_hba *hba) +{ + hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities); + return 0; +} + +static irqreturn_t ufs_mtk_mcq_intr(int irq, void *__intr_info) +{ + struct ufs_mtk_mcq_intr_info *mcq_intr_info = __intr_info; + struct ufs_hba *hba = mcq_intr_info->hba; + struct ufs_hw_queue *hwq; + u32 events; + int i = mcq_intr_info->qid; + + hwq = &hba->uhq[i]; + + events = ufshcd_mcq_read_cqis(hba, i); + if (events) + ufshcd_mcq_write_cqis(hba, events, i); + + if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) + ufshcd_mcq_poll_cqe_nolock(hba, hwq); + + return IRQ_HANDLED; +} + +static int ufs_mtk_config_mcq_irq(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + u32 irq, i; + int ret; + + for (i = 0; i < host->mcq_nr_intr; i++) { + irq = host->mcq_intr_info[i].intr; + if (irq == MTK_MCQ_INVALID_IRQ) { + dev_err(hba->dev, "invalid irq. %d\n", i); + return -ENOPARAM; + } + + host->mcq_intr_info[i].qid = i; + ret = devm_request_irq(hba->dev, irq, ufs_mtk_mcq_intr, 0, UFSHCD, + &host->mcq_intr_info[i]); + + dev_info(hba->dev, "request irq %d intr %s\n", irq, ret ? "failed": ""); + + if (ret) + return ret; + } + + return 0; +} + +static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + int ret = 0; + + if (!host->mcq_set_intr) { + + /* Disable irq option register */ + ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0); + + if (irq) + ret = ufs_mtk_config_mcq_irq(hba); + + if (ret) + return ret; + + host->mcq_set_intr = true; + } + + ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0); + ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0); + + return 0; +} + +static int ufs_mtk_config_esi(struct ufs_hba *hba) +{ + return ufs_mtk_config_mcq(hba, true); +} + /* * struct ufs_hba_mtk_vops - UFS MTK specific variant operations * @@ -1521,8 +1669,43 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { .event_notify = ufs_mtk_event_notify, .config_scaling_param = ufs_mtk_config_scaling_param, .clk_scale_notify = ufs_mtk_clk_scale_notify, + /* mcq vops */ + .get_hba_mac = ufs_mtk_get_hba_mac, + .op_runtime_config = ufs_mtk_op_runtime_config, + .mcq_config_resource = ufs_mtk_mcq_config_resource, + .config_esi = ufs_mtk_config_esi, }; +static int ufs_mtk_mcq_get_irq(struct platform_device *pdev) +{ + int i, irq, cnt; + + for (i = 0; i < UFSHCD_MAX_Q_NR; i++) + mtk_mcq_irq[i] = MTK_MCQ_INVALID_IRQ; + + cnt = platform_irq_count(pdev); + + if (cnt < 0) + return cnt; + + /* no irq for mcq */ + if (cnt == 1) + return 0; + + for (i = 0; i < UFSHCD_MAX_Q_NR; i++) { + /* irq index 0 is ufshcd system irq, sq, cq irq start from index 1 */ + irq = platform_get_irq(pdev, i + 1); + if (irq < 0) { + dev_err(&pdev->dev, "get platform mcq irq fail: %d\n", i); + return irq; + } + mtk_mcq_irq[i] = irq; + dev_info(&pdev->dev, "get platform mcq irq: %d, %d\n", i, irq); + } + + return 0; +} + /** * ufs_mtk_probe - probe routine of the driver * @pdev: pointer to Platform device handle @@ -1562,12 +1745,18 @@ static int ufs_mtk_probe(struct platform_device *pdev) } skip_reset: + err = ufs_mtk_mcq_get_irq(pdev); + if (err) { + dev_err(dev, "get irq failed %d\n", err); + goto out; + } + /* perform generic probe */ err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); out: if (err) - dev_info(dev, "probe failed %d\n", err); + dev_err(dev, "probe failed %d\n", err); of_node_put(reset_node); return err; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index 2fc6d7b87694..542b4c3a763c 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -10,11 +10,27 @@ #include #include +/* + * MCQ define and struct + */ +#define UFSHCD_MAX_Q_NR 8 +#define MTK_MCQ_INVALID_IRQ 0xFFFF + +/* REG_UFS_MMIO_OPT_CTRL_0 160h */ +#define EHS_EN 0x1 +#define PFM_IMPV 0x2 +#define MCQ_MULTI_INTR_EN 0x4 +#define MCQ_CMB_INTR_EN 0x8 +#define MCQ_AH8 0x10 + +#define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN) + /* * Vendor specific UFSHCI Registers */ #define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_REFCLK_CTRL 0x144 +#define REG_UFS_MMIO_OPT_CTRL_0 0x160 #define REG_UFS_EXTREG 0x2100 #define REG_UFS_MPHYCTRL 0x2200 #define REG_UFS_MTK_IP_VER 0x2240 @@ -26,6 +42,13 @@ #define REG_UFS_DEBUG_SEL_B2 0x22D8 #define REG_UFS_DEBUG_SEL_B3 0x22DC +#define REG_UFS_MTK_SQD 0x2800 +#define REG_UFS_MTK_SQIS 0x2814 +#define REG_UFS_MTK_CQD 0x281C +#define REG_UFS_MTK_CQIS 0x2824 + +#define REG_UFS_MCQ_STRIDE 0x30 + /* * Ref-clk control * @@ -136,6 +159,12 @@ struct ufs_mtk_hw_ver { u8 major; }; +struct ufs_mtk_mcq_intr_info { + struct ufs_hba *hba; + u32 intr; + u8 qid; +}; + struct ufs_mtk_host { struct phy *mphy; struct pm_qos_request pm_qos_req; @@ -155,6 +184,10 @@ struct ufs_mtk_host { u16 ref_clk_ungating_wait_us; u16 ref_clk_gating_wait_us; u32 ip_ver; + + bool mcq_set_intr; + int mcq_nr_intr; + struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR]; }; /*