From patchwork Wed Feb 22 21:47:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13149613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C1A3C61DA4 for ; Wed, 22 Feb 2023 21:47:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA50410E2E6; Wed, 22 Feb 2023 21:47:18 +0000 (UTC) Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1196010E1EA for ; Wed, 22 Feb 2023 21:47:15 +0000 (UTC) Received: by mail-lf1-x129.google.com with SMTP id f18so11896992lfa.3 for ; Wed, 22 Feb 2023 13:47:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=in63kkOlF7AtxceONSVC3/gRevpfU5tcwdwBpL/2KyM=; b=KeM5Jd9PP6sKET3tC+jVjGKIxkt9KdvLN5KPtG7FquRbFFmzwM797jZOUYXTAlxQ1E AbwP03ooktQuTemzqxedPeJvEoenpub7MMLvo8mWImW2Nb0oezowfCwiI8xHQN28v5p3 6Q1OjIYirPMsTtgR5v2AmQoSomFpxBvqJnEM5u7IgI5G7ee+bG1xfJeTIsh9WybKrIM4 dlBaVoIPgvRLnPA6VnmxbF4i5i6vIwY4FwG7VQ04NsRUmxTpSc12ELP5415qzFoCy2N4 wTHF4VqT5Wm2ScAjY+VY0RTtmjw1NmIOF7W06aWhUd8EeO+/a09hnYfyFLC0U6HMYbu6 Y0Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=in63kkOlF7AtxceONSVC3/gRevpfU5tcwdwBpL/2KyM=; b=gQXkDKmmM9e7BgwHSGE9G6Zg0h6jVC/WoB/W8i2fNgRStfw4cvT2C9nKk9Zwt3O3DY VvP+Vu33b7eSiNlMYP6PHLzk74ioAZtbOMH0ecQxyHDK1hEY0pCr7jwYtz5wtXqIwoc8 1Ro9Nb9sFoR+bhDZNZD9fOxM+0ilw72Gl1aVWMub/PUbzLg+XfJ5b0fYuInEmOyz1PXm sRASF/r8fQ3MjHTrOBkBpj864v1iKyB9H/7zcG0NJmFalT2hA6NlDyZmzevqY94gu1Mx Msom6LsIkH4rS/t3jiJEuAseS7Ej1cD7B4Y3dz8hr1ExupH2RgFXQ9CIMRInZ63HQx8f +Akw== X-Gm-Message-State: AO0yUKUVtwokPz9Ky8xNtq8Icdo6Dtap/Lmj51FhH5DDkG4qXT08+Mnu WDmf0NiZnscL7h8/S0btJEOG7A== X-Google-Smtp-Source: AK7set/zwE4n33DuF1ijWw0Mn7XP5Waf6LKQEsQ6hwBwaQC+FVOvhsxGfJoTJp79xa9ArFb7ogqaFQ== X-Received: by 2002:ac2:4e05:0:b0:4dd:9f03:1f7e with SMTP id e5-20020ac24e05000000b004dd9f031f7emr1083698lfr.22.1677102433234; Wed, 22 Feb 2023 13:47:13 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:12 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:10 +0100 Subject: [PATCH 1/5] drm/msm/adreno: Use OPP for every GPU generation MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-1-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=6142; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XjCTxbeQ2g0wp3MiyX1zJyPLmA7rilIPN/CTVTjyz6M=; b=NWCfHrmYdFscaF+ZYcQO7FL3I6ZLWXdqVlElXTGvme3D9qz6OouxYc83qnwpMTuc1El3Yz+FLhWB 7FrMDyr3ALLVmn23zBM3AarmXDFJ4QvR3NuDoO98ZEbX4/9vjaRp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some older GPUs (namely a2xx with no opp tables at all and a320 with downstream-remnants gpu pwrlevels) used not to have OPP tables. They both however had just one frequency defined, making it extremely easy to construct such an OPP table from within the driver if need be. Do so and switch all clk_set_rate calls on core_clk to their OPP counterparts. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 94 +++++++++++++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 3 files changed, 45 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..9b940c0f063f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -922,73 +922,50 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) ring->id); } -/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ -static int adreno_get_legacy_pwrlevels(struct device *dev) -{ - struct device_node *child, *node; - int ret; - - node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); - if (!node) { - DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); - return -ENXIO; - } - - for_each_child_of_node(node, child) { - unsigned int val; - - ret = of_property_read_u32(child, "qcom,gpu-freq", &val); - if (ret) - continue; - - /* - * Skip the intentionally bogus clock value found at the bottom - * of most legacy frequency tables - */ - if (val != 27000000) - dev_pm_opp_add(dev, val, 0); - } - - of_node_put(node); - - return 0; -} - -static void adreno_get_pwrlevels(struct device *dev, +static int adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); unsigned long freq = ULONG_MAX; struct dev_pm_opp *opp; int ret; gpu->fast_rate = 0; - /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) - ret = adreno_get_legacy_pwrlevels(dev); - else { - ret = devm_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); - } - - if (!ret) { + /* devm_pm_opp_of_add_table may error out but will still create an OPP table */ + ret = devm_pm_opp_of_add_table(dev); + if (ret == -ENODEV) { + /* Special cases for ancient hw with ancient DT bindings */ + if (adreno_is_a2xx(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n"); + dev_pm_opp_add(dev, 200000000, 0); + gpu->fast_rate = 200000000; + } else if (adreno_is_a320(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n"); + dev_pm_opp_add(dev, 450000000, 0); + gpu->fast_rate = 450000000; + } else { + DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); + return -ENODEV; + } + } else if (ret) { + DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + return ret; + } else { /* Find the fastest defined rate */ opp = dev_pm_opp_find_freq_floor(dev, &freq); - if (!IS_ERR(opp)) { + + if (IS_ERR(opp)) + return PTR_ERR(opp); + else { gpu->fast_rate = freq; dev_pm_opp_put(opp); } } - if (!gpu->fast_rate) { - dev_warn(dev, - "Could not find a clock rate. Using a reasonable default\n"); - /* Pick a suitably safe clock speed for any target */ - gpu->fast_rate = 200000000; - } - DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + + return 0; } int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, @@ -1046,6 +1023,17 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; + int ret; + + /* This can only be done here, or devm_pm_opp_set_supported_hw will WARN_ON() */ + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1070,7 +1058,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(dev, gpu); + ret = adreno_get_pwrlevels(dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 380249500325..cdcb00df3f25 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -59,7 +59,7 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { if (gpu->core_clk && gpu->fast_rate) - clk_set_rate(gpu->core_clk, gpu->fast_rate); + dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); /* Set the RBBM timer rate to 19.2Mhz */ if (gpu->rbbmtimer_clk) @@ -78,7 +78,7 @@ static int disable_clk(struct msm_gpu *gpu) * will be rounded down to zero anyway so it all works out. */ if (gpu->core_clk) - clk_set_rate(gpu->core_clk, 27000000); + dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); if (gpu->rbbmtimer_clk) clk_set_rate(gpu->rbbmtimer_clk, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } dev_pm_opp_put(opp); From patchwork Wed Feb 22 21:47:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13149615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7F26C61DA4 for ; Wed, 22 Feb 2023 21:47:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6630110E44B; Wed, 22 Feb 2023 21:47:25 +0000 (UTC) Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3424110E1ED for ; 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:14 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:11 +0100 Subject: [PATCH 2/5] drm/msm/a2xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-2-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=2245; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=aOv4GpOcxYV0TegYhJBmwWoY68FI0H+2TrCshMKIIzs=; b=0OCPjYibSX+1IERZyu2BRoD05ys93RHFHJC69kwCa2fK2MoMZ7eN3CZd5G2p2wqPjAYeWIgEKIMK Tb6k+0SdB2SeaUXBlUrMeHAOl8klFw8++PiOSp/d9sF0R3zB5xlD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement gpu_busy based on the downstream msm-3.4 code [1]. This allows us to use devfreq on this old old old hardware! [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..6258c98e5a88 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -481,6 +481,33 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) return aspace; } +/* While the precise size of this field is unknown, it holds at least these three values.. */ +#define PERF_MODE_CNT GENMASK(2, 0) + #define PERF_STATE_RESET 0x0 + #define PERF_STATE_ENABLE 0x1 + #define PERF_STATE_FREEZE 0x2 +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + /* Freeze the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_FREEZE)); + + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); + + /* Reset the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_RESET)); + + /* Re-enable the performance monitors */ + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_ENABLE)); + + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -502,6 +529,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a2xx_gpu_busy, .gpu_state_get = a2xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = a2xx_create_address_space, From patchwork Wed Feb 22 21:47:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13149617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06E6BC636D6 for ; Wed, 22 Feb 2023 21:47:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23FC110E1EC; Wed, 22 Feb 2023 21:47:26 +0000 (UTC) Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by gabe.freedesktop.org (Postfix) with ESMTPS id A434810E1ED for ; Wed, 22 Feb 2023 21:47:16 +0000 (UTC) Received: by mail-lf1-x12d.google.com with SMTP id r27so9771632lfe.10 for ; Wed, 22 Feb 2023 13:47:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=h4TOwLOMt599To1JExzRPWtUssAyU9NR4zE3oZiUZ+A=; b=vIL6E4WB430uGyuj0lUufFhuF3CQGdR7a0e2PL3GMslNGEyrtQDEjXZMeY3345jFvp HWO1elZEKOm+pdo7JkxplbSgn5GGT34/qsUrVg5t3ihU77eXSDx2zTE4mgNMLojm4Vhx MdFudMtuetf1KVuDIDp2jxF4OkeULi7JyBNPMTzKYXq5LG/SSSgT5fbUvFF05j26AqtB vyJ5II7jzDWQna98MFh0FBBYs5NK6pS0E66bRO+Rwax/We5NU19WGLzypCiJm5ckFhWj h5nAwqCUTPyF4bDoylbIKOJYICX2AvqMnOwvsjcFpGkZjXqjxcyQL1aUDCPiMnXWzTX7 vQTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h4TOwLOMt599To1JExzRPWtUssAyU9NR4zE3oZiUZ+A=; b=Dk75JPAiMLE/9HDF+L81cw6VgtSR8+/ObrsEZhopO85GfOlhEg6ngfx2VmlGiyNoyL AhZVQGwenuTGPfM7xe7WhNBZuADjwvHHcViHxT42YBEMIav+FZcpixzaTJHyHRGR151o JvSZzav0f9M4E4frBUaTicIUsgZBMeN9vAn62EIZ6IozW5R7yNioapOgC9HkIRk1/KIX JESK9YWM2EwCHvoV7TjdRHRxXNUuG6yNMjmG8XaJDmEV7SIt6xjJQ9zi6MMHMmmvpvKl hzIobq6gfkJK3gpnS0a1neVRT3lj6QeoAWaHcQeSfgOXYl0ybgmOqGaXZx5wwe/p8qlT pfKQ== X-Gm-Message-State: AO0yUKW3HKmzJNt+5zg0fEqLnpCBtrlIP0pT8sQ0VMpf9gomq2MO3ia6 MEq7ArRZiwGfnKVMWmtRkiPNMQ== X-Google-Smtp-Source: AK7set+eW4mPqMzVEo+D/f0ChPtdJWyXdI0ZByYaPjTH4iVSby/zH5gzClBzhxeJzbHzlpRzj0AzIQ== X-Received: by 2002:ac2:521b:0:b0:4da:8838:31d9 with SMTP id a27-20020ac2521b000000b004da883831d9mr2808196lfl.8.1677102436200; Wed, 22 Feb 2023 13:47:16 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:15 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:12 +0100 Subject: [PATCH 3/5] drm/msm/a3xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-3-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=1323; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=i47Ky4BsxixFNiVTtrlkGNfUWp9lquZtebebI9yr3wY=; b=v8h6Dm7DVQ7sOt5Zbr5iRrvE0ULoDp8T5pjmqb2KYeBnxk5vKNo9UlQ2/Sso9Qhla9hLMw4Up0kT 4+nWOquwCwmoF65CjP0+7f/xpuDb4iBQzCNUnkIRlGCnRE4TyxfE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for gpu_busy on a3xx, which is required for devfreq support. Signed-off-by: Konrad Dybcio Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) return state; } +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a3xx_gpu_busy, .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Wed Feb 22 21:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13149614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6071C61DA4 for ; Wed, 22 Feb 2023 21:47:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B47F910E403; Wed, 22 Feb 2023 21:47:23 +0000 (UTC) Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF6B610E1ED for ; Wed, 22 Feb 2023 21:47:17 +0000 (UTC) Received: by mail-lf1-x12c.google.com with SMTP id s22so11784585lfi.9 for ; Wed, 22 Feb 2023 13:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SBObAXrrIUPtcxXkSYb1/MPep4XlGTpRKBjzQvdnZZw=; b=DYSfqZcq1BWpH+P2IBd79HjNKdKOG3b8AjS3DIzytdnEhbqpWN/TgFGuXhJ9HI12Q3 gSc2dvaycy+N3a8rxLUr/kQpz58VcT8cFeD/FRCfbo0gsX7gLrs/YBKoX8xQoP7Mlz4u 37JNW1PJvoQ3RHem/XqNNt/Aty2SzoY5HsD9GY3oIXWgGIiJd6n+dRV+AmxOVsCWe7OX pwJAmELMnjZLaSsdC4s8lT98kyXkPA5J8S0erUdGXVJXyLVO25+VIaCEOOqg8cD5XuV0 1In1RxBkjZi1Fx5cIh1DqgkQ4E0WF6yPIcFufuu3YgMeoAfB5j8nywnzViKwwkXISnlv BeoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SBObAXrrIUPtcxXkSYb1/MPep4XlGTpRKBjzQvdnZZw=; b=cuftYp/3d1IDQY87+a0ghA1uzXk0P8thM6aRJyFkVsrmn6n6v9rXr6FtS47L/XT02c r4kQ1gxDYVB8XfKzOT0WNMK3Vw+WLcbFPe2rU5+Avcz0dNKW6w1UKy4nZbs3OIPgokbc y4ZOVZNA/si2mNhpLueASkW+6zFBAEX4FoHsirCbkC/CCkE0jcQ+pZToG++338xsxeMN qG8R2B7t0p+S0ogVgT5FJKXuhHhAA87p9mcVUE5w8JBVPX2CDUxGD004ahbxOkGxzPs8 rf1KX1eOj9XGIbWVrpNmnsJRMq6SngAOJSilrOQTIvmBaiIHUc/5Ovjhsm6FkuBKYFMK 2Z9A== X-Gm-Message-State: AO0yUKV2B23WWSvVsN3uymr90GK/15yUWrdi0Zz/NPCbWIa3p6Zpu9sA J2jBmQ+b4jG0IBR8DjqxmVzW+Q== X-Google-Smtp-Source: AK7set8TVuK6O3j1A8cKQm/rm5TJ/U1qSbdnto6SXbID7beCkWyu0PMvaFkdf8HTx2O7tdm/3pc17A== X-Received: by 2002:ac2:568d:0:b0:4db:1b30:e634 with SMTP id 13-20020ac2568d000000b004db1b30e634mr2851991lfr.65.1677102437491; Wed, 22 Feb 2023 13:47:17 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:17 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:13 +0100 Subject: [PATCH 4/5] drm/msm/a4xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-4-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=1318; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=MauCU/9YqXIm/dt7dtytFcQBPIj8IAOvGMxFT4S8Dyc=; b=QP/b0QG4Xziuy8NNeXVPRPJH7YGpUoSLjur6u0R/Y4RiCLZ1iUjbF/PJzlgL6+eqAwD9/vnnCxZG rE5QRKXECnql9QRhMyM73Qpy3yERT9D7erzVd9cu5uOP/HjMtgUw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for gpu_busy on a4xx, which is required for devfreq support. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 3e09d3a7a0ac..715436cb3996 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -611,6 +611,16 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) return 0; } +static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); @@ -632,6 +642,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a4xx_gpu_busy, .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Wed Feb 22 21:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13149616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88087C64EC7 for ; Wed, 22 Feb 2023 21:47:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A95A10E449; Wed, 22 Feb 2023 21:47:25 +0000 (UTC) Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6BFB210E41E for ; Wed, 22 Feb 2023 21:47:20 +0000 (UTC) Received: by mail-lf1-x136.google.com with SMTP id k14so10897948lfj.7 for ; Wed, 22 Feb 2023 13:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=39aG+iURI09iswW6gk3gC6TBwToV0heQthXAeMfwVro=; b=HzIPoQRPbG/dXz63sWAdJwl2JHB79lNtcfUTS1bk6pyYqiR9a92sQZ8oexO++tzYOV Tbk9YCRPD6MoPA4l/RV2iTQYtFRDA9eUjNuD9vyQpT59cm9obwO5UfFORpcTVfVTZVuW KjJv8fVNIDJArcRFG2m28RQuy4EZhxT13CiysjTbub+h0aDOd1qRTJYWm17Q/Z0cGZkT RCBMrM3+QjBRGlUQS+89zQlYptl1+ppeCt9IpLzXzOIo9y4UGBhyeaH5RxrgBqbokBHK DUk+Jpr27OC+WEvWbqlIyHOwuz3UvBY3oLUWm3+gFD6W78IP8A3m0KbGa/NSxW1wFv5x CdhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=39aG+iURI09iswW6gk3gC6TBwToV0heQthXAeMfwVro=; b=zgHvLhXbmdIo6I9NUFY9ISFHM2l39UItMwtK5PbmMBpORi56IcTSInVQ351Zhho34T qMnjN3IfRXzUTBDnDJRjHlNtQpVSUWMJ1bugdikXigccMXyY4vuylrdTju0+KIJNzqdr lMwdocbDxzoTRDBsew9hkPb1Ul9zJocBjQzAYuDcgnYhaxZK8WhJivXlBbSy+zz4opT8 XHE/G+9Wn5bph9EE93YvD/LuKq1yY2T2YcUJsp3U2Sd1CRIHb8t1j9gRq/XXzT58kcCN eWZmabTcfGNjdY22nGvvdKevBEi5BKQFjKcNFg3YH5f6MKTpki+a+3OodDl6VxybdVks AMgQ== X-Gm-Message-State: AO0yUKXlZYi0eicnuKNS9PlsPDbwMTGbFXQatAXRkQxZ+Tmi5EnREFZC Wl4tRO3s4uzS1lC9gme9WQxAQLTpsCb++qsK X-Google-Smtp-Source: AK7set+nn2KRiV4gLdb9BVSubaqkj4Yacm0rOrroDID/OutRQP5o2HwsQd0w7jcVi9x79C8aqjh0fg== X-Received: by 2002:ac2:485a:0:b0:4dc:4c56:19ac with SMTP id 26-20020ac2485a000000b004dc4c5619acmr3609922lfy.58.1677102438644; Wed, 22 Feb 2023 13:47:18 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:18 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:14 +0100 Subject: [PATCH 5/5] drm/msm/a5xx: Enable optional icc voting from OPP tables MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-5-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=807; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TMGW8gjkiQwEJ0fii5rrgM+Nl4d+tDtzpTg1fjmA9zo=; b=o1Nbuq1XpVhn6xnmPyYkuaAq0xiZ0aski/AfFD81WLJwQsE/JusmS5elxNiSQcEnM76oc3Ers35U eiDijrx9C0uZlUc59nitgz2e4VYiOpcCz4G/cJuX7NgFzniXRWFC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index d09221f97f71..a33af0cc27b6 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1775,5 +1775,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) /* Set up the preemption specific bits and pieces for each ringbuffer */ a5xx_preempt_init(gpu); + ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); + if (ret) + return ERR_PTR(ret); + return gpu; }