From patchwork Fri Feb 24 19:46:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C5F1C64ED8 for ; Fri, 24 Feb 2023 19:47:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229489AbjBXTrI (ORCPT ); Fri, 24 Feb 2023 14:47:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229452AbjBXTrH (ORCPT ); Fri, 24 Feb 2023 14:47:07 -0500 Received: from bee.birch.relay.mailchannels.net (bee.birch.relay.mailchannels.net [23.83.209.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E25A56C198 for ; Fri, 24 Feb 2023 11:47:05 -0800 (PST) X-Sender-Id: dreamhost|x-authsender|dave@stgolabs.net Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id C4DC5413C8; Fri, 24 Feb 2023 19:47:04 +0000 (UTC) Received: from pdx1-sub0-mail-a250.dreamhost.com (unknown [127.0.0.6]) (Authenticated sender: dreamhost) by relay.mailchannels.net (Postfix) with ESMTPA id 340DC41E34; Fri, 24 Feb 2023 19:47:04 +0000 (UTC) ARC-Seal: i=1; s=arc-2022; d=mailchannels.net; t=1677268024; a=rsa-sha256; cv=none; b=ogOSPOatlOxMBYtZDHKh18DJsGO9byyKDs1OzJPBBh0DAe9+33Nb6C2+pG0qSJCKAbwkQJ 3sRtuEr0XRhsNHE0NCrzXwJ8+/wyE2EFVYeF15w5vEYA0fMgTfgh4E5Bn8iWTEqamLyDh6 4Axp5JdW4No0MWYI/eJNLke0CJnoR16jq31iU8AsUkl+nV7235zUiruCXxuF0CDRkzxcs6 +0g3sZGQoVysKLhxNqkcUKMcnsYTH7q2iMXYHvm3Oa9MMpAoLV748o7KvPAypE4evb/xSs TNhrY+VMtWV6Geuv/MN/Gk+XwldKm2EEFcHmjavPnsC8OrnFwFrGCIuKqH1kNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=mailchannels.net; s=arc-2022; t=1677268024; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=V2I++juXSCA0Nxo7T8cxpd5bOdVDAFjngnMd/Z/exmk=; b=DciKW+rNfQRDWQqDP7e7ilH9S9+ybeFgPdg0IsEN5ZZsvtJDPCFrCdCE6WjE47qhTg9oGX tRKnUeEGKFpvq+7DwouoJrMw4Ce7prG6qNjFfLwrysHSiAexl5wjokBseGT5AZFvgYN6x+ hWLJDQoIw1bDRsoozH/SZJa4UOfP8qfrXcl/8Ylxg/rLX/j60ZLXLbhg3B+W2ZjIgttyNq lc/d8rgp9KrvUE9Gk6DtHEw8ZxNE+bEvSi1jgZSZU3eJKdJ7QI5JsMhmkesDwBOu8MWKVz VQN9zptZSCggbE/epxHMOIQcmbsWNvaCIXEie/Vb7W5EoMZFjbuLVQMZctKg0g== ARC-Authentication-Results: i=1; rspamd-9788b98bc-pxv92; auth=pass smtp.auth=dreamhost smtp.mailfrom=dave@stgolabs.net X-Sender-Id: dreamhost|x-authsender|dave@stgolabs.net X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|dave@stgolabs.net X-MailChannels-Auth-Id: dreamhost X-Chief-Interest: 0d0fa5cc58b96e0f_1677268024626_306224221 X-MC-Loop-Signature: 1677268024626:2631171739 X-MC-Ingress-Time: 1677268024626 Received: from pdx1-sub0-mail-a250.dreamhost.com (pop.dreamhost.com [64.90.62.162]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384) by 100.116.179.67 (trex/6.7.1); Fri, 24 Feb 2023 19:47:04 +0000 Received: from offworld.. (ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQF10jcz2Q; Fri, 24 Feb 2023 11:47:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268022; bh=V2I++juXSCA0Nxo7T8cxpd5bOdVDAFjngnMd/Z/exmk=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=KbLxIkPKnPg7ZhGnbWP3nJglTNRZLVOaX89oJvmPs3hbxcferBcCY3C/JftYosW0j w8cz8oeRJX6Dh66moHKN2qRQQ74mSOzfO93r6Bb6KCc+SGx6zPMJdYCbD1KNan8N9D mZw2EgjjWWinAwhCOlmzWojDe+cB37nvNKFD82qbGCl3FLk7mffpqpVCIIGspK/9du hByibqHWw5CCQyeu5k5xRbOf4p/Kx9v7dOJ8kNmhpifgkEom9cbd2onEeai/GmywPy 8yKYhvAIO0lIs3jGXFHk6FjEKvznUFerIO10aXeevhAHUtNEl8x8YH9m4rhE88O8EB Qxt85Bd0K91XA== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 1/7] cxl/mbox: Add background cmd handling machinery Date: Fri, 24 Feb 2023 11:46:46 -0800 Message-Id: <20230224194652.1990604-2-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org This adds support for handling background operations, as defined in the CXL 3.0 spec. Commands that can take too long (over ~2 seconds) can run in the background asynchronously (to the hardware). Currently these are limited to Maintenance, transfer/activate Firmware, Scan Media, Sanitize (aka overwrite), and VPPB bind/unbind. The driver will deal with such commands synchronously, blocking all other incoming commands for a specified period of time, allowing time-slicing the command such that the caller can send incremental requests to avoid monopolizing the driver/device. This approach makes the code simpler, where any out of sync (timeout) between the driver and hardware is just disregarded as an invalid state until the next successful submission. On devices where mbox interrupts are supported, this will still use a poller that will wakeup in the specified wait intervals. The irq handler will simply awake a blocked cmd, which is also safe vs a task that is either waking (timing out) or already awoken. Signed-off-by: Davidlohr Bueso Reviewed-by: Dave Jiang --- drivers/cxl/cxl.h | 7 +++ drivers/cxl/cxlmem.h | 6 +++ drivers/cxl/pci.c | 100 +++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 109 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index d853a0238ad7..b834e55375e3 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -176,14 +176,21 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) /* CXL 2.0 8.2.8.4 Mailbox Registers */ #define CXLDEV_MBOX_CAPS_OFFSET 0x00 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) +#define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) +#define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) #define CXLDEV_MBOX_CTRL_OFFSET 0x04 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) +#define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) #define CXLDEV_MBOX_CMD_OFFSET 0x08 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) #define CXLDEV_MBOX_STATUS_OFFSET 0x10 +#define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 +#define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) +#define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) +#define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 /* diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index ccbafc05a636..934076254d52 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -108,6 +108,9 @@ static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, * variable sized output commands, it tells the exact number of bytes * written. * @min_out: (input) internal command output payload size validation + * @poll_count: (input) Number of timeouts to attempt. + * @poll_interval: (input) Number of ms between mailbox background command + * polling intervals timeouts. * @return_code: (output) Error code returned from hardware. * * This is the primary mechanism used to send commands to the hardware. @@ -123,6 +126,8 @@ struct cxl_mbox_cmd { size_t size_in; size_t size_out; size_t min_out; + int poll_count; + u64 poll_interval; u16 return_code; }; @@ -322,6 +327,7 @@ enum cxl_opcode { CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, CXL_MBOX_OP_SCAN_MEDIA = 0x4304, CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, + CXL_MBOX_OP_SANITIZE = 0x4400, CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 60b23624d167..26b6105e2797 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -52,6 +52,8 @@ static unsigned short mbox_ready_timeout = 60; module_param(mbox_ready_timeout, ushort, 0644); MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); +static DECLARE_WAIT_QUEUE_HEAD(mbox_wait); + static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) { const unsigned long start = jiffies; @@ -85,6 +87,25 @@ static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ status & CXLMDEV_FW_HALT ? " firmware-halt" : "") +static irqreturn_t cxl_mbox_irq(int irq, void *id) +{ + /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ + wake_up(&mbox_wait); + return IRQ_HANDLED; +} + +static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) +{ + u64 bgcmd_status_reg; + u32 pct; + + bgcmd_status_reg = readq(cxlds->regs.mbox + + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); + pct = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, bgcmd_status_reg); + + return pct == 100; +} + /** * __cxl_pci_mbox_send_cmd() - Execute a mailbox command * @cxlds: The device state to communicate with. @@ -178,6 +199,56 @@ static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds, mbox_cmd->return_code = FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); + /* + * Handle the background command in a synchronous manner. + * + * All other mailbox commands will serialize/queue on the mbox_mutex, + * which we currently hold. Furthermore this also guarantees that + * cxl_mbox_background_complete() checks are safe amongst each other, + * in that no new bg operation can occur in between. + * + * With the exception of special cases that merit monopolizing the + * driver/device, bg operations are timesliced in accordance with + * the nature of the command being sent. + * + * In the event of timeout, the mailbox state is indeterminate + * until the next successful command submission and the driver + * can get back in sync with the hardware state. + */ + if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { + u64 bg_status_reg; + const bool timeslice = mbox_cmd->opcode != CXL_MBOX_OP_SANITIZE; + + dev_dbg(dev, "Mailbox background operation started\n"); + + while (1) { + if (wait_event_interruptible_timeout( + mbox_wait, cxl_mbox_background_complete(cxlds), + msecs_to_jiffies(mbox_cmd->poll_interval)) > 0) + break; + + if (timeslice && !--mbox_cmd->poll_count) + break; + } + + if (!cxl_mbox_background_complete(cxlds)) { + u64 md_status = + readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); + + cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, + "background timeout"); + return -ETIMEDOUT; + } + + bg_status_reg = readq(cxlds->regs.mbox + + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); + mbox_cmd->return_code = + FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, + bg_status_reg); + + dev_dbg(dev, "Mailbox background operation completed\n"); + } + if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { dev_dbg(dev, "Mailbox operation had an error: %s\n", cxl_mbox_cmd_rc2str(mbox_cmd)); @@ -222,8 +293,11 @@ static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *c static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) { const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); + struct device *dev = cxlds->dev; + struct pci_dev *pdev = to_pci_dev(dev); unsigned long timeout; u64 md_status; + int rc, irq; timeout = jiffies + mbox_ready_timeout * HZ; do { @@ -272,6 +346,24 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) dev_dbg(cxlds->dev, "Mailbox payload sized %zu", cxlds->payload_size); + if (!(cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ)) { + dev_dbg(dev, "Only Mailbox polling is supported"); + return 0; + } + + irq = pci_irq_vector(pdev, + FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap)); + if (irq < 0) + return irq; + + rc = devm_request_irq(dev, irq, cxl_mbox_irq, + IRQF_SHARED, "mailbox", cxlds); + if (rc) + return rc; + + writel(CXLDEV_MBOX_CTRL_BG_CMD_IRQ, + cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); + return 0; } @@ -757,6 +849,10 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + rc = cxl_alloc_irq_vectors(pdev); + if (rc) + return rc; + rc = cxl_pci_setup_mailbox(cxlds); if (rc) return rc; @@ -777,10 +873,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; - rc = cxl_alloc_irq_vectors(pdev); - if (rc) - return rc; - cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); From patchwork Fri Feb 24 19:46:47 2023 Content-Type: text/plain; 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(ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQJ0dc5zMP; Fri, 24 Feb 2023 11:47:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268024; bh=DjzZAOO4awNY+j0vnzloQLKua0xzw1hNI/cCA000ioA=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=hHqgOFDYCbIivObTDIBKI8cuw+K328KA4QAHdirW2iWIP538AEa8xEqZKopMYeYAW cXc0MgkiNbfH6rGAQfRfTITqA9V8yThNWOX9y0iayjdz0gSf7FSh4nvkdWQl+CCpha 3xhlRQ2lqz6nxFvmMqXdj4W34Q3l9imeTFbCHbWiFVXsj71cqTTHXII9ajudZDMIo2 hDWcq4yvBTwPSrl0y3hxFJ+7kru0AeZpjznsEZcXj0S9CP653DgTurlqwOaBSoPoJc SIP9aAPTLHFdhMy2hhpheWaBMLwlIDGKuY6AE/UZlk9SRSvRI4i+ht+nj2oRoZK0Sp G90AlX0X8Ywxw== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 2/7] cxl/security: Add security state sysfs ABI Date: Fri, 24 Feb 2023 11:46:47 -0800 Message-Id: <20230224194652.1990604-3-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org This adds the sysfs memdev's security/ directory with a single 'state' file, which is always visible. In the case of unsupported security features, this will show disabled. Signed-off-by: Davidlohr Bueso Reviewed-by: Dave Jiang --- Documentation/ABI/testing/sysfs-bus-cxl | 8 ++++ drivers/cxl/core/memdev.c | 49 +++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 3acf2f17a73f..e9c432a5a841 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -57,6 +57,14 @@ Description: host PCI device for this memory device, emit the CPU node affinity for this device. +What: /sys/bus/cxl/devices/memX/security/state +Date: February, 2023 +KernelVersion: v6.4 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The security state for that device. The following states + are available: frozen, locked, unlocked and disabled (which + is also the case for any unsupported security features). What: /sys/bus/cxl/devices/*/devtype Date: June, 2021 diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 0af8856936dc..47cc625bb1b0 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. */ +#include #include #include #include @@ -89,6 +90,43 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, static struct device_attribute dev_attr_pmem_size = __ATTR(size, 0444, pmem_size_show, NULL); +static ssize_t security_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 sec_out; + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_get_security_output { + __le32 flags; + } out; + struct cxl_mbox_cmd mbox_cmd = { + .opcode = CXL_MBOX_OP_GET_SECURITY_STATE, + .payload_out = &out, + .size_out = sizeof(out), + }; + + if (!cpu_cache_has_invalidate_memregion()) + goto disabled; + + if (cxl_internal_send_cmd(cxlds, &mbox_cmd) < 0) + goto disabled; + + sec_out = le32_to_cpu(out.flags); + if (!(sec_out & CXL_PMEM_SEC_STATE_USER_PASS_SET)) + goto disabled; + if (sec_out & CXL_PMEM_SEC_STATE_FROZEN) + return sysfs_emit(buf, "frozen\n"); + if (sec_out & CXL_PMEM_SEC_STATE_LOCKED) + return sysfs_emit(buf, "locked\n"); + else + return sysfs_emit(buf, "unlocked\n"); +disabled: + return sysfs_emit(buf, "disabled\n"); +} + +static struct device_attribute dev_attr_security_state = + __ATTR(state, 0444, security_state_show, NULL); + static ssize_t serial_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -148,10 +186,21 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = { .attrs = cxl_memdev_pmem_attributes, }; +static struct attribute *cxl_memdev_security_attributes[] = { + &dev_attr_security_state.attr, + NULL, +}; + +static struct attribute_group cxl_memdev_security_attribute_group = { + .name = "security", + .attrs = cxl_memdev_security_attributes, +}; + static const struct attribute_group *cxl_memdev_attribute_groups[] = { &cxl_memdev_attribute_group, &cxl_memdev_ram_attribute_group, &cxl_memdev_pmem_attribute_group, + &cxl_memdev_security_attribute_group, NULL, }; From patchwork Fri Feb 24 19:46:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9561C6FA8E for ; Fri, 24 Feb 2023 19:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229495AbjBXTrK (ORCPT ); Fri, 24 Feb 2023 14:47:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbjBXTrJ (ORCPT ); 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(ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQK2SvNz2Q; Fri, 24 Feb 2023 11:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268026; bh=NZUKbFkQhmzwX/XIY66T6M+R2xD4t4IwbUDe6lPcZLc=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=pGXZIXJ073EoaYBAknYQTP4EeoqbIFeEduSAc/hetNHFRpo9guUYwUXtziHmRN/sK /2PxHEWELdPpNjk5/F8jpmpfhSqjpMcF6GxI0bFXmpFNQFdBOxAeKbSaFzyRgOwfSP hjtm5d//12/a8p7c2GW/s6BJj9IT+s6PkGGsr97Y3KYUIW1PC0woWOqev9evaqQIYL WqA2kZpX4QdMRX8mlaCVYVH5NVQvzxMfvvxkiO6XxIWkgsC95QuXdNEPd24Y+21oYz hSnzP4wCbX8vrn8bNgwq1KKV/0L7a/PI3Wdou3pvE0ZhilJ8sxsyFL7up2wxYXLtvY FILCXZn9wJcDg== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 3/7] cxl/region: Add cxl_memdev_active_region() Date: Fri, 24 Feb 2023 11:46:48 -0800 Message-Id: <20230224194652.1990604-4-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Track all regions associated to a memdev in order to tell if the device might be in active use. Signed-off-by: Davidlohr Bueso --- drivers/cxl/core/memdev.c | 1 + drivers/cxl/core/region.c | 33 +++++++++++++++++++++++++++++++-- drivers/cxl/cxl.h | 6 ++++++ drivers/cxl/cxlmem.h | 4 ++++ 4 files changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 47cc625bb1b0..68c0ab06b999 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -306,6 +306,7 @@ static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds, dev->type = &cxl_memdev_type; device_set_pm_not_required(dev); INIT_WORK(&cxlmd->detach_work, detach_memdev); + INIT_LIST_HEAD(&cxlmd->region_list); cdev = &cxlmd->cdev; cdev_init(cdev, fops); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index f29028148806..cea9de6457b9 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1730,7 +1730,10 @@ void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled) { down_write(&cxl_region_rwsem); cxled->mode = CXL_DECODER_DEAD; - cxl_region_detach(cxled); + if (!cxl_region_detach(cxled)) { + struct cxl_region *cxlr = cxled->cxld.region; + list_del(&cxlr->node); + } up_write(&cxl_region_rwsem); } @@ -1749,8 +1752,12 @@ static int attach_target(struct cxl_region *cxlr, down_read(&cxl_dpa_rwsem); rc = cxl_region_attach(cxlr, cxled, pos); - if (rc == 0) + if (rc == 0) { + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + set_bit(CXL_REGION_F_INCOHERENT, &cxlr->flags); + list_add_tail(&cxlr->node, &cxlmd->region_list); + } up_read(&cxl_dpa_rwsem); up_write(&cxl_region_rwsem); return rc; @@ -1778,6 +1785,8 @@ static int detach_target(struct cxl_region *cxlr, int pos) } rc = cxl_region_detach(p->targets[pos]); + if (rc == 0) + list_del(&cxlr->node); out: up_write(&cxl_region_rwsem); return rc; @@ -2654,6 +2663,26 @@ int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled) } EXPORT_SYMBOL_NS_GPL(cxl_add_to_region, CXL); +bool cxl_memdev_active_region(struct cxl_memdev *cxlmd) +{ + bool ret = false; + struct cxl_region *cxlr; + + down_read(&cxl_region_rwsem); + list_for_each_entry(cxlr, &cxlmd->region_list, node) { + struct cxl_region_params *p = &cxlr->params; + + if (p->state >= CXL_CONFIG_ACTIVE) { + ret = true; + break; + } + } + up_read(&cxl_region_rwsem); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(cxl_memdev_active_region, CXL); + static int cxl_region_invalidate_memregion(struct cxl_region *cxlr) { if (!test_bit(CXL_REGION_F_INCOHERENT, &cxlr->flags)) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b834e55375e3..e211241b079b 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -502,6 +502,7 @@ struct cxl_region { struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; + struct list_head node; }; struct cxl_nvdimm_bridge { @@ -773,6 +774,7 @@ struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled); struct cxl_dax_region *to_cxl_dax_region(struct device *dev); +bool cxl_memdev_active_region(struct cxl_memdev *cxlmd); #else static inline bool is_cxl_pmem_region(struct device *dev) { @@ -791,6 +793,10 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) { return NULL; } +static inline bool cxl_memdev_active_region(struct cxl_memdev *cxlmd) +{ + return false; +} #endif /* diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 934076254d52..4e31f3234519 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -5,6 +5,7 @@ #include #include #include +#include #include "cxl.h" /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ @@ -40,6 +41,8 @@ * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem * @id: id number of this memdev instance. * @depth: endpoint port depth + * @region_list: List of regions that have as target the endpoint + * decoder associated with this memdev */ struct cxl_memdev { struct device dev; @@ -50,6 +53,7 @@ struct cxl_memdev { struct cxl_nvdimm *cxl_nvd; int id; int depth; + struct list_head region_list; }; static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) From patchwork Fri Feb 24 19:46:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A813C7EE30 for ; Fri, 24 Feb 2023 19:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229532AbjBXTrK (ORCPT ); Fri, 24 Feb 2023 14:47:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbjBXTrK (ORCPT ); Fri, 24 Feb 2023 14:47:10 -0500 Received: from bird.elm.relay.mailchannels.net (bird.elm.relay.mailchannels.net [23.83.212.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A58256C1A2 for ; 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(ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQL2LYSz2d; Fri, 24 Feb 2023 11:47:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268027; bh=pQp/N3Eufw05PzXNXa9+lQfLf0rhBWb4ZP5pKq1qTQo=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=q0dcms7cDxLEkznkEBjIzCj/ateOoE4W1B45nMmx5VKyS4I8+Z2xQcqkyBOFijvQG 37h9eruP9bcFnVNsL2impD4mVM6PIsKD8/wUvr7aO+UrdVMZOdO/IAfRjdePzYTxm9 DqtwG6VWMV5HLEfW/rN8oTr3DN5Ta/WLV3oayzHSeSuPhP0fdWm3uOWr5M8ETqC4Kv 4UUXfA0KJQl85DsU6Pwj/iScJfzU0zQdwTVNOxHMdjg2CIE55JaOZ/vmOdk+WfK5rY UA/DZSQpwKm4Y577bIusAgjIWoOXEKCrSZ5va8EbW/8RSieMHBAFDP9HlIJ5+FooGk f+S7rkXLQDwgg== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 4/7] cxl/mem: Support Sanitation Date: Fri, 24 Feb 2023 11:46:49 -0800 Message-Id: <20230224194652.1990604-5-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Implement support for the non-pmem exclusive sanitize (aka overwrite), per CXL specs. This is the baseline for the sanitize-on-release functionality. To properly support this feature, create a 'security/sanitize' sysfs file that when read will list the current pmem security state and when written to, perform the requested operation. This operation can run in the background and the driver must wait for completion (no timeout), where the poller will awake every ~10 seconds (this could be further based on the size of the device). Signed-off-by: Davidlohr Bueso --- Documentation/ABI/testing/sysfs-bus-cxl | 14 ++++++ drivers/cxl/core/mbox.c | 61 +++++++++++++++++++++++++ drivers/cxl/core/memdev.c | 39 ++++++++++++++++ drivers/cxl/cxlmem.h | 2 + 4 files changed, 116 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index e9c432a5a841..b315d78b7e91 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -66,6 +66,20 @@ Description: are available: frozen, locked, unlocked and disabled (which is also the case for any unsupported security features). +What: /sys/bus/cxl/devices/memX/security/sanitize +Date: February, 2023 +KernelVersion: v6.4 +Contact: linux-cxl@vger.kernel.org +Description: + (WO) Write a boolean 'true' string value to this attribute to + sanitize the device to securely re-purpose or decommission it. + This is done by ensuring that all user data and meta-data, + whether it resides in persistent capacity, volatile capacity, + or the LSA, is made permanently unavailable by whatever means + is appropriate for the media type. This causes all CPU caches + to be flushed. If this sysfs entry is not present then the + architecture does not support security features. + What: /sys/bus/cxl/devices/*/devtype Date: June, 2021 KernelVersion: v5.14 diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index f2addb457172..885de3506735 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ #include +#include #include #include #include @@ -1021,6 +1022,66 @@ int cxl_dev_state_identify(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_dev_state_identify, CXL); +/** + * cxl_mem_sanitize() - Send sanitation (aka overwrite) command to the device. + * @cxlds: The device data for the operation + * + * Return: 0 if the command was executed successfully, regardless of + * whether or not the actual security operation is done in the background. + * Upon error, return the result of the mailbox command or -EINVAL if + * security requirements are not met. CPU caches are flushed before and + * after succesful completion of each command. + * + * See CXL 3.0 @8.2.9.8.5.1 Sanitize. + */ +int cxl_mem_sanitize(struct cxl_dev_state *cxlds) +{ + int rc; + u32 sec_out = 0; + struct cxl_get_security_output { + __le32 flags; + } out; + struct cxl_mbox_cmd sec_cmd = { + .opcode = CXL_MBOX_OP_GET_SECURITY_STATE, + .payload_out = &out, + .size_out = sizeof(out), + }; + struct cxl_mbox_cmd mbox_cmd = { + .opcode = CXL_MBOX_OP_SANITIZE, + .poll_interval = 10000UL, + }; + + if (!cpu_cache_has_invalidate_memregion()) + return -EINVAL; + + rc = cxl_internal_send_cmd(cxlds, &sec_cmd); + if (rc < 0) { + dev_err(cxlds->dev, "Failed to get security state : %d", rc); + return rc; + } + + /* + * Prior to using these commands, any security applied to + * the user data areas of the device shall be DISABLED (or + * UNLOCKED for secure erase case). + */ + sec_out = le32_to_cpu(out.flags); + if (sec_out & CXL_PMEM_SEC_STATE_USER_PASS_SET) + return -EINVAL; + + cpu_cache_invalidate_memregion(IORES_DESC_CXL); + + rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); + if (rc < 0) { + dev_err(cxlds->dev, "Failed to sanitize device : %d", rc); + return rc; + } + + cpu_cache_invalidate_memregion(IORES_DESC_CXL); + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_mem_sanitize, CXL); + static int add_dpa_res(struct device *dev, struct resource *parent, struct resource *res, resource_size_t start, resource_size_t size, const char *type) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 68c0ab06b999..a1bb095d081c 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -127,6 +127,34 @@ static ssize_t security_state_show(struct device *dev, static struct device_attribute dev_attr_security_state = __ATTR(state, 0444, security_state_show, NULL); +static ssize_t security_sanitize_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + ssize_t rc; + bool sanitize; + + rc = kstrtobool(buf, &sanitize); + if (rc) + return rc; + + if (sanitize) { + if (cxl_memdev_active_region(cxlmd)) + return -EBUSY; + + rc = cxl_mem_sanitize(cxlds); + } + + if (rc == 0) + rc = len; + return rc; +} + +static struct device_attribute dev_attr_security_sanitize = + __ATTR(sanitize, 0200, NULL, security_sanitize_store); + static ssize_t serial_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -188,11 +216,22 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = { static struct attribute *cxl_memdev_security_attributes[] = { &dev_attr_security_state.attr, + &dev_attr_security_sanitize.attr, NULL, }; +static umode_t cxl_security_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + if (!cpu_cache_has_invalidate_memregion() && + a == &dev_attr_security_sanitize.attr) + return 0; + return a->mode; +} + static struct attribute_group cxl_memdev_security_attribute_group = { .name = "security", + .is_visible = cxl_security_visible, .attrs = cxl_memdev_security_attributes, }; diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 4e31f3234519..0d2009b36933 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -631,6 +631,8 @@ static inline void cxl_mem_active_dec(void) } #endif +int cxl_mem_sanitize(struct cxl_dev_state *cxlds); + struct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; From patchwork Fri Feb 24 19:46:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED723C7EE31 for ; Fri, 24 Feb 2023 19:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229491AbjBXTrL (ORCPT ); Fri, 24 Feb 2023 14:47:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbjBXTrK (ORCPT ); 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(ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQM3FFSz2Q; Fri, 24 Feb 2023 11:47:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268028; bh=V5tX9bU4PXyDcIBGDeJkgwU79PnzSt35DBkXyyj3TIk=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=kRLJ/XO+IRyhFRfxOJC7dD0yp/YwVrsdH7GVz7QvPXn+Jebm1Q+L/Tnijp0dtVu7H VUFggEeKA1i1eR34AyqGjm492iLMEPDtNwHTtQ24mENbqYgpINdoKDtPPNarUmwiBR SPsm7+rZcAoyXjRKWbsUbdffFPa4l4Hecu/fBXCuZEdt9wE/7VUVN9IxKbzFsWRLjo cfSW02avLb9ALQakw8nJz8vbI+Ve0UKnJzaHdJ3yczeAfODRfipAH8aojEVYh+sqZM FF8Av0oMU9fv1NJARO5GFXDNAWyFmUs0Xw549N1EOndnBFtN0nGoVYfyAAuB8OSaKz zY1kkKuR8gWdQ== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 5/7] cxl/test: Add "Sanitize" opcode support Date: Fri, 24 Feb 2023 11:46:50 -0800 Message-Id: <20230224194652.1990604-6-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add support to emulate a CXL mem device support the "Sanitize" operation, without incurring in the background. Signed-off-by: Davidlohr Bueso Reviewed-by: Dave Jiang --- tools/testing/cxl/test/mem.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 9263b04d35f7..d4466cb27947 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -497,6 +497,28 @@ static int mock_partition_info(struct cxl_dev_state *cxlds, return 0; } +static int mock_sanitize(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) +{ + struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); + + if (cmd->size_in != 0) + return -EINVAL; + + if (cmd->size_out != 0) + return -EINVAL; + + if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { + cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; + return -ENXIO; + } + if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { + cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; + return -ENXIO; + } + + return 0; /* assume less than 2 secs, no bg */ +} + static int mock_get_security_state(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) { @@ -924,6 +946,9 @@ static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd * case CXL_MBOX_OP_GET_HEALTH_INFO: rc = mock_health_info(cxlds, cmd); break; + case CXL_MBOX_OP_SANITIZE: + rc = mock_sanitize(cxlds, cmd); + break; case CXL_MBOX_OP_GET_SECURITY_STATE: rc = mock_get_security_state(cxlds, cmd); break; From patchwork Fri Feb 24 19:46:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED595C6FA8E for ; Fri, 24 Feb 2023 19:54:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229580AbjBXTyw (ORCPT ); Fri, 24 Feb 2023 14:54:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229638AbjBXTyv (ORCPT ); Fri, 24 Feb 2023 14:54:51 -0500 Received: from bird.elm.relay.mailchannels.net (bird.elm.relay.mailchannels.net [23.83.212.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA12E628FC for ; Fri, 24 Feb 2023 11:54:49 -0800 (PST) X-Sender-Id: dreamhost|x-authsender|dave@stgolabs.net Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 29A403C1F46; Fri, 24 Feb 2023 19:47:10 +0000 (UTC) Received: from pdx1-sub0-mail-a250.dreamhost.com (unknown [127.0.0.6]) (Authenticated sender: dreamhost) by relay.mailchannels.net (Postfix) with ESMTPA id 901A93C1F5C; Fri, 24 Feb 2023 19:47:09 +0000 (UTC) ARC-Seal: i=1; s=arc-2022; d=mailchannels.net; t=1677268029; a=rsa-sha256; cv=none; b=JjULwDOF8mhC7wVOgllUnm9o4Cl+eQmWpvsZL7fPIO7EKhTZCBLOU8oNsP+quB02rLIhfq 0j6OlKS/UtGn7l3p7aSFWl8ti3kAyJLHZg26S++zEVfElWEX7n/lfgC79TZUfZKcxtagng PvnfgcuJWqonM6k9lgll9xSLdjfoeMW2/lpufz3RgruX8BNJo9lq2rallrQA4jh6iZDgyd EiPO5aqkzKrbk/YoCsJkUn2dr9iQXLSlnoraFvQRHz0LcirBS5KqjgxqEB0KgcqL+mVBlk 3AdZorkTIMbRJvCgXZpDwJh6W7N8LX+1Ys/gqxbf2pwtjHCGzfNhCOuwioJecQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=mailchannels.net; s=arc-2022; t=1677268029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=GiOeG5lrocXfUVyExHZRoYMiICaJ3EVxSwc8oBrFE+8=; b=uWoB1YNN+pKqg+oVu8ywgUvuiYsLGIRHYy2dTDiJKKRK+jclBCE62EofxPNPIoFKROht8X hDbx5CIQUhmGncV3NqDCdhynhH3fX0GluyAJDajrT6MAW9kd+gv52lX32xsnmi3vE8foM6 zJVBZ2QavPU3+6aXPKCJywrViZt8hbP2Iy1zJRrloEjs7sIvyO06WQ4walkeGdFstVCK+H HZiUUleGaEVNEODDTnYGufYQ6HEtI7b+E3JJZHGA21pV95jwXHc6PZQW09hi1I5bgY4R0K HUOheCIkBzcmpZH2fr/cvOg7CJwzsoeB7WLmpRNNssnq1CG74CNGlCS+FNmgzA== ARC-Authentication-Results: i=1; rspamd-9788b98bc-x62tj; auth=pass smtp.auth=dreamhost smtp.mailfrom=dave@stgolabs.net X-Sender-Id: dreamhost|x-authsender|dave@stgolabs.net X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|dave@stgolabs.net X-MailChannels-Auth-Id: dreamhost X-Versed-Tart: 0317de5f04cc1a46_1677268029943_6978840 X-MC-Loop-Signature: 1677268029943:48012232 X-MC-Ingress-Time: 1677268029943 Received: from pdx1-sub0-mail-a250.dreamhost.com (pop.dreamhost.com [64.90.62.162]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384) by 100.116.179.67 (trex/6.7.1); Fri, 24 Feb 2023 19:47:09 +0000 Received: from offworld.. (ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQN2DWqz2d; Fri, 24 Feb 2023 11:47:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268029; bh=GiOeG5lrocXfUVyExHZRoYMiICaJ3EVxSwc8oBrFE+8=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=mpMYESCo8OrAaWMufta4RtYCKwsEuM9G0rpz5p7wA3IKnVJ8AV5E9IT7bq8CBdJo9 1Hm9EsMrkyvEVYYcrg8Fbll/i5kuyut6j5QZtWyGEC9UtwxRCXC1tnMXWLKmtOru6e MBv+US/TW8Qw6Y/iqiyzD2LXzc1naDVlL37MHyFV7/1UCs7Oq167uUvlbTCnsdSnhL 6GclikV/0Hc1M5MZXwKyYcre62Krj1nKlSPRGY0ncvjHT/LQ6CrZuHpThQxqjjoo7G zmOodOmHL8yW4beqibdQXkjeMLOg6xyFijpgcIaMejZJn9GC62I/7scJoRJ/MQq4Rr hKkfaH0MQGV8Q== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 6/7] cxl/mem: Support Secure Erase Date: Fri, 24 Feb 2023 11:46:51 -0800 Message-Id: <20230224194652.1990604-7-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Implement support for the non-pmem exclusive secure erase, per CXL specs. To properly support this feature, create a 'security/erase' sysfs file that when read will list the current pmem security state and when written to, perform the requested operation. Signed-off-by: Davidlohr Bueso --- Documentation/ABI/testing/sysfs-bus-cxl | 12 ++++++ drivers/cxl/core/mbox.c | 56 +++++++++++++++++++++++++ drivers/cxl/core/memdev.c | 32 +++++++++++++- drivers/cxl/cxlmem.h | 2 + 4 files changed, 101 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index b315d78b7e91..91a74e27f248 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -80,6 +80,18 @@ Description: to be flushed. If this sysfs entry is not present then the architecture does not support security features. +What: /sys/bus/cxl/devices/memX/security/erase +Date: February, 2023 +KernelVersion: v6.4 +Contact: linux-cxl@vger.kernel.org +Description: + (WO) Write a boolean 'true' string value to this attribute to + secure erase the device to securely re-purpose or decommission + it. This is done by hanging the media encryption keys for all + user data areas of the device. This causes all CPU caches to + be flushed. If this sysfs entry is not present then the + architecture does not support security features. + What: /sys/bus/cxl/devices/*/devtype Date: June, 2021 KernelVersion: v5.14 diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 885de3506735..bf206fe26839 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1082,6 +1082,62 @@ int cxl_mem_sanitize(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_mem_sanitize, CXL); +/** + * cxl_mem_secure_erase() - Send secure erase command to the device. + * @cxlds: The device data for the operation + * + * Return: 0 if the command was executed successfully. + * Upon error, return the result of the mailbox command or -EINVAL if + * security requirements are not met. CPU caches are flushed before and + * after succesful completion of each command. + * + * See CXL 3.0 @8.2.9.8.5.2 Secure Erase. + */ +int cxl_mem_secure_erase(struct cxl_dev_state *cxlds) +{ + int rc; + u32 sec_out = 0; + struct cxl_get_security_output { + __le32 flags; + } out; + struct cxl_mbox_cmd sec_cmd = { + .opcode = CXL_MBOX_OP_GET_SECURITY_STATE, + .payload_out = &out, + .size_out = sizeof(out), + }; + struct cxl_mbox_cmd mbox_cmd = { + .opcode = CXL_MBOX_OP_SECURE_ERASE, + }; + + if (!cpu_cache_has_invalidate_memregion()) + return -EINVAL; + + rc = cxl_internal_send_cmd(cxlds, &sec_cmd); + if (rc < 0) { + dev_err(cxlds->dev, "Failed to get security state : %d", rc); + return rc; + } + + sec_out = le32_to_cpu(out.flags); + if (sec_out & CXL_PMEM_SEC_STATE_USER_PASS_SET) + return -EINVAL; + + if (sec_out & CXL_PMEM_SEC_STATE_LOCKED) + return -EINVAL; + + cpu_cache_invalidate_memregion(IORES_DESC_CXL); + + rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); + if (rc < 0) { + dev_err(cxlds->dev, "Failed to secure erase device : %d", rc); + return rc; + } + + cpu_cache_invalidate_memregion(IORES_DESC_CXL); + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_mem_secure_erase, CXL); + static int add_dpa_res(struct device *dev, struct resource *parent, struct resource *res, resource_size_t start, resource_size_t size, const char *type) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index a1bb095d081c..6334a0d1a925 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -155,6 +155,34 @@ static ssize_t security_sanitize_store(struct device *dev, static struct device_attribute dev_attr_security_sanitize = __ATTR(sanitize, 0200, NULL, security_sanitize_store); +static ssize_t security_erase_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + ssize_t rc; + bool erase; + + rc = kstrtobool(buf, &erase); + if (rc) + return rc; + + if (erase) { + if (cxl_memdev_active_region(cxlmd)) + return -EBUSY; + + rc = cxl_mem_secure_erase(cxlds); + } + + if (rc == 0) + rc = len; + return rc; +} + +static struct device_attribute dev_attr_security_erase = + __ATTR(sanitize, 0200, NULL, security_erase_store); + static ssize_t serial_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -217,6 +245,7 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = { static struct attribute *cxl_memdev_security_attributes[] = { &dev_attr_security_state.attr, &dev_attr_security_sanitize.attr, + &dev_attr_security_erase.attr, NULL, }; @@ -224,7 +253,8 @@ static umode_t cxl_security_visible(struct kobject *kobj, struct attribute *a, int n) { if (!cpu_cache_has_invalidate_memregion() && - a == &dev_attr_security_sanitize.attr) + (a == &dev_attr_security_sanitize.attr || + a == &dev_attr_security_erase.attr)) return 0; return a->mode; } diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 0d2009b36933..2cf9ec3242a6 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -332,6 +332,7 @@ enum cxl_opcode { CXL_MBOX_OP_SCAN_MEDIA = 0x4304, CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, CXL_MBOX_OP_SANITIZE = 0x4400, + CXL_MBOX_OP_SECURE_ERASE = 0x4401, CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, @@ -632,6 +633,7 @@ static inline void cxl_mem_active_dec(void) #endif int cxl_mem_sanitize(struct cxl_dev_state *cxlds); +int cxl_mem_secure_erase(struct cxl_dev_state *cxlds); struct cxl_hdm { struct cxl_component_regs regs; From patchwork Fri Feb 24 19:46:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 13151749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCD17C64ED8 for ; Fri, 24 Feb 2023 19:47:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229547AbjBXTrO (ORCPT ); Fri, 24 Feb 2023 14:47:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbjBXTrN (ORCPT ); Fri, 24 Feb 2023 14:47:13 -0500 Received: from bird.elm.relay.mailchannels.net (bird.elm.relay.mailchannels.net [23.83.212.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 292396C194 for ; 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Fri, 24 Feb 2023 19:47:11 +0000 Received: from offworld.. (ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a250.dreamhost.com (Postfix) with ESMTPSA id 4PNgQP2kLVz2Q; Fri, 24 Feb 2023 11:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1677268030; bh=ankyqMP5oBsP3OoxQ0mKfhsnHGElQxwf0AyjpHp4i0E=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=BIKI7cz6lAVA6Ti1w84JHLbQrGk6wq2RB0Y2xvgPhFUn/7dT3a13LINcPE19uXTxQ CceJiw04DXzbJidugodutLono5NsF1FZkKUhJTeAZ/m41p4DKEcF0ZHz38a/5I3Olv j6GKMkzUjsSTRAiZiQ0v6sgAsghhBina/AYtz8u5J7RAMxQEJuELYKgrr3aif8OV1E a+OpPwZV4FQEJS4oBStg4xxTQ+gf/a+AbY+APhui3pBEw60wSK4c5WAT0iY431x5Sw 67fOj6PjOP5r7MkdGfefgLEM4A59YYot/EC1v4pG2Pg6OVCxRQYnkFI4L4kl/0lk4e 7tOvg6JiZQPCQ== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: jonathan.cameron@huawei.com, ira.weiny@intel.com, fan.ni@samsung.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 7/7] cxl/test: Add "Secure Erase" opcode support Date: Fri, 24 Feb 2023 11:46:52 -0800 Message-Id: <20230224194652.1990604-8-dave@stgolabs.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224194652.1990604-1-dave@stgolabs.net> References: <20230224194652.1990604-1-dave@stgolabs.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add support to emulate a CXL mem device support the "Secure Erase" operation. Signed-off-by: Davidlohr Bueso Reviewed-by: Dave Jiang --- tools/testing/cxl/test/mem.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index d4466cb27947..8a22a4e592c6 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -519,6 +519,30 @@ static int mock_sanitize(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) return 0; /* assume less than 2 secs, no bg */ } +static int mock_secure_erase(struct cxl_dev_state *cxlds, + struct cxl_mbox_cmd *cmd) +{ + struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); + + if (cmd->size_in != 0) + return -EINVAL; + + if (cmd->size_out != 0) + return -EINVAL; + + if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { + cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; + return -ENXIO; + } + + if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { + cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; + return -ENXIO; + } + + return 0; +} + static int mock_get_security_state(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) { @@ -949,6 +973,9 @@ static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd * case CXL_MBOX_OP_SANITIZE: rc = mock_sanitize(cxlds, cmd); break; + case CXL_MBOX_OP_SECURE_ERASE: + rc = mock_secure_erase(cxlds, cmd); + break; case CXL_MBOX_OP_GET_SECURITY_STATE: rc = mock_get_security_state(cxlds, cmd); break;