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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /j9GOjpUcozFwNSp2aA4l2zd4PSOXc/7YKj1/RGG8uGE32RVVBs8OWYlBFFId4sPnvojP0QfYj8n/IN6n/Gspe3fOjA28Kq53BEq2fKX4Aw2W87b90ZBMGhD/ENKvwt0wwe3hRC2mY0JFEM7K1Ag2iQDAWZ4cYMy9K/Klwcb/WjD5BD++QH/Y2dAP4+pqrZkhxQDFgUjSRMsobBXFtKKwNiXW4NK2af81mWM6iQt5w+WPgZn0IWeW7tfnTl1o/q2T6ZJAcPuMD+n3A7Dmn1UmdvKOhbVHjzzi+vkZZKRP/2FCfJ9Q7EkX648qqhu5BQjWXXtMM6F21IySpKuuwyLMDRPoahhhDQPm5XQgZOlGu8anB0VkFYRQp2r+8pdtmpWre5jBzeeNIh6m9Kee+6w3lmFoldR8DJL/s7SeZ45EBIPbQbfy3k34qlCZXpDTeN9YTq7riYgLBFK5L5uJOv1egLALDNF0ZRUbFbcoN9omKIedVnTUpU74dhTrUMH2AKif0WEEjm2pkX0HZxrLXPj5xl+ZpKT4qBzMbf2NXUEL7kSF7UTNsAyGufb0FjMxKS7rqC3zXKVblwCbpnIdNHVRZ/yHSZVQ2Ol8n1JLqpM78fLVpUzJ9Slg4d50WcyABic4gWqJUngInDGOoE3mYPb6GgukyImRD8YLN+AjnketimYnCTiysoDvh97sbRdPA2B8Ta6+BjS01VwqxnfkOBB9R5ivWhGK2E5ao+kDORsOVXiXmux2ShbGiKfCAFcZp0zdEb2haOprb3sjwbmbuxcRt2El7tAGs+8BGDYN8qcJQynrjWBMPVlV1Iy52D1DORBWhcwR/CbxojgHpIt41MEDZhx0JrqbGlfcvuJxrH4Q95gpJnBi3CDlZIDWgPuAs1FJH95kycaSFW0YSQkY3umdf3EQrElJdxX8eSDZ43VDrxel5uQcoHS5nTYdXeM8p1nQIrd+/MamDRy5FMDLFLOD86Z3ZlfRIksx6SHwehYKGp3ZTja5QHgLCXKZIpdbEryLXnVVjzBgDcKEDyWpwsBNJGVtsZDAvcsG/GZPqfFQwUT2DtwUhzTYN3sXrxJZ/7njoC2COrfQ6nKz5wUp42OldEW5jW/BHLKM0ksGQ6iwJvRQJBVxCtvQv2HMJ1XGr4DKTcRGAzoZ49lhyJOeQo6FewnjLCchdseDYUGwC09hBF6kICdV1DcnWQWABRXkivUTFaSOBFlWSdYDdYLEI1bPbI3Wv+LxOdHqTS5wdWAXI8wTy3hXPQbcmwrzhKqN2o5DGDDc9PKycDkJh+8DcL2vGGTiap/IFUJxZ2ITWwjpaHbXYMsmj9IRqjrXvaIqUHZ9gPAT7zar25En3Sk+00C7y1YqRfz08tM7Nxq3D2xMcA6+8Fpuu1V/g5DD3SiB1RnS1XyyW9XfG6Mu78YV34jjXj+1atSUSNf1zNhZLpPc52zSzWYJEFY4+pdTtgL74t1sNc+BHgTfES/y1xIpeeZajBXTOxg+8BJxdHD6Oy0OIGedvpD6N2X5aDHfjCZT8rtpW/sSxvENHvFIxvdG8kvxrDbQks8R2yPzVhbBrMi0ORnjMt/DEwHnllhMF/94LYcE7Pqmb+q5ZxnqrhoZqnG3gfB8QiAl2pbyfuGw4QxlqA= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: a962cd65-22f7-48e2-c64b-08db19435232 X-MS-Exchange-CrossTenant-AuthSource: DM8PR01MB6824.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2023 04:21:53.6869 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qtkrA5WqKV9fGSlsuWS2l1Ta4B29MZsGp44AH1lB0cWlUvvgxM63ItBZfB7prfKQC0w6ouaMzyyKRHYsqf4C0IwipgBk5hKHQR/5N2oCgeBE+bMc3h6b84OOU7kiZvKw X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4700 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230227_202203_317908_C2CD871A X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per PCI specification (PCI Express Base Specification Revision 6.0, Section 10.5) both PF and VFs of a PCI EP are permitted to be enabled independently for ATS capability, however the STU(Smallest Translation Unit) is shared between PF and VFs. For VFs, it is hardwired to Zero and the associated PF's value applies to VFs. In the current code, the STU is being configured while enabling the PF ATS. Hence, it is not able to enable ATS for VFs, if it is not enabled on the associated PF already. Adding a function pci_ats_stu_configure(), which can be called to configure the STU during PF enumeration. Latter enumerations of VFs can successfully enable ATS independently. Signed-off-by: Ganapatrao Kulkarni Acked-by: Bjorn Helgaas --- drivers/pci/ats.c | 33 +++++++++++++++++++++++++++++++-- include/linux/pci-ats.h | 3 +++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index f9cc2e10b676..1611bfa1d5da 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -46,6 +46,35 @@ bool pci_ats_supported(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_ats_supported); +/** + * pci_ats_stu_configure - Configure STU of a PF. + * @dev: the PCI device + * @ps: the IOMMU page shift + * + * Returns 0 on success, or negative on failure. + */ +int pci_ats_stu_configure(struct pci_dev *dev, int ps) +{ + u16 ctrl; + + if (dev->ats_enabled || dev->is_virtfn) + return 0; + + if (!pci_ats_supported(dev)) + return -EINVAL; + + if (ps < PCI_ATS_MIN_STU) + return -EINVAL; + + dev->ats_stu = ps; + pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl); + ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); + pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_ats_stu_configure); + /** * pci_enable_ats - enable the ATS capability * @dev: the PCI device @@ -68,8 +97,8 @@ int pci_enable_ats(struct pci_dev *dev, int ps) return -EINVAL; /* - * Note that enabling ATS on a VF fails unless it's already enabled - * with the same STU on the PF. + * Note that enabling ATS on a VF fails unless it's already + * configured with the same STU on the PF. */ ctrl = PCI_ATS_CTRL_ENABLE; if (dev->is_virtfn) { diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index df54cd5b15db..7d62a92aaf23 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -8,6 +8,7 @@ /* Address Translation Service */ bool pci_ats_supported(struct pci_dev *dev); int pci_enable_ats(struct pci_dev *dev, int ps); +int pci_ats_stu_configure(struct pci_dev *dev, int ps); void pci_disable_ats(struct pci_dev *dev); int pci_ats_queue_depth(struct pci_dev *dev); int pci_ats_page_aligned(struct pci_dev *dev); @@ -16,6 +17,8 @@ static inline bool pci_ats_supported(struct pci_dev *d) { return false; } static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } +static inline int pci_ats_stu_configure(struct pci_dev *d, int ps) +{ return -ENODEV; } static inline void pci_disable_ats(struct pci_dev *d) { } static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } From patchwork Tue Feb 28 04:21:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ganapatrao Kulkarni X-Patchwork-Id: 13154403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7495C64ED6 for ; Tue, 28 Feb 2023 04:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Tue, 28 Feb 2023 04:21:54 +0000 From: Ganapatrao Kulkarni To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, joro@8bytes.org, bhelgaas@google.com, robin.murphy@arm.com, will@kernel.org Cc: jean-philippe@linaro.org, sathyanarayanan.kuppuswamy@linux.intel.com, darren@os.amperecomputing.com, scott@os.amperecomputing.com, gankulkarni@os.amperecomputing.com Subject: [PATCH v2 2/2] iommu/arm-smmu-v3: Configure STU of a PF if ATS is not enabled. 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In bypass mode, ATS is not enabled on all VFs and associated PF. When VFs are attached to a VM, the corresponding iommu domain is set to SMMU translation mode and smmu-v3 driver try to enable the ATS and fails due to invalid STU of a PF. Adding a fix to configure STU of a PF while enumerating in passthrough mode. Signed-off-by: Ganapatrao Kulkarni --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f2425b0f0cd6..b218ef0bf001 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2292,6 +2292,23 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master) return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)); } +static void arm_smmu_ats_stu_init(struct arm_smmu_master *master) +{ + size_t stu; + struct pci_dev *pdev; + struct arm_smmu_device *smmu = master->smmu; + + if (master->ats_enabled) + return; + + /* Smallest Translation Unit: log2 of the smallest supported granule */ + stu = __ffs(smmu->pgsize_bitmap); + pdev = to_pci_dev(master->dev); + + if (pci_ats_stu_configure(pdev, stu)) + dev_err(master->dev, "Failed to configure ATS STU (%zu)\n", stu); +} + static void arm_smmu_enable_ats(struct arm_smmu_master *master) { size_t stu; @@ -2404,6 +2421,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master *master; + bool ats_supported; if (!fwspec) return -ENOENT; @@ -2446,9 +2464,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) } master->domain = smmu_domain; + ats_supported = arm_smmu_ats_supported(master); if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS) - master->ats_enabled = arm_smmu_ats_supported(master); + master->ats_enabled = ats_supported; arm_smmu_install_ste_for_dev(master); @@ -2458,6 +2477,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) arm_smmu_enable_ats(master); + /* Configure ATS STU of a PF in passthrough */ + if (!master->ats_enabled && ats_supported) + arm_smmu_ats_stu_init(master); + out_unlock: mutex_unlock(&smmu_domain->init_mutex); return ret;