From patchwork Fri Mar 3 13:12:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13158773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51622C678D4 for ; Fri, 3 Mar 2023 13:15:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY5F6-0005FC-B4; Fri, 03 Mar 2023 08:14:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY5F4-000572-Hi for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:14:34 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pY5F2-0008KH-Ib for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:14:34 -0500 Received: by mail-wm1-x335.google.com with SMTP id p26so1541028wmc.4 for ; Fri, 03 Mar 2023 05:14:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1677849271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q244UH1X0Qq28sL8qCMK3QrXi2ZbEVOh6RiT7mirFEc=; b=FhIF7bOK/8tqLWp8TpgHao5zAcw8FSDm53jEHCDrnet1VNq96HpP2XCtqUd3Q+7s4U jInpT2j3DenoQjbcbhBy9wjRmPKxaWXIF+HUNTj+B4Zrlix5sfgpFrKJCJN4Iy+LY/dT vlSLRCTToFFLacWA7BH57Z8uVjAiOxmNhg6f6+ZBoyatctAMqOjXvVfGdhZLCmwyz+dI 4u/KXGlwstuQuY08hvJ1v7oIx61gMQ94v0LF81+EXaCG+NoZtotllOyKUzj6lrdOd+Lr KfiM4zFRGsIL8i3HdJfbDN6reM0QaSHr8q/69LgqNqSJeC32Pdh0LVRuBJQVf2wdc31C ulmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677849271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q244UH1X0Qq28sL8qCMK3QrXi2ZbEVOh6RiT7mirFEc=; b=shhwhd1b7uuYHDsyLY9SXgXGPE+m/4y3CAJs+xDZVaHSmD4OyYffZ08xiSkmQSXSsU eH/AXOutzMCVbcZuAsSX1/5F7prkPqSFIA/WMLdUFuwEVl9x5JOeaBAv6zQqYloJJsAu eQxatKHRZYYwmJ+JbzLUMifN2DhHiACP6W4Vn6zPQXgDjxJcKM9taNcbPJJ1H9BA+rVf /iWlM8QsNTs+N/TfuSO6TNRMUEWKrZdewZAFNthQfi2vyNoVoK/Cdtkb4fKSHInGpx/k y7ZvDrHzb2zoCCFKFzaUxPo9UW5dp3A4QZ02k76/F1vX8/fn4cTcfKgndFNtKK5uk86S bU2A== X-Gm-Message-State: AO0yUKXMSAMIayxhFgI5GPImSNeg9A5v43k/Jwq5/1E21UEvoO/UkJqo 7s7KuryeDsT6Vs0zjYVEFtFmOw== X-Google-Smtp-Source: AK7set97Mn0O2StlUdYm3F5ghjiVUP/+9pUmncJscr9u5f+hbf6vADx5+XPbzmOg3tZGeFe/sp4qyg== X-Received: by 2002:a05:600c:4687:b0:3e2:201a:5bcc with SMTP id p7-20020a05600c468700b003e2201a5bccmr1622369wmo.33.1677849271120; Fri, 03 Mar 2023 05:14:31 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id z4-20020a056000110400b002ce3b31753fsm1103722wrw.26.2023.03.03.05.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:14:30 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v11 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Fri, 3 Mar 2023 14:12:48 +0100 Message-Id: <20230303131252.892893-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230303131252.892893-1-alexghiti@rivosinc.com> References: <20230303131252.892893-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9eb748a283..5dc11d6670 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -213,7 +213,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -251,7 +251,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -260,7 +260,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -269,7 +269,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -279,7 +279,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -324,7 +324,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -334,7 +334,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -353,7 +353,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -364,7 +364,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; cpu->cfg.epmp = true; @@ -376,7 +376,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -391,7 +391,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1161,11 +1161,12 @@ static Property riscv_cpu_extensions[] = { * properties and leave. env.misa_ext = 0 means that we want * all the default properties to be registered. */ -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { - RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); + RISCVCPU *cpu = RISCV_CPU(obj); uint32_t misa_ext = cpu->env.misa_ext; Property *prop; + DeviceState *dev = DEVICE(obj); /* * If misa_ext is not zero, set cfg properties now to From patchwork Fri Mar 3 13:12:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13158774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7D98C678D4 for ; Fri, 3 Mar 2023 13:15:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY5G5-00081O-9b; Fri, 03 Mar 2023 08:15:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY5G3-0007q8-B0 for qemu-devel@nongnu.org; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id v38-20020a05600c4da600b003eb68bb61c8sm2063077wmp.3.2023.03.03.05.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:15:31 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v11 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Fri, 3 Mar 2023 14:12:49 +0100 Message-Id: <20230303131252.892893-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230303131252.892893-1-alexghiti@rivosinc.com> References: <20230303131252.892893-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693..163eb3b82b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1123,16 +1123,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1215,7 +1215,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2641,7 +2641,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; From patchwork Fri Mar 3 13:12:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13158775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 012F1C64EC4 for ; Fri, 3 Mar 2023 13:17:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY5H6-0004DL-Hr; Fri, 03 Mar 2023 08:16:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY5H2-000456-U5 for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:16:37 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pY5H0-0000Yr-J4 for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:16:36 -0500 Received: by mail-wr1-x429.google.com with SMTP id bw19so2185582wrb.13 for ; Fri, 03 Mar 2023 05:16:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1677849393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9kFK5nQEwRHbzwaL5rnvzVrCzc2i5+OtM4kq8PfGYNk=; b=OJzBO4f0bZ1IZrn8XKvO9DJkPK1CSwVwIGGie0MQxze+XkCUJU/OeqgsaI33YfTu1b ipW4ghmG2L4koq76WWtt1WobHjEZclDNDCNCCHLmbtw5JSj8ySmPHclQyjHAh9yI6DRo dOsBHCyUN8iv8PsKysCylH+60JM3buHH87/ZCa+/8BSRXd8n+/y8MuP7TWO/UW/OUO/o mKvNW4L3QbT9zZ0Mo+sSg0RgqunNBQ3+yrY+y6VOWdAWdk+7uiEic5iqRKXHzXCvSTX2 r+D2UCwk6uSqiHXeIDexoM3lF00LGAH+a2gAojusmSbLBxrh2hPIk3hlnhVsPiHqSvZP uwPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677849393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9kFK5nQEwRHbzwaL5rnvzVrCzc2i5+OtM4kq8PfGYNk=; b=J+eZeE814G7lYbuCO3i/v+o8JmIvHkIqnZ2NdO1bf3Hdws1cqohcvgxEAueYVPe8t+ lLbmKUltWRWX6l4u+AxJuCIgQYkHpGUZqEmfVUGuUOsiX1VlmZ4vYEJxH4+KsoUUqaEb UUDKufbRiXFVQZkZBrPfVRgs/avZC76FfGTEVIxvv2a6rgPEVhhofJL7YvKuOwyDaex/ GLas3xdyu8yX9y9aHwAwfWBgs6RjTRlriJzZZEu6YJZ0mJAImji4+uYSK6MmmI3Z1RLt LO1MuOeLib0sAWG795M3hNkijYuwTxoQyEWMsrji4dh6gqiARBTQcjKSkKYzMhV3lj7w NnSA== X-Gm-Message-State: AO0yUKXhDjggsdhhBBsNL7VYLG5D64bMXHgNdb4J6dC9iN2kfFXZAni7 zoKEc8vuomOE9tdV/INU5rjitA== X-Google-Smtp-Source: AK7set9yEN4YzH4uQGJZFigBe5lKOS3VUZJeuYjBFnIYIhnaVniYeSDKpgNVykXmu9D+dd/1psGEvw== X-Received: by 2002:a5d:6407:0:b0:2c5:4dbd:dfa3 with SMTP id z7-20020a5d6407000000b002c54dbddfa3mr1306076wru.21.1677849392921; Fri, 03 Mar 2023 05:16:32 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id h16-20020a5d5490000000b002ce37d2464csm1224482wrv.83.2023.03.03.05.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:16:32 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry , Bin Meng Subject: [PATCH v11 3/5] riscv: Allow user to set the satp mode Date: Fri, 3 Mar 2023 14:12:50 +0100 Message-Id: <20230303131252.892893-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230303131252.892893-1-alexghiti@rivosinc.com> References: <20230303131252.892893-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 214 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 21 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 240 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5dc11d6670..6de2ca0eaa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -28,6 +28,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -242,6 +243,82 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +#ifndef CONFIG_USER_ONLY +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57)); + } else { + cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE); + } +} +#endif + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -870,6 +947,87 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) set_misa(env, env->misa_mxl, ext); } +#ifndef CONFIG_USER_ONLY +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map == 0) { + if (cpu->cfg.satp_mode.init == 0) { + /* If unset by the user, we fallback to the default satp mode. */ + set_satp_mode_default_map(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.map |= (1 << i); + } + } +} +#endif + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ +#ifndef CONFIG_USER_ONLY + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +#endif +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -980,6 +1138,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -989,6 +1153,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = satp_map->map & (1 << satp); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + static void riscv_cpu_set_irq(void *opaque, int irq, int level) { RISCVCPU *cpu = RISCV_CPU(opaque); @@ -1197,6 +1407,10 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + +#ifndef CONFIG_USER_ONLY + riscv_add_satp_mode_properties(obj); +#endif } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 31537fc05f..7af91359a5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -414,6 +415,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -500,6 +512,10 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + +#ifndef CONFIG_USER_ONLY + RISCVSATPMap satp_mode; +#endif }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -806,9 +822,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 163eb3b82b..87958c1adc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1123,12 +1123,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1217,11 +1217,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; - } else { - return valid_vm_1_10_64[vm & 0xf]; - } + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); + + return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map); } static RISCVException write_mstatus(CPURISCVState *env, int csrno, From patchwork Fri Mar 3 13:12:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13158776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E55BC678D4 for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id o33-20020a05600c512100b003e209186c07sm7263479wms.19.2023.03.03.05.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:17:33 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v11 4/5] riscv: Introduce satp mode hw capabilities Date: Fri, 3 Mar 2023 14:12:51 +0100 Message-Id: <20230303131252.892893-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230303131252.892893-1-alexghiti@rivosinc.com> References: <20230303131252.892893-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 93 ++++++++++++++++++++++++++++++++++------------ target/riscv/cpu.h | 8 +++- 2 files changed, 75 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6de2ca0eaa..d4584299db 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -306,17 +306,24 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default_map(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57)); - } else { - cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE); + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } + +/* Set the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; +} #endif static void riscv_any_cpu_init(Object *obj) @@ -327,6 +334,13 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); +#endif + set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); } @@ -340,6 +354,9 @@ static void rv64_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); +#endif } static void rv64_sifive_u_cpu_init(Object *obj) @@ -348,6 +365,9 @@ static void rv64_sifive_u_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); +#endif } static void rv64_sifive_e_cpu_init(Object *obj) @@ -359,6 +379,9 @@ static void rv64_sifive_e_cpu_init(Object *obj) register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } static void rv64_thead_c906_cpu_init(Object *obj) @@ -388,6 +411,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.ext_xtheadsync = true; cpu->cfg.mvendorid = THEAD_VENDOR_ID; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV39); +#endif } static void rv128_base_cpu_init(Object *obj) @@ -404,6 +430,9 @@ static void rv128_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); +#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -414,6 +443,9 @@ static void rv32_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif } static void rv32_sifive_u_cpu_init(Object *obj) @@ -422,6 +454,9 @@ static void rv32_sifive_u_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif } static void rv32_sifive_e_cpu_init(Object *obj) @@ -433,6 +468,9 @@ static void rv32_sifive_e_cpu_init(Object *obj) register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } static void rv32_ibex_cpu_init(Object *obj) @@ -444,6 +482,9 @@ static void rv32_ibex_cpu_init(Object *obj) register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif cpu->cfg.epmp = true; } @@ -456,6 +497,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); +#endif } #endif @@ -951,8 +995,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { if (cpu->cfg.satp_mode.init == 0) { @@ -965,9 +1010,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * valid_vm_1_10_32/64. */ for (int i = 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -978,37 +1024,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } /* Finally expand the map so that all valid modes are set */ - for (int i = satp_mode_max - 1; i >= 0; --i) { - if (valid_vm[i]) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { + if (cpu->cfg.satp_mode.supported & (1 << i)) { cpu->cfg.satp_mode.map |= (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7af91359a5..ad291ee13f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -417,13 +417,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { From patchwork Fri Mar 3 13:12:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13158777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44EE0C64EC4 for ; Fri, 3 Mar 2023 13:18:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY5J3-0007kb-Hm; Fri, 03 Mar 2023 08:18:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY5Iz-0007k5-L9 for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:18:38 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pY5Ix-0001Cg-Uc for qemu-devel@nongnu.org; Fri, 03 Mar 2023 08:18:37 -0500 Received: by mail-wm1-x32f.google.com with SMTP id d41-20020a05600c4c2900b003e9e066550fso1222566wmp.4 for ; Fri, 03 Mar 2023 05:18:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1677849514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i04DfVNT3wWKNZazOpk4mHXgOMtB63hku687MDx0WG0=; b=sVI+MON0FWq6Gq3kwldHSn2Otdz21k9w8Z1Rrx8ue88L1SSwHkNQbmttlTDJcssdBc KMtrNFQIvwEA/fSNZAZGa4EphmObobgtuE4HcGuS9W7ExwLklr5gMEuIe1JP8yHgcjDJ s9up5iTe253BUr7AZ2Y/cNv5zvYpzpzDiQ7/7UXowad2ZmFJjJZExwCn3q2JPpWOpL3z KwO2ce+PZpBGzJB4dbUpqL/md6NH+NSIMTxMCrUj9xPna+l3zCQlgBS8cMy/HcoJdGJ4 uOU1hHhy3ndx8XusACQb5w4Udao4oUXjz9OBLKf4JR9gljvjhqygHlsrVUMdVRzTAB+V kWwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677849514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i04DfVNT3wWKNZazOpk4mHXgOMtB63hku687MDx0WG0=; b=MUNqg5ZJFcN++QAoUsu2ZbqpoXc31fUzpI0lWeTfcK9Xr3bErFdWVp/9FNg5qXIsbV u/nhnxQ3Qlxd5L4vRk8UyroQt9FPq98vFE84TivHTdNV4F2D3qA9KQYNlgyAUJSpWNjt TiRs2fG7/j/a1CnwCJG6abY0/PgkXTDlWSIdHJHa84CY6cQCCpu1mvjilFGoxz+a8wKw X28M3P8iJOVXvZqGm1VqpLPMIoU7UTNWCRouGz4pe5s2LAsah+LpCXMNnVwW8dI+Lyzy RQ01Wzw17b0ELSFJcBmgoNzkaLCQhP8p11HkT+4r4S/V/Y1y5VCTrHzOnnkqRODv560j kpEw== X-Gm-Message-State: AO0yUKVgu/Gkp1Otl66oDNLDjkYMImWG4kJrsKTM4EpGcB8EeeXyUKVR BozK5nWDxJuR6f/xbijjiFS7rw== X-Google-Smtp-Source: AK7set/7eGaDOpkxT9zm4hGt70Efm6Dh8AAq1gjRvTfyIs3YJeqKYioyYakuQvLGXAMHa+P8oxxL5w== X-Received: by 2002:a1c:2b86:0:b0:3ea:ed4d:38ee with SMTP id r128-20020a1c2b86000000b003eaed4d38eemr1701504wmr.4.1677849514315; Fri, 03 Mar 2023 05:18:34 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id r3-20020a1c2b03000000b003e9ae2a8cbfsm2684887wmr.2.2023.03.03.05.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:18:34 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Fri, 3 Mar 2023 14:12:52 +0100 Message-Id: <20230303131252.892893-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230303131252.892893-1-alexghiti@rivosinc.com> References: <20230303131252.892893-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 86c4adc0c9..59922d6965 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,8 +228,9 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *ms = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); + uint8_t satp_mode_max; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -237,14 +238,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); - } else { - qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + satp_mode_max = satp_mode_max_from_map( + s->soc[socket].harts[cpu].cfg.satp_mode.map); + sv_name = g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_bit)); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); + g_free(sv_name); + name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name);