From patchwork Sat Mar 4 22:15:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A783C678DB for ; Sat, 4 Mar 2023 22:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229461AbjCDWPj (ORCPT ); Sat, 4 Mar 2023 17:15:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229437AbjCDWPi (ORCPT ); Sat, 4 Mar 2023 17:15:38 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D42C512F22 for ; Sat, 4 Mar 2023 14:15:36 -0800 (PST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 7AF9B5C0101; Sat, 4 Mar 2023 17:15:35 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Sat, 04 Mar 2023 17:15:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968135; x= 1678054535; bh=6wu56FuUf5PEAXYiDOFQaP4gNqab8JFzm14DGfaET4A=; b=L fND/DOLdlKm1ufsqFjiyx/iq6zK3mgNu8lCHOzcDvx0fqfQ/UkuSoAJTd4KjrPfj QEk+Xq0vgk1JlOSz5gCnw/tmS7HuJeKhW5YXvrEu7j7Calg3SoBeHnDkd2t+i6tN RTE1k4MRlQr+1jhZYsrg/WEBdlu801CcN1GQEue57LiFNaF1ZhQM7u7o9bDlP2hL 6ws22/HQaX1MeQ87bt+3vUPYtVPNh/VL4SjlKKN19d5NpEhM2d16tj6TCylR7Qg6 PCjRqZ63eIscGEyAw5VSBculbeITTxO1+lPQSCstaOhQBctoDeWjcYrWjGPskRNq ELMO3KFUV5caxtMZU5hjA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968135; x= 1678054535; bh=6wu56FuUf5PEAXYiDOFQaP4gNqab8JFzm14DGfaET4A=; b=H 89j96yLIvbyugdaT84BvLRHQTCOQ+neMTQA34R/4zAfD3gORk/5gaANOIM/3onIb f+vwyG15ewIwdFgvIiXl97j9E9tCWLnfvOgmg0onyCrkRTIcSRYCjwBNBLL7xSLv l0KRfOC0JAdks35sZTBiy5MOGVDBYte9mEV6uoW0zB1RKtUwd8iEQQ5lL3wbzrRK Qgr/C3Il0DjqR2DtoA4x/oh0Fs7U4v+MQQjOqHM/3xkoWZbIf5bjSH+srEb2/kkx fofnkXi4CTT/7h0KxQteD7PLwtszi+WcTTF51HWwDidbvL7nBov/QGP4ZQFqgyLk 2SlDzp4EHMC2M+hGgCPLQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehhecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:34 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 01/12] MIPS: Move declaration of bcache ops to cache.c Date: Sat, 4 Mar 2023 22:15:13 +0000 Message-Id: <20230304221524.47160-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org bcache is not tied to CPU's cache interface. Just move those declaration to cache.c so it can be avaialble to CPU with all cache types. Signed-off-by: Jiaxun Yang --- arch/mips/mm/c-r4k.c | 14 -------------- arch/mips/mm/cache.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a549fa98c2f4..fd660d5c5328 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -110,20 +110,6 @@ static unsigned long dcache_size __read_mostly; static unsigned long vcache_size __read_mostly; static unsigned long scache_size __read_mostly; -/* - * Dummy cache handling routines for machines without boardcaches - */ -static void cache_noop(void) {} - -static struct bcache_ops no_sc_ops = { - .bc_enable = (void *)cache_noop, - .bc_disable = (void *)cache_noop, - .bc_wback_inv = (void *)cache_noop, - .bc_inv = (void *)cache_noop -}; - -struct bcache_ops *bcops = &no_sc_ops; - #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 11b3e7ddafd5..25cedd6ee572 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,22 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_icache_all); +#ifdef CONFIG_BOARD_SCACHE +/* + * Dummy cache handling routines for machines without boardcaches + */ +static void cache_noop(void) {} + +static struct bcache_ops no_sc_ops = { + .bc_enable = (void *)cache_noop, + .bc_disable = (void *)cache_noop, + .bc_wback_inv = (void *)cache_noop, + .bc_inv = (void *)cache_noop +}; + +struct bcache_ops *bcops = &no_sc_ops; +#endif + #ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ From patchwork Sat Mar 4 22:15:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 129B5C6FD18 for ; Sat, 4 Mar 2023 22:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbjCDWPk (ORCPT ); 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Sat, 4 Mar 2023 17:15:35 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 02/12] MIPS: smp-cps: Disable coherence setup for unsupported ISA Date: Sat, 4 Mar 2023 22:15:14 +0000 Message-Id: <20230304221524.47160-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We don't know how to do coherence setup on ISA before MIPS Release 1. As CPS support only servers simulation purpose on those cores, and simulators are always coherent, just disable initialization code and provide user a warning in case coherence is not setup properly. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/cps-vec.S | 5 +++++ arch/mips/kernel/smp-cps.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 8ef492da827f..64ecfdac6580 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -116,6 +116,8 @@ not_nmi: li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS mtc0 t0, CP0_STATUS + /* We don't know how to do coherence setup on earlier ISA */ +#if MIPS_ISA_REV > 0 /* Skip cache & coherence setup if we're already coherent */ lw s7, GCR_CL_COHERENCE_OFS(s1) bnez s7, 1f @@ -129,6 +131,7 @@ not_nmi: li t0, 0xff sw t0, GCR_CL_COHERENCE_OFS(s1) ehb +#endif /* MIPS_ISA_REV > 0 */ /* Set Kseg0 CCA to that in s0 */ 1: mfc0 t0, CP0_CONFIG @@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes) nop END(mips_cps_boot_vpes) +#if MIPS_ISA_REV > 0 LEAF(mips_cps_cache_init) /* * Clear the bits used to index the caches. Note that the architecture @@ -588,6 +592,7 @@ dcache_done: jr ra nop END(mips_cps_cache_init) +#endif /* MIPS_ISA_REV > 0 */ #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 4fc288bb85b9..f968a319d87f 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -361,6 +361,8 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) static void cps_init_secondary(void) { + int core = cpu_core(¤t_cpu_data); + /* Disable MT - we only want to run 1 TC per VPE */ if (cpu_has_mipsmt) dmt(); @@ -376,6 +378,9 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } + if (core > 0 && !read_gcr_cl_coherence()) + pr_warn("Core %u is not in coherent domain\n", core); + if (cpu_has_veic) clear_c0_status(ST0_IM); else From patchwork Sat Mar 4 22:15:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C833C6FA8E for ; Sat, 4 Mar 2023 22:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229590AbjCDWPk (ORCPT ); Sat, 4 Mar 2023 17:15:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbjCDWPi (ORCPT ); Sat, 4 Mar 2023 17:15:38 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3556C13DDE for ; Sat, 4 Mar 2023 14:15:38 -0800 (PST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 9DCE95C0106; Sat, 4 Mar 2023 17:15:37 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Sat, 04 Mar 2023 17:15:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968137; x= 1678054537; bh=FyiMnbB7vO9pKAJ1t/+CxPIKESYZIYJEg2a1QH+wfQ8=; b=B HhLKo5GuHr1+dLVzEass+HU63KzURwi6TEFYfnkk4dq9dsIQ59+UnsssZJ+aK3sP qsSyJdnDxojaU1Fq/UT6FVPmMBik7jBSOeuRQsmMm3+cDWbLUCDSliuw4PuU2SzT 4quzLeZYzwYlH4lrAvFbM96p9N0wsch1O0wfClpu9KGnziJwCvUaKizInucZkF+0 INxuYAJnhe2Hh/QkvvnRw9vQg/3430Qh9pew6tynpyBAsHFqoizIRysX5ofNZRKd 7y8MWeeQW1UD0zJVQAOLzTiZ5H56R+94Y6eg6YW6jlsWFiZDpQ53CuLtXrz1bkx9 Qdwm84BWD7UuCaLU1f30Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968137; x= 1678054537; bh=FyiMnbB7vO9pKAJ1t/+CxPIKESYZIYJEg2a1QH+wfQ8=; b=t a+m2WdbLYeQSTLijUzxhiv3/aCVA1D+LLAVK4JBbDiDl0tEp2cKAfduGP1rRDLbQ fqgEJRUnjmHIneW2TU8/F8hVEyOMvOUCQDBzplOzEr+KFUs5dMgoCmh65aRgYuhG 8hsQC+y2mv9zPH8No94NOgRRNJzbbS+J2Pn7CWi44HrLxQZ2/G9TKiPYoM+MYtka OavMmf/DV9kzmFDBDd0PRo3YnTnjzL6zg1N7JkQyyHroUdLplck+j3fwkF7C9NDK 9grqjwbLFTwkJANdASPVc3kAkENqf10OjLghqPo4BvhSxDeXJ7n7L72dTZDbCuo6 /5OP2J4JvRx3w5HODJpvw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:36 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 03/12] MIPS: mips-cm: Check availability of config registers Date: Sat, 4 Mar 2023 22:15:15 +0000 Message-Id: <20230304221524.47160-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Prevent reading unsupported config register during probing process. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/mips-cm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index b4f7d950c846..3f00788b0871 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); phys_addr_t __mips_cm_phys_base(void) { - u32 config3 = read_c0_config3(); unsigned long cmgcr; /* Check the CMGCRBase register is implemented */ - if (!(config3 & MIPS_CONF3_CMGCR)) + if (!(read_c0_config() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config2() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config3() & MIPS_CONF3_CMGCR)) return 0; /* Read the address from CMGCRBase */ From patchwork Sat Mar 4 22:15:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42827C6FD19 for ; Sat, 4 Mar 2023 22:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229615AbjCDWPl (ORCPT ); Sat, 4 Mar 2023 17:15:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229519AbjCDWPk (ORCPT ); Sat, 4 Mar 2023 17:15:40 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C78412F22 for ; Sat, 4 Mar 2023 14:15:39 -0800 (PST) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id B18095C00F4; Sat, 4 Mar 2023 17:15:38 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Sat, 04 Mar 2023 17:15:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968138; x= 1678054538; bh=wIDTEiHzh6Ropf3Pdulwmt7BPaBwI6CcgfYjGy9/w/Q=; b=D npk+L0UeS4u8EwAUVFobdkspFgnx9pgUaMknItGjoWWLxPTpx+4vFvk0mLFf6Lfl g7Fjmp/zXPiE/tLqXWiuuc7urF+oAECyxLYKa0qozjV/XwZLAjTTQ+kP22idhq4W wo9jIdiR8LAVeecyQQ+2JNU0Ba7zLIxj9VoZA8pq9Akqjx1JnPZCGSYe6uque/R9 DwUvT51Ti5J/6tWaOOVXMQOy1oaYoOBEOjwO+pCdk8fzzhkDgfX3oTC6bh/wNBG3 9k0vXnNT6i2sFb/9JiwY9fHyyiFLwf1OQaiVLGibi5JwlkZ3ZwC91D5kKDDQsB9A KzBFgHrL65z6L8dBvSUUQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968138; x= 1678054538; bh=wIDTEiHzh6Ropf3Pdulwmt7BPaBwI6CcgfYjGy9/w/Q=; b=Y pU0CyAf5jltoxhrAYX5MMXIPW2zRQIHWTiG0eHHqFL8UyxE1av3dnnH4ardJJyx2 wPPEWeBEpVHuEeTT72dI8f1rSSpiLkzRKrvgW7e1v+/bjqgAjDsT8nYl9MzTB+dM SduKoJZxJGKbiF9+85HFMPvUoKCjWdEBVlVxmJhINM/WMfTlmeFbzSYRfNMxXpbZ JL8qAuSMKZfGf3+af+6ZLQjD+jtlASMCVSccyFWUhb1A+901Wyufxo8pl/5bvSoO omExICkc9sXCmJB91IpOk08eT4RKr40qTe1hsEKbF/4sjbMNz4f445Mkx1qZqjR+ CtIAD628irar/mtCik53Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:37 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature Date: Sat, 4 Mar 2023 22:15:16 +0000 Message-Id: <20230304221524.47160-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Octeon has a different cache interface with traditional R4K one, just opt-out this flag for octeon to avoid run R4K cache initialization code accidentally. Also remove ISA level assumption for 4k cache. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/cpu-features.h | 2 +- arch/mips/kernel/cpu-probe.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c0983130a44c..c613426b0bfc 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -118,7 +118,7 @@ #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) #endif #ifndef cpu_has_4k_cache -#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) +#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) #endif #ifndef cpu_has_octeon_cache #define cpu_has_octeon_cache 0 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7ddf07f255f3..6d15a398d389 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + /* Octeon has different cache interface */ + c->options &= ~MIPS_CPU_4K_CACHE; switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: From patchwork Sat Mar 4 22:15:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5855C6FD1A for ; Sat, 4 Mar 2023 22:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229519AbjCDWPm (ORCPT ); Sat, 4 Mar 2023 17:15:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229607AbjCDWPl (ORCPT ); Sat, 4 Mar 2023 17:15:41 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6459913D4C for ; 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Sat, 4 Mar 2023 17:15:38 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 05/12] MIPS: cpu-features: Enable octeon_cache by cpu_type Date: Sat, 4 Mar 2023 22:15:17 +0000 Message-Id: <20230304221524.47160-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org cpu_has_octeon_cache was tied to 0 for generic cpu-features, whith this generic kernel built for octeon CPU won't boot. Just enable this flag by cpu_type. It won't hurt orther platforms because compiler will eliminate the code path on other processors. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/cpu-features.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c613426b0bfc..51a1737b03d0 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -121,7 +121,24 @@ #define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) #endif #ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 +#define cpu_has_octeon_cache \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 1; \ + break; \ + \ + default: \ + __res = 0; \ + } \ + \ + __res; \ +}) #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu From patchwork Sat Mar 4 22:15:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD00CC678DB for ; Sat, 4 Mar 2023 22:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229607AbjCDWPn (ORCPT ); Sat, 4 Mar 2023 17:15:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229651AbjCDWPm (ORCPT ); Sat, 4 Mar 2023 17:15:42 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 955CA15561 for ; Sat, 4 Mar 2023 14:15:41 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 1149E5C00F4; Sat, 4 Mar 2023 17:15:41 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Sat, 04 Mar 2023 17:15:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968141; x= 1678054541; bh=HNkAfdxffXQLdeoL0w3dAD1nPfxPtiCA6XUALlUExAc=; b=L 8JsdJVVfULtx+2YKGzqLPFT5ZASib6MzTuXjVmLbWu6rGAAD4xE8/dn6SLXSIVHG XP3SCLVznAGk71P7Y1SXuGqtL2LcJPb7Q8Sfm7FOg39v31+PwsubNeF5qdRdiyJP mXuDPR9tbmH5DsOk4XfwiKveINR85my3KHwhiFZze8m+9ryGO65KgVoZ0IMzZtti ynshgxa8rJI7cBEkRINZb0/6MBYJdKssn/W7kLo1iGZqboC9iXzBlRGKH406xZ3q gG5vkE6zCtI6GHreXSWfPS5dkSDGGvxytQ1sr8z8ZsUkCIhm67FPerT1xvcD6+lQ 5ckFA4jrZNQ6MbnhAcrsQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968141; x= 1678054541; bh=HNkAfdxffXQLdeoL0w3dAD1nPfxPtiCA6XUALlUExAc=; b=I 0hWqnD0sv8sg9GFPDGosJU6P2N34SQWaUCOHsnmRy7a3ITcmXmWWA1lb3tOz+Hr3 gUBUAQamA/SZkmwC2Nfxkd2AzlqM2LxvLVPjgFcOzwGjIBGsQmgGuWXi84tgZzy8 Yf/oYIdevgK71P8EbBHfS8MHmXVYcUxlgvOwmGbzVO/CprCszz8EZLuF5mtVbmmD J8fZZJwVmF1ud+NGOyqR2wVCBiIMDaIENHBI/KYAQh9eNRZc3eNgAjR47S/uSdgL DioVwS0RWJzFWxeWJhS3xqr8zV7IymkVZoOTxMQxySEPDTwKcW1F6Y3ZMa/u1Wux Ur4MSy0zn8TloUO8sXbjQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:40 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 06/12] MIPS: c-octeon: Provide alternative SMP cache flush function Date: Sat, 4 Mar 2023 22:15:18 +0000 Message-Id: <20230304221524.47160-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Curretly c-octeon relies on octeon's own smp function to flush I-Cache. However this function is not available on generic platform. Just use smp_call_function_many on generic platform. Signed-off-by: Jiaxun Yang --- arch/mips/mm/c-octeon.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index c7ed589de882..61db09e5044c 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -83,8 +83,14 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) else mask = *cpu_online_mask; cpumask_clear_cpu(cpu, &mask); - for_each_cpu(cpu, &mask) +#ifdef CONFIG_CAVIUM_OCTEON_SOC + for_each_cpu(cpu, &mask) { octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); + } +#else + smp_call_function_many(&mask, (smp_call_func_t)octeon_local_flush_icache, + NULL, 1); +#endif preempt_enable(); #endif From patchwork Sat Mar 4 22:15:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3098EC6FD1B for ; Sat, 4 Mar 2023 22:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229653AbjCDWPo (ORCPT ); Sat, 4 Mar 2023 17:15:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229651AbjCDWPn (ORCPT ); Sat, 4 Mar 2023 17:15:43 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB7F316336 for ; Sat, 4 Mar 2023 14:15:42 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 3515E5C0101; Sat, 4 Mar 2023 17:15:42 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sat, 04 Mar 2023 17:15:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968142; x= 1678054542; bh=fDyL1JljQsZoXFLAXwN//RV19WQQKUijfcIVBv0fh6k=; b=L RS2ZXbxNFyHrT3ZMpW1Kb/Xn6dpcCConGmpD8CQ5PANpRxLAa7aeTgC6clNG00Jm UN2HMscDDQELfUdAAMg9W797pvPtOGkRsGGKkAKl6znn0gtttMMRg7Irsiz7TJ2O I9d3ROTCsG/V54BZ6bJj+gi14sshqRp1bBr9NwB4hqNtF4BxhEN0ZiCJtlNdZEsq PZQEGY/cQ7JL29niy3ibMvsZV+PcjNdSl/SM0BaevGl5/VwBpsIDYmpvQhHac4e5 HrAEf/QQrlOnRH7h66ESWJ/F6d4cLPreARZyj78UprxBvy9d3auETkfSxGhLkLDJ /HniLaO/SxT1hy4pUh5dg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968142; x= 1678054542; bh=fDyL1JljQsZoXFLAXwN//RV19WQQKUijfcIVBv0fh6k=; b=Q WjTClmn8oKBHv2CUXoVdjfQSMaOH9GwnMEaxp7lkj/2pqs5fVutohSKaALammG+G 8Ev0qas0lLQNvWS+tbFSSQWMT2LKRw09dqhYgo8SnIEP2DwutAoW11xDo5zr5Uhx /ZY+kUIhDxBnDPFxUw+gs6cRmdOCpCOtb/Ug0Ewi9zmQnSmkDMZR838ODzG9+2UB yt71v+SM/NdiVkU1/ZjphPIImWo+rituSs3XmIJs2RtY7/7hQxnJR7Dxu5hHdhJV 6UFV3XgfviWKhNXESjZt5VDqcKj8LCstV7Qz4wnnN+NafAic9Xoe3Zg4KZK9Bdsp Ot1gcsyC+zPv1QECYvWjw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehhecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:41 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 07/12] MIPS: Octeon: Allow CVMSEG to be disabled Date: Sat, 4 Mar 2023 22:15:19 +0000 Message-Id: <20230304221524.47160-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Don't include cvmseg states into thread_status when CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE is not defined or 0. Fix compile for kernel without this feature. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/processor.h | 7 ++++++- arch/mips/kernel/asm-offsets.c | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3fde1ff72bd1..ae2cd37a38f0 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -202,11 +202,13 @@ struct octeon_cop2_state { #define COP2_INIT \ .cp2 = {0,}, +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 struct octeon_cvmseg_state { unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] [cpu_dcache_line_size() / sizeof(unsigned long)]; }; - +#endif #else #define COP2_INIT #endif @@ -263,7 +265,10 @@ struct thread_struct { unsigned long trap_nr; #ifdef CONFIG_CPU_CAVIUM_OCTEON struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); +#endif #endif struct mips_abi *abi; }; diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index c4501897b870..40fd4051bb3d 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void) OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3); OFFSET(THREAD_CP2, task_struct, thread.cp2); +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); +#endif BLANK(); } #endif From patchwork Sat Mar 4 22:15:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40B1BC678D5 for ; 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Sat, 4 Mar 2023 17:15:42 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 08/12] MIPS: Loongson: Move arch cflags to MIPS top level Makefile Date: Sat, 4 Mar 2023 22:15:20 +0000 Message-Id: <20230304221524.47160-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Arch cflags should be independent to Platform. Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 38 ++++++++++++++++++++++++++++++++++ arch/mips/loongson2ef/Platform | 35 ------------------------------- arch/mips/loongson64/Platform | 16 -------------- 3 files changed, 38 insertions(+), 51 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 04e46ec24319..a7a4ee66a9d3 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -181,9 +181,47 @@ endif cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +# Some -march= flags enable MMI instructions, and GCC complains about that +# support being enabled alongside -msoft-float. Thus explicitly disable MMI. +cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi) +ifdef CONFIG_CPU_LOONGSON64 +cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap +cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a +cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 +endif +cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi) + cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS +cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop +cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump +endif + +# +# Some versions of binutils, not currently mainline as of 2019/02/04, support +# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction +# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a +# description). +# +# We disable this in order to prevent the assembler meddling with the +# instruction that labels refer to, ie. if we label an ll instruction: +# +# 1: ll v0, 0(a0) +# +# ...then with the assembler fix applied the label may actually point at a sync +# instruction inserted by the assembler, and if we were using the label in an +# exception table the table would no longer contain the address of the ll +# instruction. +# +# Avoid this by explicitly disabling that assembler behaviour. If upstream +# binutils does not merge support for the flag then we can revisit & remove +# this later - for now it ensures vendor toolchains don't cause problems. +# +cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # For smartmips configurations, there are hundreds of warnings due to ISA overrides # in assembly and header files. smartmips is only supported for MIPS32r1 onwards diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform index c6f7a4b95997..d446b705fba4 100644 --- a/arch/mips/loongson2ef/Platform +++ b/arch/mips/loongson2ef/Platform @@ -2,41 +2,6 @@ # Loongson Processors' Support # -cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -# -# Some versions of binutils, not currently mainline as of 2019/02/04, support -# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction -# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a -# description). -# -# We disable this in order to prevent the assembler meddling with the -# instruction that labels refer to, ie. if we label an ll instruction: -# -# 1: ll v0, 0(a0) -# -# ...then with the assembler fix applied the label may actually point at a sync -# instruction inserted by the assembler, and if we were using the label in an -# exception table the table would no longer contain the address of the ll -# instruction. -# -# Avoid this by explicitly disabling that assembler behaviour. If upstream -# binutils does not merge support for the flag then we can revisit & remove -# this later - for now it ensures vendor toolchains don't cause problems. -# -cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) - -# Enable the workarounds for Loongson2f -ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS -cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop -cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump -endif - -# Some -march= flags enable MMI instructions, and GCC complains about that -# support being enabled alongside -msoft-float. Thus explicitly disable MMI. -cflags-y += $(call cc-option,-mno-loongson-mmi) - # # Loongson Machines' Support # diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform index 473404cae1c4..49c9889e3d56 100644 --- a/arch/mips/loongson64/Platform +++ b/arch/mips/loongson64/Platform @@ -1,19 +1,3 @@ -# -# Loongson Processors' Support -# - - -cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap - -ifdef CONFIG_CPU_LOONGSON64 -cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a -cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 -endif - -# Some -march= flags enable MMI instructions, and GCC complains about that -# support being enabled alongside -msoft-float. Thus explicitly disable MMI. -cflags-y += $(call cc-option,-mno-loongson-mmi) - # # Loongson Machines' Support # From patchwork Sat Mar 4 22:15:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB7DC6FA8E for ; Sat, 4 Mar 2023 22:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjCDWPr (ORCPT ); Sat, 4 Mar 2023 17:15:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229651AbjCDWPq (ORCPT ); Sat, 4 Mar 2023 17:15:46 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E602D12F22 for ; Sat, 4 Mar 2023 14:15:44 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 619875C0107; Sat, 4 Mar 2023 17:15:44 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Sat, 04 Mar 2023 17:15:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968144; x= 1678054544; bh=oPJUVCgvgXZ0DrEgbfMpQpqQI91RPNnYp6KBlIi3GfI=; b=J f9YRLCJdifRvRlpZcVK7ImFL9+dP6zv51kukpKcydjf9vY/6pms3EKahyYDZ7i5B DpdQpei588rNptw2y4+82aCglEByro6VLISZrJxHkb8Mfsj0lNOOKAbYKK04dsvU 0USsbWvixROpccfcf4/Cm2WA7pbSaKQR6nXYfYT//NNp/jaeQXM3pNkdX2xSCX+l /9sFv+qQ56IfhDRzGBD0CC4IdnikC5+/zGjkyIsvAAmfaGjm/GmkgP6Y2PDd2UcA QlYxyRLsOBP9nozO3i38PmXi0Jrcl8GyrqMapy3oP84pRytV9SKgSGR5eevK8C3U yrcA3KjQ6bv291BzVmFAg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968144; x= 1678054544; bh=oPJUVCgvgXZ0DrEgbfMpQpqQI91RPNnYp6KBlIi3GfI=; b=D 9MH5TKWZMpym6Zq787CLqDoLTqFCoQoxUZ1cIBflyj7TGHsJyX53QRXrKwaebSL3 uJAR4Zv3mQx8hUIndPgAZczLGS4v3TCPzgYDzgqRVV0qhADcSmGRfCxSccaXqr7+ EpsqtsJpjrrmQX+d/wX80KieMZ1YXJtoqTFSyKChVtNc0rHMIBejA/wgn+ZMPwgt DtwRK9ViZFCjYAcqsD6kMisly3v2Yal/uUCy+LkgqWmVDDghGpqlVZ2jB53pW+Io D7Gd4ueUHeEVDOeoURlCnOGp6qi6x2vtv3MnsXrrOMupI2oPF01TDmDs5C4ukbN8 lLXRko4YRrRY0HVpaS99Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:43 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 09/12] MIPS: Loongson: Don't select platform features with CPU Date: Sat, 4 Mar 2023 22:15:21 +0000 Message-Id: <20230304221524.47160-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org ARCH_HAS_PHYS_TO_DMA and GPIOLIB are all platform level features they shouldn't be selected with CPU. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 2 -- arch/mips/loongson2ef/Kconfig | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e2f3ca73f40d..940ade1c9449 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1366,7 +1366,6 @@ config CPU_LOONGSON2F bool "Loongson 2F" depends on SYS_HAS_CPU_LOONGSON2F select CPU_LOONGSON2EF - select GPIOLIB help The Loongson 2F processor implements the MIPS III instruction set with many extensions. @@ -1788,7 +1787,6 @@ config CPU_LOONGSON2EF select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES - select ARCH_HAS_PHYS_TO_DMA config CPU_LOONGSON32 bool diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig index 96dc6eba4310..f93eb6f42238 100644 --- a/arch/mips/loongson2ef/Kconfig +++ b/arch/mips/loongson2ef/Kconfig @@ -7,6 +7,7 @@ choice config LEMOTE_FULOONG2E bool "Lemote Fuloong(2e) mini-PC" select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_PHYS_TO_DMA select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select CEVT_R4K @@ -36,6 +37,7 @@ config LEMOTE_FULOONG2E config LEMOTE_MACH2F bool "Lemote Loongson 2F family machines" select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_PHYS_TO_DMA select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select BOARD_SCACHE @@ -46,6 +48,7 @@ config LEMOTE_MACH2F select CSRC_R4K if ! MIPS_EXTERNAL_TIMER select DMA_NONCOHERENT select GENERIC_ISA_DMA_SUPPORT_BROKEN + select GPIOLIB select FORCE_PCI select I8259 select IRQ_MIPS_CPU From patchwork Sat Mar 4 22:15:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B601C6FD18 for ; Sat, 4 Mar 2023 22:15:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229651AbjCDWPr (ORCPT ); Sat, 4 Mar 2023 17:15:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229655AbjCDWPr (ORCPT ); Sat, 4 Mar 2023 17:15:47 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E180199DC for ; Sat, 4 Mar 2023 14:15:46 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 765495C0103; Sat, 4 Mar 2023 17:15:45 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Sat, 04 Mar 2023 17:15:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968145; x= 1678054545; bh=sGJmLjd5JbRIkRrjcWhhoRa3Yyv3+p46+kg1LIGSDKE=; b=C mN1C8Ifk9MH+3x6fJNCDPBJNkbU7OQvZLWaNe/bJmiZtAWqcX2tYREQyaEs85dAr SGgGx0nSXpjcYFYHY81hwFC8vcXpnHB0ceVP8NJlPTOxz7E56BYkwC4f5bM3Ik9L lVECmjJY0regDUN2P+TNjopfc+qzwCEXK8PsKeoo8zYZGz/+Huhe26kUjxuaf4nX uJx/1WN+6NkVsbNLujYBL4/GkAWOzqQ771yudM/4kU2gwq0wgr25YuccwXvM3biu iZPjXpzX01n67EoznS41UpTywwNKRBuQxnYqdfJxM8vpDM4/VVTPiHam9akHHmgK XulI7XXeoPxV3fyNoBNiQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968145; x= 1678054545; bh=sGJmLjd5JbRIkRrjcWhhoRa3Yyv3+p46+kg1LIGSDKE=; b=m BIB7eYacRhx7qdYLa+lBy1A6QcEhIUk6NKLiwG9QiBgZF51FwWV2PW1ykOFOAfQb gCHS15T4SOQR+8VWmHoIcCzn6YNn78UMfLrpC0Jtc5aj+1OtPx0Ad7P5tQHcjjjE Aibu50YM1plbeo5NBIyaabeHhy6PU5GSOTLfGaLLSSzNkVCjmaIM4tjnzqC4IYdV cZM2rcB9DAyK+YMaM9hfWhG2u6OtkIZMGsBBquvmAKG8REc7iZKDeIzcVS6mxo4s wL2fHEfxEdfyHlqRjymM1qBQJ0hEQ0Usgx+6Y6KKTkWXCzV6ptwsJe5+79oqCzVK 8ESDfkHNB9Jwhb3x8QhkQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:44 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 10/12] MIPS: Octeon: Disable CVMSEG by default on other platforms Date: Sat, 4 Mar 2023 22:15:22 +0000 Message-Id: <20230304221524.47160-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org QEMU can't emulate CVMSEG on generic platform for now. Just disable it by default. Signed-off-by: Jiaxun Yang --- arch/mips/cavium-octeon/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index c1899f109e19..450e979ef5d9 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1 config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" range 0 54 - default 1 + default 0 if !CAVIUM_OCTEON_SOC + default 1 if CAVIUM_OCTEON_SOC help CVMSEG LM is a segment that accesses portions of the dcache as a local memory; the larger CVMSEG is, the smaller the cache is. From patchwork Sat Mar 4 22:15:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58CFAC678DB for ; Sat, 4 Mar 2023 22:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229659AbjCDWPs (ORCPT ); Sat, 4 Mar 2023 17:15:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229658AbjCDWPs (ORCPT ); Sat, 4 Mar 2023 17:15:48 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24C9512F22 for ; Sat, 4 Mar 2023 14:15:47 -0800 (PST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 8FC845C00A3; Sat, 4 Mar 2023 17:15:46 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Sat, 04 Mar 2023 17:15:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968146; x= 1678054546; bh=qGsv5yUkSW6MX9yok3pt0irLh7crnCuHDSfbz/DmeoQ=; b=g U0KwHeZmGe7DK6vEyBeFOPWbn7u4Ic50UI0Q2imeZoX5hu2gUHPXGt9O30gdedp5 qt0sxZLUPtIzaoBsu5WIxd9rURxtFTuWigP8o8TwX2l+dDc89GtrELQnWh0RLmEm UJ7aDdIAc+hlcNzSlLNyDK+nQXvm+osuA/c5NwGtdraMv6Zkv6zxClICYigJzv7V IurApDSzX77g0dH3poCoAi/prTQFpHRWieTfI7zQePoPZuwNMT9CRjcQfHr4PmtC YjCerII+DQGZDyaOXb0Rqwqn6/IWhwKtvVhqWe69CuBxHnQM0Q4KWBtyCMl8MMyT rfZd7ojNRRaTPqQlJh12g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968146; x= 1678054546; bh=qGsv5yUkSW6MX9yok3pt0irLh7crnCuHDSfbz/DmeoQ=; b=V LT2yJxyB3r+aInf9EZQnsittLTpr+YAQA2MFbh74DDMB5UArmsPov8StH1BMzS6Y /UrCqkm4YrEK+j544oWywvc4NivloU82Xfnc7DsTlCa2ZlK+QBfBjk5FWy2/k/4r 1iRoGtet1igm0wGn76IISwCuf3FRRJJ//CEF15e2UGGgI1AaRQgNKvFBomd4qHiZ 9FEvOBbbNZ+FHpuOjk14KCYxkw8FOxA7C/kYHUI/RDlDu2D5bicWLCAIKDfLYBpb y00UEt60Up2iZgORVG8T+zd6rziafsWQcF0y/11T/pbPSCDjMoMbp74M423AeVUA WB8TLZwO7IBi6Dg+NGjPQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:45 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 11/12] MIPS: Add board config for virt board Date: Sat, 4 Mar 2023 22:15:23 +0000 Message-Id: <20230304221524.47160-12-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Aligned with QEMU MIPS virt board. Signed-off-by: Jiaxun Yang --- arch/mips/configs/generic/board-virt.config | 38 +++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/mips/configs/generic/board-virt.config diff --git a/arch/mips/configs/generic/board-virt.config b/arch/mips/configs/generic/board-virt.config new file mode 100644 index 000000000000..5594f9e5c3a8 --- /dev/null +++ b/arch/mips/configs/generic/board-virt.config @@ -0,0 +1,38 @@ +CONFIG_COMMON_CLK=y + +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIC=y + +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_HOST_GENERIC=y + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_SYSCON_REBOOT_MODE=y + +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GOLDFISH=y + +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y + +CONFIG_MTD=y +CONFIG_MTD_CFI=y + +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_XHCI_HCD=y + +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_NET=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y From patchwork Sat Mar 4 22:15:24 2023 Content-Type: text/plain; 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Sat, 4 Mar 2023 17:15:46 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 12/12] MIPS: generic: Enable all CPUs supported by virt board in Kconfig Date: Sat, 4 Mar 2023 22:15:24 +0000 Message-Id: <20230304221524.47160-13-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Enable extra CPUs that may be supported by virt board, including R4x00 (R4000 in QEMU), Cavium Octeon (Octeon68XX in QEMU), loongson2e, loongson2f. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 940ade1c9449..53160d49387c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -155,12 +155,16 @@ config MIPS_GENERIC_KERNEL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE + select SYS_HAS_CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_LOONGSON2E + select SYS_HAS_CPU_LOONGSON2F select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_MIPS64_R6 + select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN