From patchwork Mon Mar 6 14:13:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E4EC6FA99 for ; Mon, 6 Mar 2023 14:14:38 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id B7B406B0072; Mon, 6 Mar 2023 09:14:37 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id B04AE280002; Mon, 6 Mar 2023 09:14:37 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 9F394280001; Mon, 6 Mar 2023 09:14:37 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 8F3F16B0072 for ; Mon, 6 Mar 2023 09:14:37 -0500 (EST) Received: from smtpin07.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 522E51C5EA7 for ; Mon, 6 Mar 2023 14:14:37 +0000 (UTC) X-FDA: 80538668994.07.F0A7121 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf03.hostedemail.com (Postfix) with ESMTP id 1E6E62000B for ; Mon, 6 Mar 2023 14:14:34 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="cfd/g0uP"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112075; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=uCwHynmI1Y/rCia0sOr4mdTqPBCpXkwR6NoZUQjizGs=; b=lk6Am/xYzsZKbEoYZqB0qxmJghNLJbXKNZuXIRh+Xt5T2B5R1ynj11e4Wm8KjT5ViR9P+7 z+3g41eJ2RL7ZYGwIcdWAKMvXOphiBaCokxetwwxU1PguZoNOx+PnarM3NDgA8n4C8+4Bm /Y9xAwLrdj81JG5yKeYhEd+GsZ/0rAI= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="cfd/g0uP"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112075; a=rsa-sha256; cv=none; b=OiXh6mYyvSdZbonOKwOiqqxy9Vsl6Hzoyh6c16H9dZILgqf3XqNCebN/Ozr5KJYwFlFaCL hBAWLt+n9N9VBCuzxCcll4yCKFEV6s4SCRDHTSV5gxVAazqh8A5SbAIUs/Ep8v12/tIR19 QVy9Bct1i9I0/uOV18MTflzAhTtJzOc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112075; x=1709648075; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VqcKARLycsk9x9FHwX2Ecm9BMNr+EPyvV4YYN1oDJ30=; b=cfd/g0uPStyqSwUnoQElLGCX2Y/kA8hEgFqIMGBs/+B3r1ZZLUDwbV98 FSxPm5mk/xcMH8qh74jidICVGwmPASAqgpkK/E2yf+zostktzH5VUFtmR Vm3Gr+xHakNF1+7srUVENofB2+SydG3FsbVGuw1bpRv2opQze68mouQOa Ee00mLKWZ4dG1ymqaUVc+/0FTfIMTcZkPOb2f0Sts/ocJBw2/dd2CHY3p sMrP57iABRolrBZDPhsD0zIfytyth/oKvktD8zN/23MomYaVDuQhvMgAC GBuTBWgPken6+o29chKC8iSKyxh8OvXwK6UD8T6un6dSjfLnSSeddpIBQ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337079981" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337079981" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765231976" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765231976" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:29 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 01/16] x86/tdx: Define TDX supported page sizes as macros Date: Tue, 7 Mar 2023 03:13:46 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 1E6E62000B X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: fjaynt94yija64nx5dqxcxjwztry6ez4 X-HE-Tag: 1678112074-147370 X-HE-Meta: U2FsdGVkX1/l+ozPfzMZm1SAJmhepM8naFcvRBmGIXkWkdbLbwmYFLC5Tu67G6y1gO64H69YaagBkHhIEo7WXSjnkRh0zt7JSdr6oR/t1fsoVraSd02ldSBG/eEKSq7s1CUDAOUZ31XLKFUnd0OqTkaFvyel5LhGve0TGGkDSh8Iv943YNM5XxHVUwTvT272qNneLbh0joRyidyVFfIUa7eeP/BRZyTZWXlj+e2hjLvFN+9HqseUW9TiM6eto9UJZf8mAQRLR0MpRE71WaBPgepSLkl3TorX/KJv4WVDcucSiFYrZm5zUO4LZee394aGHTh9NSGFDs59zLrmUY2NWB4nzsF7QawkrITTF7sMtzwxpyTpYX92kXCBJGAlbKjocUi45/sDnRXQipXh5TcuGtEH/YB2p3mTRAvVGtUC/GTNB3s7OgXlSARsU+LtE4ho+76DXXYhFgRTyZPfXvAE8fJX5kKhM9boVUd/8NY3QNf6/+T2H+KLoIUb2vPUQVZ2QMMYdgEFufDqbFdWXEeMDnxf1S9uBC1oo9tTb6egBPqQJaghtxTw7IgsM3ZRnrQ+X8YgGx0VPuTwBn3cyY14XXvCh/cYejdt52MReQT29LTNgF/Vgnj60wCTjFdsho3QjqeCnucYxC315xeLkCB2Ggu21buyXbjkjOwM+IZRUhYmSoy3yRT9MhQJX+1pmL2wFJT5K/rlgkf8j0AoKeQu9Q4RGXLmHmr4CT/j7lpAc8CFticc5SxxuP90/v6E9JSGygo0kJNRuL21/PGZWQSIjqHy19pjy5+YBa8jCjl6jtp53VaallKuPkGsRlFHL7LFfqhuxW0UUmr8scnRJ75m5jCLJrHtwz8FGu9lEI+mhng9thvkz9DoWqiYP0l6HfeoM+0mAfBAUmP+dgvct5xIUMnP59NOF2iqmBxLWTNW004u4Bq4JFYZ+66WL3sOIAGMPiYCZnDqwzMgaq6tO7O dnCHbDBV iiN3g9imlpw1TD6UkDfl1nA+CaaWvrxp/OrEzDaGUp0CwkKowVX1PZYwdXHAYwrKmGjr+MHgDdC/BryAyBydxq30o052KXWoLYO7MWbUA9GoFYR4Jrkviy90SrOWHMzcMGo5/Gw7cfUPA1Fy8PNdNyLjY9z2UTSZX7rVB7MJxVAGVYIUGwQ67bJ/KZBC6IDG7TzC/Q5YTWcfTZlBlx6DZWDG6pA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: TDX supports 4K, 2M and 1G page sizes. The corresponding values are defined by the TDX module spec and used as TDX module ABI. Currently, they are used in try_accept_one() when the TDX guest tries to accept a page. However currently try_accept_one() uses hard-coded magic values. Define TDX supported page sizes as macros and get rid of the hard-coded values in try_accept_one(). TDX host support will need to use them too. Signed-off-by: Kai Huang Reviewed-by: Kirill A. Shutemov Reviewed-by: Dave Hansen Reviewed-by: David Hildenbrand --- v9 -> v10: - No change. v8 -> v9: - Added Dave's Reviewed-by v7 -> v8: - Improved the comment of TDX supported page sizes macros (Dave) v6 -> v7: - Removed the helper to convert kernel page level to TDX page level. - Changed to use macro to define TDX supported page sizes. --- arch/x86/coco/tdx/tdx.c | 6 +++--- arch/x86/include/asm/tdx.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index b593009b30ab..e27c3cd97fcb 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -777,13 +777,13 @@ static bool try_accept_one(phys_addr_t *start, unsigned long len, */ switch (pg_level) { case PG_LEVEL_4K: - page_size = 0; + page_size = TDX_PS_4K; break; case PG_LEVEL_2M: - page_size = 1; + page_size = TDX_PS_2M; break; case PG_LEVEL_1G: - page_size = 2; + page_size = TDX_PS_1G; break; default: return false; diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 28d889c9aa16..25fd6070dc0b 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -20,6 +20,11 @@ #ifndef __ASSEMBLY__ +/* TDX supported page sizes from the TDX module ABI. */ +#define TDX_PS_4K 0 +#define TDX_PS_2M 1 +#define TDX_PS_1G 2 + /* * Used to gather the output registers values of the TDCALL and SEAMCALL * instructions when requesting services from the TDX module. From patchwork Mon Mar 6 14:13:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0C5EC61DA4 for ; Mon, 6 Mar 2023 14:14:42 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 671E26B0073; Mon, 6 Mar 2023 09:14:42 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 622A9280002; Mon, 6 Mar 2023 09:14:42 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 4C398280001; Mon, 6 Mar 2023 09:14:42 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 3C35C6B0073 for ; Mon, 6 Mar 2023 09:14:42 -0500 (EST) Received: from smtpin11.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 0E39B14043E for ; Mon, 6 Mar 2023 14:14:42 +0000 (UTC) X-FDA: 80538669204.11.6015F61 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf03.hostedemail.com (Postfix) with ESMTP id DC34A2000B for ; Mon, 6 Mar 2023 14:14:39 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=XCmVtalQ; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112080; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=vFnKjnW2TAIoTuGWc5ZCUtdQVts2h4dgavA5fZAr0lE=; b=W3tXRqODR/OLkfKDXsfIOOU1+S6ytcrcMctUh9hHKz66NUTJ76mpD2fA64ZUkC1YQLBrEx KOWAvjqVnFba+/4i47uX+ROUsKHdY08q7qQ24pdDZSfKGisFhtjjuWNpqnSy+stgv39zno qkvwa5ls3HJ41WK2GskkkNPeOaWmbaU= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=XCmVtalQ; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112080; a=rsa-sha256; cv=none; b=WhTBts7AlJyaG4NQRoFXuEYptEkpSWitXTUqz8M8PQU45GzOiMHgwSvNKqXTflC3ErU6M1 nY7NBmp+cPTLDhkyMr49/nc9EN574XBU2UuaMT/C/6N4n0UCAUexAApok+BtAMfalz5g99 B6GLJpLAHke5ENOIamtPJQcRAr1UnP4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112080; x=1709648080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E/xESLm6AuJmJjZ1XaxBdqGbrkk49BYxt+tFKArhrw4=; b=XCmVtalQPWrvo64Q/4DGnU6MMHJRPwZm+zJAL3k2E0a7+tmbVWwcNx96 ke0zHRA3UYMcut4f6aNEPNUzosNpWNLaBVcZJbyB82vbMyigTRITNiZKh 49gewf1BVrrAOdYmdYctECXFGHJwZyIr0g578EQgjj35lBe35d3KrDP40 aNghPyInEqb/wa1owJA8+QZ3QvMRG+fQu7n10jQZvsI+oVRFff6BG8+cq /EvjpRYBqvpfWi1BYyDuc9oay4d9osTbURjsps90woEnMPPEmd+TGuBM3 gNBu/pXqb04wRMrLLOL4e46DEuNjL33zgtkh/dfXcrKTnxZRiNEtu4b6q Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080009" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080009" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232021" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232021" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:34 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 02/16] x86/virt/tdx: Detect TDX during kernel boot Date: Tue, 7 Mar 2023 03:13:47 +1300 Message-Id: <35a2421ca97d9e8dd938dcd744674602f4faa617.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: DC34A2000B X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: hgiw6qmh1p3g5ftiqnq4um4yfun14qhn X-HE-Tag: 1678112079-236556 X-HE-Meta: U2FsdGVkX19oPe+umVQiy8YaUHqKVKgtqvmyyABL/Vyxw04dhFhJwnVbtbOobaJkGS7lDr82NUNO85cs8HzzwTnyXj14uUMnYBCi2fGTrTqvWVPpd1kerImo1wlzHPxw83Ye1mSbspHCHIIJOhheni796VEF3o4oYquT51phtDBGanSbLtA1arps/fl6sllyqnKZQKejLfnk4T1IB/xp9x3MwLNF1oZ8KLjyptXS3xGQweVo4yKgWtjdVkMS/k0fuM0uFtUvibCpeEnIvIhmW+E4h8BzGOFIXuxaX+FsU6SzhODiht19bOcppxFWHe69OmRmMzv1ZrkNFp/s/CcNAjHz1FhTRHiLAafbVmIbXPIwAmGLTDwqOvbshqBuNZ4XJxfND2YE7AcFBT+kh6E6XXHWqS2na/9vmnblvSuNOtuxiMbyGIWHANYAZfx+IcGcx44vgXNfNI+l0fNWVHkyFSy8+wc160kR6TmiZAje0V7ogMew5hmx82u40U22yYfvcLFKjYajfu/5FFQjR5wCqY99tadQR4UWZ2atXF6rGyLjW9AUDzB2A5q59zjZDTQiFMPPl3CsNJ3J1zKhDFxrK4StxhjUvOK7QqJqKnPKYWAP3a7TJ0ncPP7ZIqySlBt59rslYs0RQuexL1mQyMZhBnem8FXl9sfYBL0P5z1giz9SvTDdoxSkxiOMctmtokPV5tShyV7+UHQo2t9iWzmgd/6l6fXiBf2tZHIVeDEzABnvOIKLbthlSD37a4D7ys/ZT1Emi/BLcGDICVSOUQHZGEPKVPiTORg+5VjAuqd5C6SQEvC6aWTIgMdxHFLlslHa965bK4nQ3C/xrQFflAPX1Ga6i676ymuyFJXXhGjnsxrnGoG2FBjRP4/93xr6MNq/EjSyaAMt3hCMDqn0n56BMOoLLk0MI1d1Gpwo01ETD0/9N25NLxWpye8+yMDdhNC+11fV7al5qiDrugOAt1K 3OrQf/1E qWqcDgx+LoQ0DWMCn+UZIqmxzNhdJf+9bJXedI13ziAmW5NLamD+1oKpzmA2sF4n/aN0pGMyEQED0/hDnGl7eAjkDMCDpbuOnTusx1nr0Sr0JQLzq2Gm1tzbyqSlZEqn1guhKlYzsGDMIdE7dJ2kmYbH2D/lWDvTFmYuKhjMQ45olCIg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Intel Trust Domain Extensions (TDX) protects guest VMs from malicious host and certain physical attacks. A CPU-attested software module called 'the TDX module' runs inside a new isolated memory range as a trusted hypervisor to manage and run protected VMs. Pre-TDX Intel hardware has support for a memory encryption architecture called MKTME. The memory encryption hardware underpinning MKTME is also used for Intel TDX. TDX ends up "stealing" some of the physical address space from the MKTME architecture for crypto-protection to VMs. The BIOS is responsible for partitioning the "KeyID" space between legacy MKTME and TDX. The KeyIDs reserved for TDX are called 'TDX private KeyIDs' or 'TDX KeyIDs' for short. TDX doesn't trust the BIOS. During machine boot, TDX verifies the TDX private KeyIDs are consistently and correctly programmed by the BIOS across all CPU packages before it enables TDX on any CPU core. A valid TDX private KeyID range on BSP indicates TDX has been enabled by the BIOS, otherwise the BIOS is buggy. The TDX module is expected to be loaded by the BIOS when it enables TDX, but the kernel needs to properly initialize it before it can be used to create and run any TDX guests. The TDX module will be initialized by the KVM subsystem when KVM wants to use TDX. Add a new early_initcall(tdx_init) to detect the TDX by detecting TDX private KeyIDs. Also add a function to report whether TDX is enabled by the BIOS. Similar to AMD SME, kexec() will use it to determine whether cache flush is needed. The TDX module itself requires one TDX KeyID as the 'TDX global KeyID' to protect its metadata. Each TDX guest also needs a TDX KeyID for its own protection. Just use the first TDX KeyID as the global KeyID and leave the rest for TDX guests. If no TDX KeyID is left for TDX guests, disable TDX as initializing the TDX module alone is useless. To start to support TDX, create a new arch/x86/virt/vmx/tdx/tdx.c for TDX host kernel support. Add a new Kconfig option CONFIG_INTEL_TDX_HOST to opt-in TDX host kernel support (to distinguish with TDX guest kernel support). So far only KVM uses TDX. Make the new config option depend on KVM_INTEL. Signed-off-by: Kai Huang Reviewed-by: Kirill A. Shutemov --- v9 -> v10: - No change. v8 -> v9: - Moved MSR macro from local tdx.h to (Dave). - Moved reserving the TDX global KeyID from later patch to here. - Changed 'tdx_keyid_start' and 'nr_tdx_keyids' to 'tdx_guest_keyid_start' and 'tdx_nr_guest_keyids' to represent KeyIDs can be used by guest. (Dave) - Slight changelog update according to above changes. v7 -> v8: (address Dave's comments) - Improved changelog: - "KVM user" -> "The TDX module will be initialized by KVM when ..." - Changed "tdx_int" part to "Just say what this patch is doing" - Fixed the last sentence of "kexec()" paragraph - detect_tdx() -> record_keyid_partitioning() - Improved how to calculate tdx_keyid_start. - tdx_keyid_num -> nr_tdx_keyids. - Improved dmesg printing. - Add comment to clear_tdx(). v6 -> v7: - No change. v5 -> v6: - Removed SEAMRR detection to make code simpler. - Removed the 'default N' in the KVM_TDX_HOST Kconfig (Kirill). - Changed to use 'obj-y' in arch/x86/virt/vmx/tdx/Makefile (Kirill). --- arch/x86/Kconfig | 12 ++++ arch/x86/Makefile | 2 + arch/x86/include/asm/msr-index.h | 3 + arch/x86/include/asm/tdx.h | 7 +++ arch/x86/virt/Makefile | 2 + arch/x86/virt/vmx/Makefile | 2 + arch/x86/virt/vmx/tdx/Makefile | 2 + arch/x86/virt/vmx/tdx/tdx.c | 105 +++++++++++++++++++++++++++++++ 8 files changed, 135 insertions(+) create mode 100644 arch/x86/virt/Makefile create mode 100644 arch/x86/virt/vmx/Makefile create mode 100644 arch/x86/virt/vmx/tdx/Makefile create mode 100644 arch/x86/virt/vmx/tdx/tdx.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3604074a878b..fc010973a6ff 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1952,6 +1952,18 @@ config X86_SGX If unsure, say N. +config INTEL_TDX_HOST + bool "Intel Trust Domain Extensions (TDX) host support" + depends on CPU_SUP_INTEL + depends on X86_64 + depends on KVM_INTEL + help + Intel Trust Domain Extensions (TDX) protects guest VMs from malicious + host and certain physical attacks. This option enables necessary TDX + support in host kernel to run protected VMs. + + If unsure, say N. + config EFI bool "EFI runtime service support" depends on ACPI diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 9cf07322875a..972b5a64ce38 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -252,6 +252,8 @@ archheaders: libs-y += arch/x86/lib/ +core-y += arch/x86/virt/ + # drivers-y are linked after core-y drivers-$(CONFIG_MATH_EMULATION) += arch/x86/math-emu/ drivers-$(CONFIG_PCI) += arch/x86/pci/ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 37ff47552bcb..952374ddb167 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -512,6 +512,9 @@ #define MSR_RELOAD_PMC0 0x000014c1 #define MSR_RELOAD_FIXED_CTR0 0x00001309 +/* KeyID partitioning between MKTME and TDX */ +#define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087 + /* * AMD64 MSRs. Not complete. See the architecture manual for a more * complete list. diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 25fd6070dc0b..4dfe2e794411 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -94,5 +94,12 @@ static inline long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, return -ENODEV; } #endif /* CONFIG_INTEL_TDX_GUEST && CONFIG_KVM_GUEST */ + +#ifdef CONFIG_INTEL_TDX_HOST +bool platform_tdx_enabled(void); +#else /* !CONFIG_INTEL_TDX_HOST */ +static inline bool platform_tdx_enabled(void) { return false; } +#endif /* CONFIG_INTEL_TDX_HOST */ + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_TDX_H */ diff --git a/arch/x86/virt/Makefile b/arch/x86/virt/Makefile new file mode 100644 index 000000000000..1e36502cd738 --- /dev/null +++ b/arch/x86/virt/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += vmx/ diff --git a/arch/x86/virt/vmx/Makefile b/arch/x86/virt/vmx/Makefile new file mode 100644 index 000000000000..feebda21d793 --- /dev/null +++ b/arch/x86/virt/vmx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_INTEL_TDX_HOST) += tdx/ diff --git a/arch/x86/virt/vmx/tdx/Makefile b/arch/x86/virt/vmx/tdx/Makefile new file mode 100644 index 000000000000..93ca8b73e1f1 --- /dev/null +++ b/arch/x86/virt/vmx/tdx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += tdx.o diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c new file mode 100644 index 000000000000..a600b5d0879d --- /dev/null +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2023 Intel Corporation. + * + * Intel Trusted Domain Extensions (TDX) support + */ + +#define pr_fmt(fmt) "tdx: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +static u32 tdx_global_keyid __ro_after_init; +static u32 tdx_guest_keyid_start __ro_after_init; +static u32 tdx_nr_guest_keyids __ro_after_init; + +/* + * Use tdx_global_keyid to indicate that TDX is uninitialized. + * This is used in TDX initialization error paths to take it from + * initialized -> uninitialized. + */ +static void __init clear_tdx(void) +{ + tdx_global_keyid = 0; +} + +static int __init record_keyid_partitioning(u32 *tdx_keyid_start, + u32 *nr_tdx_keyids) +{ + u32 _nr_mktme_keyids, _tdx_keyid_start, _nr_tdx_keyids; + int ret; + + /* + * IA32_MKTME_KEYID_PARTIONING: + * Bit [31:0]: Number of MKTME KeyIDs. + * Bit [63:32]: Number of TDX private KeyIDs. + */ + ret = rdmsr_safe(MSR_IA32_MKTME_KEYID_PARTITIONING, &_nr_mktme_keyids, + &_nr_tdx_keyids); + if (ret) + return -ENODEV; + + if (!_nr_tdx_keyids) + return -ENODEV; + + /* TDX KeyIDs start after the last MKTME KeyID. */ + _tdx_keyid_start = _nr_mktme_keyids + 1; + + *tdx_keyid_start = _tdx_keyid_start; + *nr_tdx_keyids = _nr_tdx_keyids; + + return 0; +} + +static int __init tdx_init(void) +{ + u32 tdx_keyid_start, nr_tdx_keyids; + int err; + + err = record_keyid_partitioning(&tdx_keyid_start, &nr_tdx_keyids); + if (err) + return err; + + pr_info("BIOS enabled: private KeyID range [%u, %u)\n", + tdx_keyid_start, tdx_keyid_start + nr_tdx_keyids); + + /* + * The TDX module itself requires one 'TDX global KeyID' to + * protect its metadata. Just use the first one. + */ + tdx_global_keyid = tdx_keyid_start; + tdx_keyid_start++; + nr_tdx_keyids--; + + /* + * If there's no more TDX KeyID left, KVM won't be able to run + * any TDX guest. Disable TDX in this case as initializing the + * TDX module alone is meaningless. + */ + if (!nr_tdx_keyids) { + pr_info("initialization failed: too few private KeyIDs available.\n"); + goto no_tdx; + } + + tdx_guest_keyid_start = tdx_keyid_start; + tdx_nr_guest_keyids = nr_tdx_keyids; + + return 0; +no_tdx: + clear_tdx(); + return -ENODEV; +} +early_initcall(tdx_init); + +/* Return whether the BIOS has enabled TDX */ +bool platform_tdx_enabled(void) +{ + return !!tdx_global_keyid; +} From patchwork Mon Mar 6 14:13:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B91FC678D4 for ; Mon, 6 Mar 2023 14:14:47 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id D9D636B0074; Mon, 6 Mar 2023 09:14:46 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id D4E79280002; Mon, 6 Mar 2023 09:14:46 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id C171E280001; Mon, 6 Mar 2023 09:14:46 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id AF57D6B0074 for ; Mon, 6 Mar 2023 09:14:46 -0500 (EST) Received: from smtpin15.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id 8AECDA0841 for ; Mon, 6 Mar 2023 14:14:46 +0000 (UTC) X-FDA: 80538669372.15.E846750 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf03.hostedemail.com (Postfix) with ESMTP id 7A5B420011 for ; Mon, 6 Mar 2023 14:14:44 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=WksUwEYi; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112084; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=+kA5rux/hcpfTk1ED8pntVzX5z1xt2ZD6grLDsv18ko=; b=cCJ7rb6F3J81VOudedHEShCbZLvJ7RWyGBFDrVXNHrZiN0hBDGGGGd5dqUoihIDG5u0K79 XyhtBLXO0bI4pq6VbEVzHmJDPiS4aryJx6aN7oiJi+Bx41yMlMC1SsLVKm4APGBLl/gENZ jctflyH76ks2h2c+iiAulDYokW8HyuE= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=WksUwEYi; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf03.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112084; a=rsa-sha256; cv=none; b=kiW9cocauAUkrCq7+ZjzTWQCkMk8jXjpRd8VG3+CohwTf9JjA05QTFqxngh62EtsYTLTa1 ms3uwFUQZNf9qrohujodeb56yRZRemAfBOxXPVibtwC9j8wfT7PO+/zs3cgWdZrAM29lUt Z/0ZMLgBOYtGA77KT8Y+8CxhJ3RmWVg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112084; x=1709648084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dSuzXAdQmayBHAPr3LIj7u4EPJ2EUXayNvd7wuACrRk=; b=WksUwEYi6iKPWV+qtXVvlDsSzoDBnmGg7F63jHKOkkSbRO/FE8afdVPS aWSON6qj6VLU0fAZNKbKl4fszwlyLtWUdXyKBnolpHbzcCkXlDYjL0m3c 8HTteZPONLzuqG61YX91ymgq0Ji2zmTguSIRT3xf/qWEx4wp9r1ZkaT5M qnHWy1cKVJghYhQBJFnpJdfqYShTk7UTvpHvbhmJE6VswEu53CQKeR53D MPvm+M+lLE/UgF7ehzgy/jjvPF5Wu0KHfgbL1jinbnBDH7bO04j+KfDpr i88rWPaHY6aaERdqB48bZJDI1TEx4LUHYfmNRvR6fxQf80wcUQjdE0qCM w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080035" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080035" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232059" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232059" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:39 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 03/16] x86/virt/tdx: Make INTEL_TDX_HOST depend on X86_X2APIC Date: Tue, 7 Mar 2023 03:13:48 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 7A5B420011 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 7wojigyanr8yozjqsrpt4ujem5t1k9we X-HE-Tag: 1678112084-449252 X-HE-Meta: U2FsdGVkX199tPZmsWllPlrZIW4P9+uVOUfVTQ4HS46D42gvzptN6MJFpfG3HlYE8CmUPoXZPBRE0Km5Vquk5v3D+v9CBggo+H2a6l98kAAGhP4cEGT1PMPvmiseRpJVGtjj7hStvYRvvC8nhqEYCRGAzUqZXXXMXESH1XFqf9r8wmQr7VAU7DpA3YS1db9IrWZ3QNjXuMoKV4mDHBgC+Re9kJ0GdAg+TVq/BJ8QzMOR6UEn5Dcp++IYIGzB8SkBaPfusp2+/dpO7q0/x+VBDYHgp+hG8TURg5Pu4NciKu5TOMy1Nk3XVF0U7k+nxHUlYp06VxRolHVC0eEUQqINywRHjpsVG946IhMLcR3HD+imWR5igYB+4xT7Wqecd43KV1sxmCHQvIJ59QMiGudhJDoj5mpDQEnsVO7wCZ5SivFolQ4WLqKiw/a9RHtmAgbxqEIvKXHw77xGzi7bI9xL9xIBMP404Wnb2u4RygumGvzgRHIssBR7wht7u8I7RtcFhca1qqFK7rt9gAmT8JnlkL9mbkNqPTyKPsXyBUGRHu6U+DlTo3xG0kmNI0xGAyY5wU0hFZjAKLLoZNxbj9g2SZ23B5VUAp4uCDCfCD1NWw3HCzPaKdWQnVfeT3h8SD9Yjslu4VS4nOG6DIyzg6yQiCWi6aKtX5yzBnI8AG6i5//9MAkS5ui7+oIMqjDqK46GdD2XGC6IPNWRhB3hHLnU1uqQD5PsU90n7tUsH/P1+c9BfDt6XWzjkBODhikYB90NZchHWYpHHOm70pGTdOT6F4miESwADPMLznsMS3wDw9jA1rVjHlPKgQg2107zVCuM+BMVEBf25qyCqap9cB1SLTi4L9RM47AbGXhjCmXnDAsAgYqDf9i7EK+miJigCcyLKy8T9pTygWcWHlxxD1FL0DISbpVa5VId7SL2HYcUR+zHwwFwf7FRzYKjWtgbrBdYpsrsT6MtEDXPUG5C/3i PUZskDzp ojSyY2T/WtdX0qu936IZg17xe2pj6AAt5mSiOqbtIpiMyADxG3ysBqBmwuT541Q+QMSG5De1k8CH5Lbdn3dX0/wcYHIRFQr6Amfbve3Wd8o5hBlytfV3HhFRK7ffDkLYCEoHX9uWQL4DuxqdwhoLk7KWZyApUcfgKJ9c7nh8XGnGsd4fpTfWQAJYsJ6mF0o4iTNtAQglOVK4cNx2ooR5BItDQmzGlNtgYLw2hqf6kCsZGuC71RZG7j7a8xbzxPQ1XGSVAoEEGmXAYrlyhmAtT+H3HJQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: TDX capable platforms are locked to X2APIC mode and cannot fall back to the legacy xAPIC mode when TDX is enabled by the BIOS. TDX host support requires x2APIC. Make INTEL_TDX_HOST depend on X86_X2APIC. Link: https://lore.kernel.org/lkml/ba80b303-31bf-d44a-b05d-5c0f83038798@intel.com/ Signed-off-by: Kai Huang Reviewed-by: Dave Hansen Reviewed-by: David Hildenbrand --- v9 -> v10: - No change. v8 -> v9: - Added Dave's Reviewed-by. v7 -> v8: (Dave) - Only make INTEL_TDX_HOST depend on X86_X2APIC but removed other code - Rewrote the changelog. v6 -> v7: - Changed to use "Link" for the two lore links to get rid of checkpatch warning. --- arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fc010973a6ff..6dd5d5586099 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1957,6 +1957,7 @@ config INTEL_TDX_HOST depends on CPU_SUP_INTEL depends on X86_64 depends on KVM_INTEL + depends on X86_X2APIC help Intel Trust Domain Extensions (TDX) protects guest VMs from malicious host and certain physical attacks. This option enables necessary TDX From patchwork Mon Mar 6 14:13:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0284C61DA4 for ; Mon, 6 Mar 2023 14:14:55 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 6E67A280001; Mon, 6 Mar 2023 09:14:55 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 6977F6B0078; Mon, 6 Mar 2023 09:14:55 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 510CD280001; Mon, 6 Mar 2023 09:14:55 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 3FC2B6B0078 for ; Mon, 6 Mar 2023 09:14:55 -0500 (EST) Received: from smtpin05.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 1D53E1406CD for ; Mon, 6 Mar 2023 14:14:55 +0000 (UTC) X-FDA: 80538669750.05.759C9AC Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id EEBDA100016 for ; Mon, 6 Mar 2023 14:14:52 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=CtCDTLt2; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112093; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=lMpQL9Pn7QGaCpJF+67zcagiAhtLviJx+/louquqMGk=; b=l3owItqUevEp+hXOgP5DvvhnChpLjDGnxsN4M4QkLShoQLR1MHLo3uoFdweN2d28Ltf9w8 Ahlw6cUmNZ41twQfRTkpl4W5ig2VaXZpSKEbrL2gUA8h2Lq/99HkJgMdGH4pLZDig1NPm0 H5Fwep/WbM0j02Kivyz1fFG3WJhW4lg= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=CtCDTLt2; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112093; a=rsa-sha256; cv=none; b=3c6pr8ki9G6bMe+roX/LSG93cFBMjp8KjSnqdustZKxkExIJMXMAXeDq6io6edG0+dEq4v JwHM62IhQacxmsp+tjMuhAfk5i7EANxb6Vt6OH2wwcqFIHIZFxMeRN1scVfy2UWrGvxU1P Z15IlPxjuoUSKYGLHMGmf5vey8ihdZo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112093; x=1709648093; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uMLzOji59KFUFjV3UhCeXK4DQopRTel++Injo387Ruk=; b=CtCDTLt2wXkJ8tUFLWY/wKg/tSMxsndqxLHEzhmInaepsOTUTNbQgOBM SNUkOuy/P7YVQRM55WlVXTXG3ig8E5zdTdOoOM6oXVmYvUPivuYNrpdhT X5uwc0QPsKThkHbPsSsq58DH0BCRio+fUrqUzblfMi4urlVReSZ5poY0E 6wDLpORmRX3h9tgnUd5RuQuI09b6WfSOCXah1el981AXAuyKunljYya8p ZZLNr93ZLh+NVrI8N9k7MxSbLJ0tJZKfj71sCSXzxUdZfX3AojXxx49xF K1SDu+oswP6S+CmLBldq5iU2s2Ts8OSy1BEQGZ9mikIUSd+Nz9G+M4V37 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080074" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080074" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232089" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232089" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:44 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 04/16] x86/virt/tdx: Add SEAMCALL infrastructure Date: Tue, 7 Mar 2023 03:13:49 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: EEBDA100016 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: h9j1h4fggwnyfcbciastju88xmor6ono X-HE-Tag: 1678112092-676916 X-HE-Meta: U2FsdGVkX1+tQinrZ7t2DUPERXODzp6CnlMmg2O7NzjLX2JzYuZZDsidSXBVLmHcniMFOezXo3IPy3XUilWs9wxMDzpULbxR2MDmCz42qfAW/ML5uf2ehz8Y8ruDGLyfvHRg2Bz34kEWj1jMD0fixeDOpdTmi8lCALxdb0Hwa3ZCUMr7KHX54xFks73Z19/l7C6ykAiFyy2DyYf5YtBsOXh/bHB1gWZTP5hwSzr4/k5mOk92iCgfgue9RW2JP4g/CoMHV8pkbZu9FIsYYrKiXV+zRGsSMHAN1xV5eHRLOXGxi8mQGIBB4/obKiGVmuIE0E9EhM7Mo5l4I1ZoZoJeaGHxtVhzyWRiNLTGvqWDdbEwqIAAnTC8D1SmY3Kaq9o0xceVotCNh7ficPzrZZ6sDBIY5drpi2lsybvfQy0Cm4mADPGYU1UagY2ZdSApxRPbYNzxQM0fTZcPBX2Cmj94uul1ca4TtQjaaNnHMe41B7Ju6sXd3kdotv6uI7emr+mXf7Hq3zPLrKBBHVvvs0QBkIXIrP5tFqyUDyuDClLuCBy3H4q+DmbgYe+kZeRlxWiVzivYP4ylqVas2DW21zXzLM40PxYyOmGptWpg4wnE4I9oLID9iHiy4O3MJ/1ulhceCwzfxSd+EXH/1RdDmL05WBc9YgOPxkIjx+k3jv8UZUmxpHlVEjwbV7dsQXa7DLsW65TLX7OruToaXF2lOvPEVgTQaIQ2KsFldUgNW39SZBUpDxofOTmvISj4j4QeVap9Lj0OcDu5uLtjHX4ftoevlCqcftfAjtWub+2uENFpJC8Ox2fiA9JyBqshGc4Mbyv/iKFs3EH0L4QCigjUQMMU6LrU2yA0UCjkeVLzKBuRo1Z6OP8KbM+R/RNuaCpBKqBhV0mEkQVrA+0fxeIvKTp32B0iUtva/xRNycVdLHjz8zW7cawz2MJzKCfwet4zPGJiZpefJ4lmZZjO8li9yBq iij5I2ja byew8nysrQQdlKU15aIUZ0l3HI2oG8ESoZ1LfOXoY6rhphwvKS3dhnLiM0iRkG7YcqeF3G+1MRM1REInqELqiZV2ac7RsDNfTTc2v9F63hwJqk0d/TkF2amGOigVj2UEseWQIprBsmhk1dJLxgNzjmEuwMB9Tqz/Wa4irVwEO6af5Yzw= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: TDX introduces a new CPU mode: Secure Arbitration Mode (SEAM). This mode runs only the TDX module itself or other code to load the TDX module. The host kernel communicates with SEAM software via a new SEAMCALL instruction. This is conceptually similar to a guest->host hypercall, except it is made from the host to SEAM software instead. The TDX module establishes a new SEAMCALL ABI which allows the host to initialize the module and to manage VMs. Add infrastructure to make SEAMCALLs. The SEAMCALL ABI is very similar to the TDCALL ABI and leverages much TDCALL infrastructure. SEAMCALL instruction causes #GP when TDX isn't BIOS enabled, and #UD when CPU is not in VMX operation. Currently, only KVM code mocks with VMX enabling, and KVM is the only user of TDX. This implementation chooses to make KVM itself responsible for enabling VMX before using TDX and let the rest of the kernel stay blissfully unaware of VMX. The current TDX_MODULE_CALL macro handles neither #GP nor #UD. The kernel would hit Oops if SEAMCALL were mistakenly made w/o enabling VMX first. Architecturally, there is no CPU flag to check whether the CPU is in VMX operation. Also, if a BIOS were buggy, it could still report valid TDX private KeyIDs when TDX actually couldn't be enabled. Extend the TDX_MODULE_CALL macro to handle #UD and #GP to return error codes. Introduce two new TDX error codes for them respectively so the caller can distinguish. Also add a wrapper function of SEAMCALL to convert SEAMCALL error code to the kernel error code, and print out SEAMCALL error code to help the user to understand what went wrong. Signed-off-by: Kai Huang --- v9 -> v10: - Make the TDX_SEAMCALL_{GP|UD} error codes unconditional but doesn't define them when INTEL_TDX_HOST is enabled. (Dave) - Slightly improved changelog to explain why add assembly code to handle #UD and #GP. v8 -> v9: - Changed patch title (Dave). - Enhanced seamcall() to include the cpu id to the error message when SEAMCALL fails. v7 -> v8: - Improved changelog (Dave): - Trim down some sentences (Dave). - Removed __seamcall() and seamcall() function name and changed accordingly (Dave). - Improved the sentence explaining why to handle #GP (Dave). - Added code to print out error message in seamcall(), following the idea that tdx_enable() to return universal error and print out error message to make clear what's going wrong (Dave). Also mention this in changelog. v6 -> v7: - No change. v5 -> v6: - Added code to handle #UD and #GP (Dave). - Moved the seamcall() wrapper function to this patch, and used a temporary __always_unused to avoid compile warning (Dave). - v3 -> v5 (no feedback on v4): - Explicitly tell TDX_SEAMCALL_VMFAILINVALID is returned if the SEAMCALL itself fails. - Improve the changelog. --- arch/x86/include/asm/tdx.h | 5 +++ arch/x86/virt/vmx/tdx/Makefile | 2 +- arch/x86/virt/vmx/tdx/seamcall.S | 52 +++++++++++++++++++++++++++++ arch/x86/virt/vmx/tdx/tdx.c | 56 ++++++++++++++++++++++++++++++++ arch/x86/virt/vmx/tdx/tdx.h | 10 ++++++ arch/x86/virt/vmx/tdx/tdxcall.S | 19 +++++++++-- 6 files changed, 141 insertions(+), 3 deletions(-) create mode 100644 arch/x86/virt/vmx/tdx/seamcall.S create mode 100644 arch/x86/virt/vmx/tdx/tdx.h diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 4dfe2e794411..b489b5b9de5d 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -8,6 +8,8 @@ #include #include +#include + /* * SW-defined error codes. * @@ -18,6 +20,9 @@ #define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40)) #define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _UL(0xFFFF0000)) +#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) +#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) + #ifndef __ASSEMBLY__ /* TDX supported page sizes from the TDX module ABI. */ diff --git a/arch/x86/virt/vmx/tdx/Makefile b/arch/x86/virt/vmx/tdx/Makefile index 93ca8b73e1f1..38d534f2c113 100644 --- a/arch/x86/virt/vmx/tdx/Makefile +++ b/arch/x86/virt/vmx/tdx/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += tdx.o +obj-y += tdx.o seamcall.o diff --git a/arch/x86/virt/vmx/tdx/seamcall.S b/arch/x86/virt/vmx/tdx/seamcall.S new file mode 100644 index 000000000000..f81be6b9c133 --- /dev/null +++ b/arch/x86/virt/vmx/tdx/seamcall.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include + +#include "tdxcall.S" + +/* + * __seamcall() - Host-side interface functions to SEAM software module + * (the P-SEAMLDR or the TDX module). + * + * Transform function call register arguments into the SEAMCALL register + * ABI. Return TDX_SEAMCALL_VMFAILINVALID if the SEAMCALL itself fails, + * or the completion status of the SEAMCALL leaf function. Additional + * output operands are saved in @out (if it is provided by the caller). + * + *------------------------------------------------------------------------- + * SEAMCALL ABI: + *------------------------------------------------------------------------- + * Input Registers: + * + * RAX - SEAMCALL Leaf number. + * RCX,RDX,R8-R9 - SEAMCALL Leaf specific input registers. + * + * Output Registers: + * + * RAX - SEAMCALL completion status code. + * RCX,RDX,R8-R11 - SEAMCALL Leaf specific output registers. + * + *------------------------------------------------------------------------- + * + * __seamcall() function ABI: + * + * @fn (RDI) - SEAMCALL Leaf number, moved to RAX + * @rcx (RSI) - Input parameter 1, moved to RCX + * @rdx (RDX) - Input parameter 2, moved to RDX + * @r8 (RCX) - Input parameter 3, moved to R8 + * @r9 (R8) - Input parameter 4, moved to R9 + * + * @out (R9) - struct tdx_module_output pointer + * stored temporarily in R12 (not + * used by the P-SEAMLDR or the TDX + * module). It can be NULL. + * + * Return (via RAX) the completion status of the SEAMCALL, or + * TDX_SEAMCALL_VMFAILINVALID. + */ +SYM_FUNC_START(__seamcall) + FRAME_BEGIN + TDX_MODULE_CALL host=1 + FRAME_END + RET +SYM_FUNC_END(__seamcall) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index a600b5d0879d..b65b838f3b5d 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -12,9 +12,11 @@ #include #include #include +#include #include #include #include +#include "tdx.h" static u32 tdx_global_keyid __ro_after_init; static u32 tdx_guest_keyid_start __ro_after_init; @@ -103,3 +105,57 @@ bool platform_tdx_enabled(void) { return !!tdx_global_keyid; } + +/* + * Wrapper of __seamcall() to convert SEAMCALL leaf function error code + * to kernel error code. @seamcall_ret and @out contain the SEAMCALL + * leaf function return code and the additional output respectively if + * not NULL. + */ +static int __always_unused seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, + u64 *seamcall_ret, + struct tdx_module_output *out) +{ + int cpu, ret = 0; + u64 sret; + + /* Need a stable CPU id for printing error message */ + cpu = get_cpu(); + + sret = __seamcall(fn, rcx, rdx, r8, r9, out); + + /* Save SEAMCALL return code if the caller wants it */ + if (seamcall_ret) + *seamcall_ret = sret; + + /* SEAMCALL was successful */ + if (!sret) + goto out; + + switch (sret) { + case TDX_SEAMCALL_GP: + pr_err_once("[firmware bug]: TDX is not enabled by BIOS.\n"); + ret = -ENODEV; + break; + case TDX_SEAMCALL_VMFAILINVALID: + pr_err_once("TDX module is not loaded.\n"); + ret = -ENODEV; + break; + case TDX_SEAMCALL_UD: + pr_err_once("SEAMCALL failed: CPU %d is not in VMX operation.\n", + cpu); + ret = -EINVAL; + break; + default: + pr_err_once("SEAMCALL failed: CPU %d: leaf %llu, error 0x%llx.\n", + cpu, fn, sret); + if (out) + pr_err_once("additional output: rcx 0x%llx, rdx 0x%llx, r8 0x%llx, r9 0x%llx, r10 0x%llx, r11 0x%llx.\n", + out->rcx, out->rdx, out->r8, + out->r9, out->r10, out->r11); + ret = -EIO; + } +out: + put_cpu(); + return ret; +} diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h new file mode 100644 index 000000000000..48ad1a1ba737 --- /dev/null +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _X86_VIRT_TDX_H +#define _X86_VIRT_TDX_H + +#include + +struct tdx_module_output; +u64 __seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, + struct tdx_module_output *out); +#endif diff --git a/arch/x86/virt/vmx/tdx/tdxcall.S b/arch/x86/virt/vmx/tdx/tdxcall.S index 49a54356ae99..757b0c34be10 100644 --- a/arch/x86/virt/vmx/tdx/tdxcall.S +++ b/arch/x86/virt/vmx/tdx/tdxcall.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include #include +#include /* * TDCALL and SEAMCALL are supported in Binutils >= 2.36. @@ -45,6 +46,7 @@ /* Leave input param 2 in RDX */ .if \host +1: seamcall /* * SEAMCALL instruction is essentially a VMExit from VMX root @@ -57,10 +59,23 @@ * This value will never be used as actual SEAMCALL error code as * it is from the Reserved status code class. */ - jnc .Lno_vmfailinvalid + jnc .Lseamcall_out mov $TDX_SEAMCALL_VMFAILINVALID, %rax -.Lno_vmfailinvalid: + jmp .Lseamcall_out +2: + /* + * SEAMCALL caused #GP or #UD. By reaching here %eax contains + * the trap number. Convert the trap number to the TDX error + * code by setting TDX_SW_ERROR to the high 32-bits of %rax. + * + * Note cannot OR TDX_SW_ERROR directly to %rax as OR instruction + * only accepts 32-bit immediate at most. + */ + mov $TDX_SW_ERROR, %r12 + orq %r12, %rax + _ASM_EXTABLE_FAULT(1b, 2b) +.Lseamcall_out: .else tdcall .endif From patchwork Mon Mar 6 14:13:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161220 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1DE7C678D4 for ; Mon, 6 Mar 2023 14:14:59 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 93188280002; Mon, 6 Mar 2023 09:14:59 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 8E08E6B0078; Mon, 6 Mar 2023 09:14:59 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 78384280002; Mon, 6 Mar 2023 09:14:59 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 6968E6B0072 for ; Mon, 6 Mar 2023 09:14:59 -0500 (EST) Received: from smtpin13.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay07.hostedemail.com (Postfix) with ESMTP id 3910016050E for ; Mon, 6 Mar 2023 14:14:59 +0000 (UTC) X-FDA: 80538669918.13.C600D96 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id BFC7C100010 for ; Mon, 6 Mar 2023 14:14:56 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=MTi9dUUd; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112097; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=ytZrO9pAD0TUKZGuXEs7p28gPyCpLCf54E+RHBDEQoQ=; b=P93IwVEQNOm686irZphVufHe+AbzmWQvPLwZKlxkkxE84igwUBRdbYDMl3clTtGMKQ8BsU YYex85K4Zy+Gn0s681DGP1v9LS/kMd7BtMqW4fcu8a50d+GykXFae7PiS83L/4jXtsu0ma Fzt90tgYcMPAh3zQFhcHA3j3zYElcHU= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=MTi9dUUd; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112097; a=rsa-sha256; cv=none; b=qKfea+JffYn6O5W1soBVGdQMORt31y4uDbICcm/zvg35qNgeAJMCd9TueXbPhQmbGwy1gG vjuBqAa7wq7EqnRibLdFJ82TYUdhAyTJPzrld2rOL7cX/wEpSB75tFp2ok2vq7qihLHKLb 8g0/v0UWBht5iGEaMv9Rw3HAHG/LTPY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112096; x=1709648096; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WsDUIOtagxcjdB7YYb5/nPYU+cZHxidSVv9+ymwBYjg=; b=MTi9dUUd0Bb3YWvqN9Frj7lglpllZwF1AeEkDDd59ueEzu5Q2hu+ZuJg qpSleP0LBTmg09QybHO4QnO/VuhAU9tVSPx2ydnD07MYVVzWvr6m+9fPk PvIPxTcXQOl7KeZ84vFIVSaMb00CGQ7cJHTWB/UUTwEfIUlNMogFozduT 0uCfLaqkr5wIouiBzgGFCGEl3pKuePe9X//4NESw2TADkFS45DMXqu9Ag Oj+AUYXFLk6dYlMJS1PQfl0Sr/n0d2EWVHJlIQEC30fnx9jnApamb8JOV Giief1DSvBJrFVSuNbRKZNCXwOpyjLy+mQkKgol519WRmA0+vq9CB/L3R w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080092" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080092" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232104" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232104" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:51 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 05/16] x86/virt/tdx: Add skeleton to enable TDX on demand Date: Tue, 7 Mar 2023 03:13:50 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: BFC7C100010 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: z9g9mztp348jatex78ynm44r9brgxiy7 X-HE-Tag: 1678112096-7905 X-HE-Meta: U2FsdGVkX1/IXtJfMYZsWRvlM5eo7siipJ/6KoeZS3Rw+dx0hx+FUl4Cv0StFgb5nOA9FKZznA4YO924eTWM+lEJiwxhCf2DeFHPvVuan3KiYQ69AbC9CUhzPd5KZzfEehqcVzcBuwtCAOaFnzbvroDUgelP8UL0HWHVxeI/4/2vJ7Blt8vY+VhNx+HkWq1iDqIyyA6LG51qWs5VwMa7fVdmWOLdCPNzu15voqoPVXjboQLGHbfswtKPY5OG0sbalHpP+c+rw9tWsRGjxjwaBB9I85CgO3f+iHA0vDKJ1DKbWifGE3yY9eUs0vRlgiWhbtlSOxISw6f/h4MkR+516PrR6gRRgeX+g7FOhyRq0wSxu6pj0a8kZVhKENAyOYYtr1mMEIk0h01ATySaAz8UqwY1lyZfg5HomjtDeoL8kdDBp/W5Bq8uoIopV8s65YUVwKXCN3QsxQ0YLIX/1u0DyeXW2kEp+Aqajg21Nm8+9mR/1TDp0BwabIAh6SrKIq8Qgwqp6HjzdKZQChWfFfpsfTcTPjl1/yoTL4oZXytF1/rU6nQmsG/jSQQeK4VTsjHPgnMdXZMyhELyCxYURjw7V1piDn1KOzWzg2SZepD1Kt570O3HJiImwnuOmSOSBIICAri+ACilqgpJqpIqg0MjXb14zIzdtMnv5g2amcKW4IEJeR2l+pHY1OaNL0ZRHiF8xbV7a1KEf4gaeDnfaJ6UD6gIvYLE3tzDw2hD0IMdgzWOXM94a7WG/gGXx4j8HN1byTIRkuGFC+/BHYeqiMEWtR2m/7Xl5qkB7tdiwNyyjBHnrZqaCFwyvzVW3U8lk/xPyLPEnYhV3Y6TdcEt5DouyK/ae4+clxuIlV5OICHFjVXQmc/nRhCVuOQ4yYiDWyHZ5/7CveDDCdEnLn+Vluq8UL4VjZ1VlIUguw0/BtWNE2qg1FHUW0Lj/xcWCO/oBU4Z0lSLdwKEp+vwKHcl40+ 52yito5q JA9Rfd9W8cY0tZ5NxN1Kz8/jzbnXqQiK76cEjKEBtTw5dOjHtCqePLATX/5oEME7m/XymeFBvtjdk9F7f9GZ72ATcC3n0T8apxx84gp9iyGjREhaCWyEuE+Dtc4okpwbwh9sDBGsRTaak32OccZf9TgLGe9KSngyvxGORsfkKTuAV8QE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: To enable TDX the kernel needs to initialize TDX from two perspectives: 1) Do a set of SEAMCALLs to initialize the TDX module to make it ready to create and run TDX guests; 2) Do the per-cpu initialization SEAMCALL on one logical cpu before the kernel wants to make any other SEAMCALLs on that cpu (including those involved during module initialization and running TDX guests). The TDX module can be initialized only once in its lifetime. Instead of always initializing it at boot time, this implementation chooses an "on demand" approach to initialize TDX until there is a real need (e.g when requested by KVM). This approach has below pros: 1) It avoids consuming the memory that must be allocated by kernel and given to the TDX module as metadata (~1/256th of the TDX-usable memory), and also saves the CPU cycles of initializing the TDX module (and the metadata) when TDX is not used at all. 2) The TDX module design allows it to be updated while the system is running. The update procedure shares quite a few steps with this "on demand" initialization mechanism. The hope is that much of "on demand" mechanism can be shared with a future "update" mechanism. A boot-time TDX module implementation would not be able to share much code with the update mechanism. 3) Making SEAMCALL requires VMX to be enabled. Currently, only the KVM code mucks with VMX enabling. If the TDX module were to be initialized separately from KVM (like at boot), the boot code would need to be taught how to muck with VMX enabling and KVM would need to be taught how to cope with that. Making KVM itself responsible for TDX initialization lets the rest of the kernel stay blissfully unaware of VMX. Similar to module initialization, also make the per-cpu initialization "on demand" as it also depends on VMX to be enabled. Add two functions, tdx_enable() and tdx_cpu_enable(), to enable the TDX module and enable TDX on local cpu respectively. For now tdx_enable() is a placeholder. The TODO list will be pared down as functionality is added. In tdx_enable() use a state machine protected by mutex to make sure the initialization will only be done once, as tdx_enable() can be called multiple times (i.e. KVM module can be reloaded) and may be called concurrently by other kernel components in the future. The per-cpu initialization on each cpu can only be done once during the module's life time. Use a per-cpu variable to track its status to make sure it is only done once in tdx_cpu_enable(). Also, a SEAMCALL to do TDX module global initialization must be done once on any logical cpu before any per-cpu initialization SEAMCALL. Do it inside tdx_cpu_enable() too (if hasn't been done). tdx_enable() can potentially invoke SEAMCALLs on any online cpus. The per-cpu initialization must be done before those SEAMCALLs are invoked on some cpu. To keep things simple, in tdx_cpu_enable(), always do the per-cpu initialization regardless of whether the TDX module has been initialized or not. And in tdx_enable(), don't call tdx_cpu_enable() but assume the caller has disabled CPU hotplug and done VMXON and tdx_cpu_enable() on all online cpus before calling tdx_enable(). Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata Signed-off-by: Isaku Yamahata --- v9 -> v10: - Merged the patch to handle per-cpu initialization to this patch to tell the story better. - Changed how to handle the per-cpu initialization to only provide a tdx_cpu_enable() function to let the user of TDX to do it when the user wants to run TDX code on a certain cpu. - Changed tdx_enable() to not call cpus_read_lock() explicitly, but call lockdep_assert_cpus_held() to assume the caller has done that. - Improved comments around tdx_enable() and tdx_cpu_enable(). - Improved changelog to tell the story better accordingly. v8 -> v9: - Removed detailed TODO list in the changelog (Dave). - Added back steps to do module global initialization and per-cpu initialization in the TODO list comment. - Moved the 'enum tdx_module_status_t' from tdx.c to local tdx.h v7 -> v8: - Refined changelog (Dave). - Removed "all BIOS-enabled cpus" related code (Peter/Thomas/Dave). - Add a "TODO list" comment in init_tdx_module() to list all steps of initializing the TDX Module to tell the story (Dave). - Made tdx_enable() unverisally return -EINVAL, and removed nonsense comments (Dave). - Simplified __tdx_enable() to only handle success or failure. - TDX_MODULE_SHUTDOWN -> TDX_MODULE_ERROR - Removed TDX_MODULE_NONE (not loaded) as it is not necessary. - Improved comments (Dave). - Pointed out 'tdx_module_status' is software thing (Dave). v6 -> v7: - No change. v5 -> v6: - Added code to set status to TDX_MODULE_NONE if TDX module is not loaded (Chao) - Added Chao's Reviewed-by. - Improved comments around cpus_read_lock(). - v3->v5 (no feedback on v4): - Removed the check that SEAMRR and TDX KeyID have been detected on all present cpus. - Removed tdx_detect(). - Added num_online_cpus() to MADT-enabled CPUs check within the CPU hotplug lock and return early with error message. - Improved dmesg printing for TDX module detection and initialization. --- arch/x86/include/asm/tdx.h | 4 + arch/x86/virt/vmx/tdx/tdx.c | 182 ++++++++++++++++++++++++++++++++++++ arch/x86/virt/vmx/tdx/tdx.h | 25 +++++ 3 files changed, 211 insertions(+) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index b489b5b9de5d..112a5b9bd5cd 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -102,8 +102,12 @@ static inline long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, #ifdef CONFIG_INTEL_TDX_HOST bool platform_tdx_enabled(void); +int tdx_cpu_enable(void); +int tdx_enable(void); #else /* !CONFIG_INTEL_TDX_HOST */ static inline bool platform_tdx_enabled(void) { return false; } +static inline int tdx_cpu_enable(void) { return -EINVAL; } +static inline int tdx_enable(void) { return -EINVAL; } #endif /* CONFIG_INTEL_TDX_HOST */ #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index b65b838f3b5d..29127cb70f51 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -13,6 +13,10 @@ #include #include #include +#include +#include +#include +#include #include #include #include @@ -22,6 +26,18 @@ static u32 tdx_global_keyid __ro_after_init; static u32 tdx_guest_keyid_start __ro_after_init; static u32 tdx_nr_guest_keyids __ro_after_init; +static unsigned int tdx_global_init_status; +static DEFINE_SPINLOCK(tdx_global_init_lock); +#define TDX_GLOBAL_INIT_DONE _BITUL(0) +#define TDX_GLOBAL_INIT_FAILED _BITUL(1) + +static DEFINE_PER_CPU(unsigned int, tdx_lp_init_status); +#define TDX_LP_INIT_DONE _BITUL(0) +#define TDX_LP_INIT_FAILED _BITUL(1) + +static enum tdx_module_status_t tdx_module_status; +static DEFINE_MUTEX(tdx_module_lock); + /* * Use tdx_global_keyid to indicate that TDX is uninitialized. * This is used in TDX initialization error paths to take it from @@ -159,3 +175,169 @@ static int __always_unused seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, put_cpu(); return ret; } + +static int try_init_module_global(void) +{ + int ret; + + /* + * The TDX module global initialization only needs to be done + * once on any cpu. + */ + spin_lock(&tdx_global_init_lock); + + if (tdx_global_init_status & TDX_GLOBAL_INIT_DONE) { + ret = tdx_global_init_status & TDX_GLOBAL_INIT_FAILED ? + -EINVAL : 0; + goto out; + } + + /* All '0's are just unused parameters. */ + ret = seamcall(TDH_SYS_INIT, 0, 0, 0, 0, NULL, NULL); + + tdx_global_init_status = TDX_GLOBAL_INIT_DONE; + if (ret) + tdx_global_init_status |= TDX_GLOBAL_INIT_FAILED; +out: + spin_unlock(&tdx_global_init_lock); + + return ret; +} + +/** + * tdx_cpu_enable - Enable TDX on local cpu + * + * Do one-time TDX module per-cpu initialization SEAMCALL (and TDX module + * global initialization SEAMCALL if not done) on local cpu to make this + * cpu be ready to run any other SEAMCALLs. + * + * Note this function must be called when preemption is not possible + * (i.e. via SMP call or in per-cpu thread). It is not IRQ safe either + * (i.e. cannot be called in per-cpu thread and via SMP call from remote + * cpu simultaneously). + * + * Return 0 on success, otherwise errors. + */ +int tdx_cpu_enable(void) +{ + unsigned int lp_status; + int ret; + + if (!platform_tdx_enabled()) + return -EINVAL; + + lp_status = __this_cpu_read(tdx_lp_init_status); + + /* Already done */ + if (lp_status & TDX_LP_INIT_DONE) + return lp_status & TDX_LP_INIT_FAILED ? -EINVAL : 0; + + /* + * The TDX module global initialization is the very first step + * to enable TDX. Need to do it first (if hasn't been done) + * before doing the per-cpu initialization. + */ + ret = try_init_module_global(); + + /* + * If the module global initialization failed, there's no point + * to do the per-cpu initialization. Just mark it as done but + * failed. + */ + if (ret) + goto update_status; + + /* All '0's are just unused parameters */ + ret = seamcall(TDH_SYS_LP_INIT, 0, 0, 0, 0, NULL, NULL); + +update_status: + lp_status = TDX_LP_INIT_DONE; + if (ret) + lp_status |= TDX_LP_INIT_FAILED; + + this_cpu_write(tdx_lp_init_status, lp_status); + + return ret; +} +EXPORT_SYMBOL_GPL(tdx_cpu_enable); + +static int init_tdx_module(void) +{ + /* + * TODO: + * + * - Get TDX module information and TDX-capable memory regions. + * - Build the list of TDX-usable memory regions. + * - Construct a list of "TD Memory Regions" (TDMRs) to cover + * all TDX-usable memory regions. + * - Configure the TDMRs and the global KeyID to the TDX module. + * - Configure the global KeyID on all packages. + * - Initialize all TDMRs. + * + * Return error before all steps are done. + */ + return -EINVAL; +} + +static int __tdx_enable(void) +{ + int ret; + + ret = init_tdx_module(); + if (ret) { + pr_err("TDX module initialization failed (%d)\n", ret); + tdx_module_status = TDX_MODULE_ERROR; + /* + * Just return one universal error code. + * For now the caller cannot recover anyway. + */ + return -EINVAL; + } + + pr_info("TDX module initialized.\n"); + tdx_module_status = TDX_MODULE_INITIALIZED; + + return 0; +} + +/** + * tdx_enable - Enable TDX module to make it ready to run TDX guests + * + * This function assumes the caller has: 1) held read lock of CPU hotplug + * lock to prevent any new cpu from becoming online; 2) done both VMXON + * and tdx_cpu_enable() on all online cpus. + * + * This function can be called in parallel by multiple callers. + * + * Return 0 if TDX is enabled successfully, otherwise error. + */ +int tdx_enable(void) +{ + int ret; + + if (!platform_tdx_enabled()) + return -EINVAL; + + lockdep_assert_cpus_held(); + + mutex_lock(&tdx_module_lock); + + switch (tdx_module_status) { + case TDX_MODULE_UNKNOWN: + ret = __tdx_enable(); + break; + case TDX_MODULE_INITIALIZED: + /* Already initialized, great, tell the caller. */ + ret = 0; + break; + default: + /* Failed to initialize in the previous attempts */ + ret = -EINVAL; + break; + } + + mutex_unlock(&tdx_module_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(tdx_enable); diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 48ad1a1ba737..4d6220e86ccf 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -4,6 +4,31 @@ #include +/* + * This file contains both macros and data structures defined by the TDX + * architecture and Linux defined software data structures and functions. + * The two should not be mixed together for better readability. The + * architectural definitions come first. + */ + +/* + * TDX module SEAMCALL leaf functions + */ +#define TDH_SYS_INIT 33 +#define TDH_SYS_LP_INIT 35 + +/* + * Do not put any hardware-defined TDX structure representations below + * this comment! + */ + +/* Kernel defined TDX module status during module initialization. */ +enum tdx_module_status_t { + TDX_MODULE_UNKNOWN, + TDX_MODULE_INITIALIZED, + TDX_MODULE_ERROR +}; + struct tdx_module_output; u64 __seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, struct tdx_module_output *out); From patchwork Mon Mar 6 14:13:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 471F6C678D4 for ; Mon, 6 Mar 2023 14:15:05 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id DC5456B0072; Mon, 6 Mar 2023 09:15:04 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id D9BE8280004; Mon, 6 Mar 2023 09:15:04 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id C3CC9280003; Mon, 6 Mar 2023 09:15:04 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id B2FDB6B0072 for ; Mon, 6 Mar 2023 09:15:04 -0500 (EST) Received: from smtpin05.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id 7177E120732 for ; Mon, 6 Mar 2023 14:15:04 +0000 (UTC) X-FDA: 80538670128.05.A2DEDC4 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id BA1AE10002B for ; Mon, 6 Mar 2023 14:15:00 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=gpUI815U; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112101; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=OO57e1MxGpJ4yHW1QGQ2tR/4Lqg9N3s3LmoBJDZqM2Q=; b=kU9TYo9r615qe1PsvHOfYGFh18N9XYPOw8jjb7tswbS36RE9F+dIyaGTnNW3RkH3OH7LSq 6YP5Nec2IzrlfNxwKW9E4vo3gPJ7uFEs2SqkDyXoilbKZh6IbCAbKmiCJ9lDD+/8KR565m MRhtlBb6YbkNHns9AUurO+h4I/YMMaU= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=gpUI815U; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112101; a=rsa-sha256; cv=none; b=gufw0GSiPO2dRuqYNp8IFD7QVIOp6nLz59qIsMWy2nEeT4+MapsUtlLwRNv46S415Iqs2u gcpp2vgGMYUMeHEaxlB4JJCEHAsqaFzWAK24XturkiaoER64lwRii4HvuObYwkNS2CkMio KiI1SjQ4Ch4dukVTa4lOb2UOaMHnkbc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112100; x=1709648100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qdVCP0l+N28e4ZOsbONZe3dTE2i3AewatZCo6kOUz7Q=; b=gpUI815UxHzJ8oQK2s/HPH+j/dtagnsojTgbSIcYhqIQt7MmRyYt/sm3 JxdxcOCr6JsMuzx4Fp6D6awBiVL4dVRd3J1XnrcDs+hu4Tqvgeks+eHac F9ITxCP8HiYNvWfhaDLrUNKBI2aXT5CojRRjYRgh2JtFApxQXNuZSx9T5 brQzZ7wEo4wia63vzNeYDrBmJ/edJScULWq02VnJls5tq8QdzFteLGK3i afFM40GHOq8ZAgvjZ8067iCRcn3J3kcuY2/XDH3mq582u9Cdk4oV+QROS fIs5uMwKXvBIxQW1mnYfPfK0a34x+XZelT6FF2XXP0pgXCGc373HIA/Qw A==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080112" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080112" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232120" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232120" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:55 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 06/16] x86/virt/tdx: Get information about TDX module and TDX-capable memory Date: Tue, 7 Mar 2023 03:13:51 +1300 Message-Id: <7c6161b262b8784b764c1b0d0fd7201d270554ba.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: BA1AE10002B X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 1zt1toz3x7ix69jeys68eoqeec1j8zu9 X-HE-Tag: 1678112100-72563 X-HE-Meta: U2FsdGVkX1+aQ3aLWTREm2cvb0ZEODsrtGy1oKFhmdtH49LzKVhCCRN4wJvdm6jdWIfhSTmdWjk9EgNRMgKx38yiofPmlBRLNfQZ0mYPe4t4Z5d47vLtB+g9OeGJi1/5aM1i8JA2yGCLGJEGkzurNFnzEXkvMfgcnbjkFNsWyo9NI1uUs3qAoJ6Z/HqSkFycPMe6B1b2qPEYxCQIqJ+vuOQrp52TfmzuloUDJhDDcVqbobufCvgTX9KU8LlCw8fOam+T/jvyed9L71g5+/OUs6CuBBU6c4Y/NvpGMH94UgcHxJYcnex/E8DWr44/7am3zQRYgdP+pvyEnrHtU0IPaCTpf5zysPZfTLyPTrST1YdcSkZ7e6YUCHGlt8kCILHx+Krr74RvCv3dp/+0KTHp8pReqSXIpB1sZvTAJxa8rUMtJ/4nmOnKqtvEKl1Vvqvu3Y7roLYzU58h3eYxo1E59mssrAI4m58GpRLqCALqF/q6hJV61II0W7oiVI19p7+gJDsABjxnWVzauCEOXUHWlzeFkQF8V8aEWLtg542Kk2yKbKycUXf+APrvFFSEs1fUhRuGt3gY6/+vQLmSBvBHj9Mz60F9dk4DSqtBC7rANcS1IB/NZi04udYqN4G8FjIT4U6hShpwJ4XibD3CdN79Z9/yPW/AJ1CD6ibTB46reK080TnjSUaT1iDklmQKHiBPUot4NYLYs8mn7pJrQ/PJ5VVVRrIQaXGg5QwjWaLYs+/+7rsI00sI2FEA3nSAZILrg+0XrS6Grj0ES0cJycyykmHNYiuLI21raqCZt72Nk2AvRAIWiyzaA2a3/0qbdHpJoZNXDpGkPMvE9lfBouG5RIztT35/qfMnsCwfKp/d2+OhzQsCPc/GflwipgAvjgUoW5z4aJkah/q6nuiUrH++K317WBX71KOSQ51waqnAzza5Iwicxf98g1Fl8Wum/wJ+gD+bOfE/rpFUsInk1/l 7Hg3dkB5 +OFCkZnNZ3gF2WSb5Op67CG3HrXOKM/gMos1s2vJHR6RV2PAohbBlg31uvIZM653t+Xks1hdoaeW4hz1+L81G1KLgS2OA49yYc74t1Fl3tTGi+W4Ur8NfJltviokrWcJIpxjZyPrKZCXrQkutlUuHFE5NuyBa2saHCdcKpG3N5enK+D4iuTZrHxJkaqzR/Ic2tuJEn2lGRgNae7huOTotKn0TzQhWFJlpaMIW8HZHIL0S3MQ= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Start to transit out the "multi-steps" to initialize the TDX module. TDX provides increased levels of memory confidentiality and integrity. This requires special hardware support for features like memory encryption and storage of memory integrity checksums. Not all memory satisfies these requirements. As a result, TDX introduced the concept of a "Convertible Memory Region" (CMR). During boot, the firmware builds a list of all of the memory ranges which can provide the TDX security guarantees. CMRs tell the kernel which memory is TDX compatible. The kernel takes CMRs (plus a little more metadata) and constructs "TD Memory Regions" (TDMRs). TDMRs let the kernel grant TDX protections to some or all of the CMR areas. The TDX module also reports necessary information to let the kernel build TDMRs and run TDX guests in structure 'tdsysinfo_struct'. The list of CMRs, along with the TDX module information, is available to the kernel by querying the TDX module. As a preparation to construct TDMRs, get the TDX module information and the list of CMRs. Print out CMRs to help user to decode which memory regions are TDX convertible. The 'tdsysinfo_struct' is fairly large (1024 bytes) and contains a lot of info about the TDX module. Fully define the entire structure, but only use the fields necessary to build the TDMRs and pr_info() some basics about the module. The rest of the fields will get used by KVM. For now both 'tdsysinfo_struct' and CMRs are only used during the module initialization. But because they are both relatively big, declare them inside the module initialization function but as static variables. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - Added back "start to transit out..." as now per-cpu init has been moved out from tdx_enable(). v8 -> v9: - Removed "start to trransit out ..." part in changelog since this patch is no longer the first step anymore. - Changed to declare 'tdsysinfo' and 'cmr_array' as local static, and changed changelog accordingly (Dave). - Improved changelog to explain why to declare 'tdsysinfo_struct' in full but only use a few members of them (Dave). v7 -> v8: (Dave) - Improved changelog to tell this is the first patch to transit out the "multi-steps" init_tdx_module(). - Removed all CMR check/trim code but to depend on later SEAMCALL. - Variable 'vertical alignment' in print TDX module information. - Added DECLARE_PADDED_STRUCT() for padded structure. - Made tdx_sysinfo and tdx_cmr_array[] to be function local variable (and rename them accordingly), and added -Wframe-larger-than=4096 flag to silence the build warning. v6 -> v7: - Simplified the check of CMRs due to the fact that TDX actually verifies CMRs (that are passed by the BIOS) before enabling TDX. - Changed the function name from check_cmrs() -> trim_empty_cmrs(). - Added CMR page aligned check so that later patch can just get the PFN using ">> PAGE_SHIFT". v5 -> v6: - Added to also print TDX module's attribute (Isaku). - Removed all arguments in tdx_gete_sysinfo() to use static variables of 'tdx_sysinfo' and 'tdx_cmr_array' directly as they are all used directly in other functions in later patches. - Added Isaku's Reviewed-by. - v3 -> v5 (no feedback on v4): - Renamed sanitize_cmrs() to check_cmrs(). - Removed unnecessary sanity check against tdx_sysinfo and tdx_cmr_array actual size returned by TDH.SYS.INFO. - Changed -EFAULT to -EINVAL in couple places. - Added comments around tdx_sysinfo and tdx_cmr_array saying they are used by TDH.SYS.INFO ABI. - Changed to pass 'tdx_sysinfo' and 'tdx_cmr_array' as function arguments in tdx_get_sysinfo(). - Changed to only print BIOS-CMR when check_cmrs() fails. --- arch/x86/virt/vmx/tdx/tdx.c | 67 +++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 72 +++++++++++++++++++++++++++++++++++++ 2 files changed, 138 insertions(+), 1 deletion(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 29127cb70f51..981e11492d0e 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "tdx.h" @@ -261,12 +262,76 @@ int tdx_cpu_enable(void) } EXPORT_SYMBOL_GPL(tdx_cpu_enable); +static inline bool is_cmr_empty(struct cmr_info *cmr) +{ + return !cmr->size; +} + +static void print_cmrs(struct cmr_info *cmr_array, int nr_cmrs) +{ + int i; + + for (i = 0; i < nr_cmrs; i++) { + struct cmr_info *cmr = &cmr_array[i]; + + /* + * The array of CMRs reported via TDH.SYS.INFO can + * contain tail empty CMRs. Don't print them. + */ + if (is_cmr_empty(cmr)) + break; + + pr_info("CMR: [0x%llx, 0x%llx)\n", cmr->base, + cmr->base + cmr->size); + } +} + +/* + * Get the TDX module information (TDSYSINFO_STRUCT) and the array of + * CMRs, and save them to @sysinfo and @cmr_array. @sysinfo must have + * been padded to have enough room to save the TDSYSINFO_STRUCT. + */ +static int tdx_get_sysinfo(struct tdsysinfo_struct *sysinfo, + struct cmr_info *cmr_array) +{ + struct tdx_module_output out; + u64 sysinfo_pa, cmr_array_pa; + int ret; + + sysinfo_pa = __pa(sysinfo); + cmr_array_pa = __pa(cmr_array); + ret = seamcall(TDH_SYS_INFO, sysinfo_pa, TDSYSINFO_STRUCT_SIZE, + cmr_array_pa, MAX_CMRS, NULL, &out); + if (ret) + return ret; + + pr_info("TDX module: atributes 0x%x, vendor_id 0x%x, major_version %u, minor_version %u, build_date %u, build_num %u", + sysinfo->attributes, sysinfo->vendor_id, + sysinfo->major_version, sysinfo->minor_version, + sysinfo->build_date, sysinfo->build_num); + + /* R9 contains the actual entries written to the CMR array. */ + print_cmrs(cmr_array, out.r9); + + return 0; +} + static int init_tdx_module(void) { + static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, + TDSYSINFO_STRUCT_SIZE, TDSYSINFO_STRUCT_ALIGNMENT); + static struct cmr_info cmr_array[MAX_CMRS] + __aligned(CMR_INFO_ARRAY_ALIGNMENT); + struct tdsysinfo_struct *sysinfo = &PADDED_STRUCT(tdsysinfo); + int ret; + + ret = tdx_get_sysinfo(sysinfo, cmr_array); + if (ret) + return ret; + /* * TODO: * - * - Get TDX module information and TDX-capable memory regions. * - Build the list of TDX-usable memory regions. * - Construct a list of "TD Memory Regions" (TDMRs) to cover * all TDX-usable memory regions. diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 4d6220e86ccf..2f2d8737a364 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -3,6 +3,8 @@ #define _X86_VIRT_TDX_H #include +#include +#include /* * This file contains both macros and data structures defined by the TDX @@ -16,6 +18,76 @@ */ #define TDH_SYS_INIT 33 #define TDH_SYS_LP_INIT 35 +#define TDH_SYS_INFO 32 + +struct cmr_info { + u64 base; + u64 size; +} __packed; + +#define MAX_CMRS 32 +#define CMR_INFO_ARRAY_ALIGNMENT 512 + +struct cpuid_config { + u32 leaf; + u32 sub_leaf; + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; +} __packed; + +#define DECLARE_PADDED_STRUCT(type, name, size, alignment) \ + struct type##_padded { \ + union { \ + struct type name; \ + u8 padding[size]; \ + }; \ + } name##_padded __aligned(alignment) + +#define PADDED_STRUCT(name) (name##_padded.name) + +#define TDSYSINFO_STRUCT_SIZE 1024 +#define TDSYSINFO_STRUCT_ALIGNMENT 1024 + +/* + * The size of this structure itself is flexible. The actual structure + * passed to TDH.SYS.INFO must be padded to TDSYSINFO_STRUCT_SIZE and be + * aligned to TDSYSINFO_STRUCT_ALIGNMENT using DECLARE_PADDED_STRUCT(). + */ +struct tdsysinfo_struct { + /* TDX-SEAM Module Info */ + u32 attributes; + u32 vendor_id; + u32 build_date; + u16 build_num; + u16 minor_version; + u16 major_version; + u8 reserved0[14]; + /* Memory Info */ + u16 max_tdmrs; + u16 max_reserved_per_tdmr; + u16 pamt_entry_size; + u8 reserved1[10]; + /* Control Struct Info */ + u16 tdcs_base_size; + u8 reserved2[2]; + u16 tdvps_base_size; + u8 tdvps_xfam_dependent_size; + u8 reserved3[9]; + /* TD Capabilities */ + u64 attributes_fixed0; + u64 attributes_fixed1; + u64 xfam_fixed0; + u64 xfam_fixed1; + u8 reserved4[32]; + u32 num_cpuid_config; + /* + * The actual number of CPUID_CONFIG depends on above + * 'num_cpuid_config'. + */ + DECLARE_FLEX_ARRAY(struct cpuid_config, cpuid_configs); +} __packed; /* * Do not put any hardware-defined TDX structure representations below From patchwork Mon Mar 6 14:13:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42954C678D4 for ; Mon, 6 Mar 2023 14:15:09 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id D50596B0078; Mon, 6 Mar 2023 09:15:08 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id CFF82280003; Mon, 6 Mar 2023 09:15:08 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id BC7B5280001; Mon, 6 Mar 2023 09:15:08 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id A96826B0078 for ; Mon, 6 Mar 2023 09:15:08 -0500 (EST) Received: from smtpin09.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 78E7F1406BB for ; Mon, 6 Mar 2023 14:15:08 +0000 (UTC) X-FDA: 80538670296.09.70D34E0 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 599AB100016 for ; Mon, 6 Mar 2023 14:15:05 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=ZRS2DN4m; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112105; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=922nywOa+e7tb6QjHPwrsrM9xYheyIddKPYc/Ze9SJ0=; b=WMbtlQcyHERaPegRYyumZpiF2L3jXWjlB/JaPrDpxb5m3i7xdeEiqR9H/i1oXcsQEMlqob IeUsic9mftp5xRC25hxAKjNtFX+tfcYOKo9QBEyl1lgrb28FENnJA39eBn60ZVUkm8Gsrn 7H2xjN9ECzkA5dTA9Lg+L4fO0x7RmP8= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=ZRS2DN4m; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112105; a=rsa-sha256; cv=none; b=ioiN3xlr4t5JX6eaLY6vwg+BsY2zyywJmnsVtJ58wtW0+swTvxI4GcC5m+kCZ6G0ByWpkE JJM0Go6uV5emSZ78+Pm2RSIGV+mBqJzRv+wls90IqkxjIk2nvGo80BA242wF2IATPSdri+ p7Dxm1ISobMaFdLC6JxyTmF3GGs+WXQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112105; x=1709648105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k87SClNK/ZMlCe0BUnMjRVRbHwBgYZY0XiVTxfQ3zsA=; b=ZRS2DN4mFwmEqrgK3uZY9svliHPjs21T29ve1Kex1Lu8zsz3e0IEsxL+ ztsJeUSyA5PkNU5F5/nUZH5a/YbXc8aEBmDQ6CsU7Rn+XZNg46QEQbRql /Xl2Y1AL01yLNJTJC7K5v51DQtRPgwynFVno2f7a2CTbDoTy9VU+85zmK PjvOCVHmhZ6t6U6C2T48mPeSOMgmWkrFQRvXvncAtsMzQvwvn/WJxudRG FHw+llXKSMxp0zCdnbkW7OSN/0AgjxWhJO/xUq4pIf3RasQ8Uwe7IMtNz yK1NSDpoUSaKd80MdDxhBdvQEBzkCXxcp18dG0tilA3arjF5yhABzlT1F Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080151" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080151" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232141" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232141" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:00 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 07/16] x86/virt/tdx: Use all system memory when initializing TDX module as TDX memory Date: Tue, 7 Mar 2023 03:13:52 +1300 Message-Id: <54fce4052e700a78843b5672c5380ffaf3879902.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 599AB100016 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: yzk4igdy3d9qhakn3xjc61euhyj8f61j X-HE-Tag: 1678112105-624706 X-HE-Meta: U2FsdGVkX18v6QHOoyI+I6Ek4GgqLPfhRPcHZcmzXmsAwUvMWRXIrp5NGmpwZJZhQE3w7RdH2IOuPVjiocsZQYNLKkjEaALu6q/7qbA2HvT88bMIdmkDanb1c/aAXWIvYb7T2+Zd+GbEBxixzjWVnRe0sPCg8qqR2ehZoKt4Ggo7qqWb6oaTFajB8dyTvjGhhgdd4Y9Hyfpst1wHAfwoIXJ9Mhx3V0iktOJlK61YszqxJX1Rz4vpxLRcTTN8KMp3+pfzNkoHmtKtDKEpSXsNq3ZrXmQ3ycUIEb5+eSlAQ+7CIAquLTQYmt7p55o+yW2rkpbSoS+C+Fi9Pkkw19OPH1nxOalcQeO4LYt6kTSxiuqfSbxk1OiP3b/RQ6NLG824GRHiWc/hz5j+0B3RLikMgiO2e8Awj6xqD5+YZwujKUSVTkq/S1RgQuR2dSBFXa4yVuiwAskcS7zQZT2zM0vRMAyBhqe1+9C3z7/w2Z8kCp+11+BUgfyBHQWNIbBbXJ6WpmnOuKpctRvNKmIE1YoIy+vd3VvOl50d5HlqIiDCAhB0ibJE9k8rOqH+4xfl83MiIkd7chnCuYoL00sKni6PFuQ2XzTSRMkjSNUIBBAsYqAonI0S3tXQ38N40VNHNnH3Z0EZrKv+CYzbK73hKip+oLK0TtWe5T0b9X2WBL+Uy7qzXA4lY5o0eUVGWpg+goVie8+o4+RBgNJ7w4naoTFMkZcxLPDNtdgBeX+oKfNPBeIQE0oRfU26meR36PosY4KZ2++faqNSES6S4pOEor1Ap4tSv1y3bKAAvjbrsK1Gu5erMKsfaQueV7xpwUAyU6lf/IrhX+HRDbU+mdQTL8H6d4v/Ag1XtsxRWUDrATABvLvWUAe6vLkPH6tTI/6LrfZYCXcDXpUxo8UMs2vi1PXiC61yoOMDIxCcaB26o4A2Pkk2kRAOK6D8ekYhLfMZ8zoD40gzOulngVRsD655GFP 2bWqoioC MtpCrEl+rmWN8wawF2F/6Pq8xCYCQHspU9qcOcKC5rDEZ8OqMoZmDsUqsPRdfI4Lf3Ue+7zlVnkZy7Dk5wGj+HdHXzrXzT/DHVImN1FY+PWggAAOX6LtSm++VhxtxvX7C2bY10fy4fsI/HshHdn0jcQ4rSWs90mm+TNW/s6U5lewsAQQ= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: As a step of initializing the TDX module, the kernel needs to tell the TDX module which memory regions can be used by the TDX module as TDX guest memory. TDX reports a list of "Convertible Memory Region" (CMR) to tell the kernel which memory is TDX compatible. The kernel needs to build a list of memory regions (out of CMRs) as "TDX-usable" memory and pass them to the TDX module. Once this is done, those "TDX-usable" memory regions are fixed during module's lifetime. To keep things simple, assume that all TDX-protected memory will come from the page allocator. Make sure all pages in the page allocator *are* TDX-usable memory. As TDX-usable memory is a fixed configuration, take a snapshot of the memory configuration from memblocks at the time of module initialization (memblocks are modified on memory hotplug). This snapshot is used to enable TDX support for *this* memory configuration only. Use a memory hotplug notifier to ensure that no other RAM can be added outside of this configuration. This approach requires all memblock memory regions at the time of module initialization to be TDX convertible memory to work, otherwise module initialization will fail in a later SEAMCALL when passing those regions to the module. This approach works when all boot-time "system RAM" is TDX convertible memory, and no non-TDX-convertible memory is hot-added to the core-mm before module initialization. For instance, on the first generation of TDX machines, both CXL memory and NVDIMM are not TDX convertible memory. Using kmem driver to hot-add any CXL memory or NVDIMM to the core-mm before module initialization will result in failure to initialize the module. The SEAMCALL error code will be available in the dmesg to help user to understand the failure. Signed-off-by: Kai Huang Reviewed-by: "Huang, Ying" Reviewed-by: Isaku Yamahata --- v9 -> v10: - Moved empty @tdx_memlist check out of is_tdx_memory() to make the logic better. - Added Ying's Reviewed-by. v8 -> v9: - Replace "The initial support ..." with timeless sentence in both changelog and comments(Dave). - Fix run-on sentence in changelog, and senstence to explain why to stash off memblock (Dave). - Tried to improve why to choose this approach and how it work in changelog based on Dave's suggestion. - Many other comments enhancement (Dave). v7 -> v8: - Trimed down changelog (Dave). - Changed to use PHYS_PFN() and PFN_PHYS() throughout this series (Ying). - Moved memory hotplug handling from add_arch_memory() to memory_notifier (Dan/David). - Removed 'nid' from 'struct tdx_memblock' to later patch (Dave). - {build|free}_tdx_memory() -> {build|}free_tdx_memlist() (Dave). - Removed pfn_covered_by_cmr() check as no code to trim CMRs now. - Improve the comment around first 1MB (Dave). - Added a comment around reserve_real_mode() to point out TDX code relies on first 1MB being reserved (Ying). - Added comment to explain why the new online memory range cannot cross multiple TDX memory blocks (Dave). - Improved other comments (Dave). --- arch/x86/Kconfig | 1 + arch/x86/kernel/setup.c | 2 + arch/x86/virt/vmx/tdx/tdx.c | 165 +++++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 6 ++ 4 files changed, 172 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6dd5d5586099..f23bc540778a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1958,6 +1958,7 @@ config INTEL_TDX_HOST depends on X86_64 depends on KVM_INTEL depends on X86_X2APIC + select ARCH_KEEP_MEMBLOCK help Intel Trust Domain Extensions (TDX) protects guest VMs from malicious host and certain physical attacks. This option enables necessary TDX diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 88188549647c..a8a119a9b48c 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1165,6 +1165,8 @@ void __init setup_arch(char **cmdline_p) * * Moreover, on machines with SandyBridge graphics or in setups that use * crashkernel the entire 1M is reserved anyway. + * + * Note the host kernel TDX also requires the first 1MB being reserved. */ x86_platform.realmode_reserve(); diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 981e11492d0e..9149144cd7e7 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -17,6 +17,13 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include #include #include @@ -39,6 +46,9 @@ static DEFINE_PER_CPU(unsigned int, tdx_lp_init_status); static enum tdx_module_status_t tdx_module_status; static DEFINE_MUTEX(tdx_module_lock); +/* All TDX-usable memory regions. Protected by mem_hotplug_lock. */ +static LIST_HEAD(tdx_memlist); + /* * Use tdx_global_keyid to indicate that TDX is uninitialized. * This is used in TDX initialization error paths to take it from @@ -77,6 +87,54 @@ static int __init record_keyid_partitioning(u32 *tdx_keyid_start, return 0; } +static bool is_tdx_memory(unsigned long start_pfn, unsigned long end_pfn) +{ + struct tdx_memblock *tmb; + + /* + * This check assumes that the start_pfn<->end_pfn range does not + * cross multiple @tdx_memlist entries. A single memory online + * event across multiple memblocks (from which @tdx_memlist + * entries are derived at the time of module initialization) is + * not possible. This is because memory offline/online is done + * on granularity of 'struct memory_block', and the hotpluggable + * memory region (one memblock) must be multiple of memory_block. + */ + list_for_each_entry(tmb, &tdx_memlist, list) { + if (start_pfn >= tmb->start_pfn && end_pfn <= tmb->end_pfn) + return true; + } + return false; +} + +static int tdx_memory_notifier(struct notifier_block *nb, unsigned long action, + void *v) +{ + struct memory_notify *mn = v; + + if (action != MEM_GOING_ONLINE) + return NOTIFY_OK; + + /* + * Empty list means TDX isn't enabled. Allow any memory + * to go online. + */ + if (list_empty(&tdx_memlist)) + return NOTIFY_OK; + + /* + * The TDX memory configuration is static and can not be + * changed. Reject onlining any memory which is outside of + * the static configuration whether it supports TDX or not. + */ + return is_tdx_memory(mn->start_pfn, mn->start_pfn + mn->nr_pages) ? + NOTIFY_OK : NOTIFY_BAD; +} + +static struct notifier_block tdx_memory_nb = { + .notifier_call = tdx_memory_notifier, +}; + static int __init tdx_init(void) { u32 tdx_keyid_start, nr_tdx_keyids; @@ -107,6 +165,13 @@ static int __init tdx_init(void) goto no_tdx; } + err = register_memory_notifier(&tdx_memory_nb); + if (err) { + pr_info("initialization failed: register_memory_notifier() failed (%d)\n", + err); + goto no_tdx; + } + tdx_guest_keyid_start = tdx_keyid_start; tdx_nr_guest_keyids = nr_tdx_keyids; @@ -316,6 +381,79 @@ static int tdx_get_sysinfo(struct tdsysinfo_struct *sysinfo, return 0; } +/* + * Add a memory region as a TDX memory block. The caller must make sure + * all memory regions are added in address ascending order and don't + * overlap. + */ +static int add_tdx_memblock(struct list_head *tmb_list, unsigned long start_pfn, + unsigned long end_pfn) +{ + struct tdx_memblock *tmb; + + tmb = kmalloc(sizeof(*tmb), GFP_KERNEL); + if (!tmb) + return -ENOMEM; + + INIT_LIST_HEAD(&tmb->list); + tmb->start_pfn = start_pfn; + tmb->end_pfn = end_pfn; + + /* @tmb_list is protected by mem_hotplug_lock */ + list_add_tail(&tmb->list, tmb_list); + return 0; +} + +static void free_tdx_memlist(struct list_head *tmb_list) +{ + /* @tmb_list is protected by mem_hotplug_lock */ + while (!list_empty(tmb_list)) { + struct tdx_memblock *tmb = list_first_entry(tmb_list, + struct tdx_memblock, list); + + list_del(&tmb->list); + kfree(tmb); + } +} + +/* + * Ensure that all memblock memory regions are convertible to TDX + * memory. Once this has been established, stash the memblock + * ranges off in a secondary structure because memblock is modified + * in memory hotplug while TDX memory regions are fixed. + */ +static int build_tdx_memlist(struct list_head *tmb_list) +{ + unsigned long start_pfn, end_pfn; + int i, ret; + + for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { + /* + * The first 1MB is not reported as TDX convertible memory. + * Although the first 1MB is always reserved and won't end up + * to the page allocator, it is still in memblock's memory + * regions. Skip them manually to exclude them as TDX memory. + */ + start_pfn = max(start_pfn, PHYS_PFN(SZ_1M)); + if (start_pfn >= end_pfn) + continue; + + /* + * Add the memory regions as TDX memory. The regions in + * memblock has already guaranteed they are in address + * ascending order and don't overlap. + */ + ret = add_tdx_memblock(tmb_list, start_pfn, end_pfn); + if (ret) + goto err; + } + + return 0; +err: + free_tdx_memlist(tmb_list); + return ret; +} + static int init_tdx_module(void) { static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, @@ -329,10 +467,25 @@ static int init_tdx_module(void) if (ret) return ret; + /* + * To keep things simple, assume that all TDX-protected memory + * will come from the page allocator. Make sure all pages in the + * page allocator are TDX-usable memory. + * + * Build the list of "TDX-usable" memory regions which cover all + * pages in the page allocator to guarantee that. Do it while + * holding mem_hotplug_lock read-lock as the memory hotplug code + * path reads the @tdx_memlist to reject any new memory. + */ + get_online_mems(); + + ret = build_tdx_memlist(&tdx_memlist); + if (ret) + goto out; + /* * TODO: * - * - Build the list of TDX-usable memory regions. * - Construct a list of "TD Memory Regions" (TDMRs) to cover * all TDX-usable memory regions. * - Configure the TDMRs and the global KeyID to the TDX module. @@ -341,7 +494,15 @@ static int init_tdx_module(void) * * Return error before all steps are done. */ - return -EINVAL; + ret = -EINVAL; +out: + /* + * @tdx_memlist is written here and read at memory hotplug time. + * Lock out memory hotplug code while building it. + */ + put_online_mems(); + + return ret; } static int __tdx_enable(void) diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 2f2d8737a364..6518024fcb68 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -101,6 +101,12 @@ enum tdx_module_status_t { TDX_MODULE_ERROR }; +struct tdx_memblock { + struct list_head list; + unsigned long start_pfn; + unsigned long end_pfn; +}; + struct tdx_module_output; u64 __seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, struct tdx_module_output *out); From patchwork Mon Mar 6 14:13:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id E36FDC678D4 for ; Mon, 6 Mar 2023 14:15:12 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 81F246B007B; Mon, 6 Mar 2023 09:15:12 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 7CF59280003; Mon, 6 Mar 2023 09:15:12 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 6974A280001; Mon, 6 Mar 2023 09:15:12 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id 56ECF6B007B for ; Mon, 6 Mar 2023 09:15:12 -0500 (EST) Received: from smtpin22.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 1B535140769 for ; Mon, 6 Mar 2023 14:15:12 +0000 (UTC) X-FDA: 80538670464.22.EFE41B3 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id D7680100014 for ; Mon, 6 Mar 2023 14:15:09 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=nyZxRpkf; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112110; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=lDhYDYbrr4vzRwExxSHjWH2qdzk7+g7qKc5v1MVJi8Q=; b=7zLD9crLMJ2+/rZwZBYkXDCG6/KsZN42E/dUGagz2jAGIkc8V1O6nHEIAzTEyW/xaR4+em GsdWh8UZ5Xet8ul08qhgLp5wOGVnvaqpKOgUknfBDzB8Ygq/CMgX8l5b3r+BXH4AOsOlCA jl4Xt6wUiRamJPKHcwRUs76ccRkIptM= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=nyZxRpkf; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112110; a=rsa-sha256; cv=none; b=Kyq1iFMpQsw8fY1xrxtzv48bfgwB2Gxrus73p772ooIN2Cnt0PQqMA5DUZip9onD+nwd4a ZEWFefPH45AdnBB76hP6V5YqILZy5AzT48Dst1jcRipBaooHys3KSVJDQPgHcNettFH/eJ 2z/0BBTaEb8oiOjAFwZ4ezQ+WSv9a6E= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112110; x=1709648110; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I1INrcXhvgOH6EWRozaxLzerjnfthFKl9cuiCzgEzug=; b=nyZxRpkfaB+0QEchKOfCwqSmD6dh+HgHrixEqsuEdbG/74RR3oxRjxY7 c65nJl3LSHvovLTlTadetS+ZNRphfwrUvCnFdBTeQna/dIUG8TDreZsRT ObSBLQxUYB0YEiceVrdhkfZKUN1oPV0BGvFhCgiqyLdn3kg3M6sNRpGI8 6a1ImkfqHxL+95rmlXCSPPXHYRvjpX81c4y8Y5Ibb8BaGMhpbkK2zTLsG 79Nvcp98OVecRVF2ju6BXPnwyfY39esJecf0t0J/o4JMWgSWDRDs3kBYd +rIJruweY3h4IdN40iHcMiy5vXhyqUAIHq1eJrsDMzDNK6lpH1fJNp5My A==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080171" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080171" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232182" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232182" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:04 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 08/16] x86/virt/tdx: Add placeholder to construct TDMRs to cover all TDX memory regions Date: Tue, 7 Mar 2023 03:13:53 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: D7680100014 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: gi94qm1xxms59pwzwb76wtrznpcwq5se X-HE-Tag: 1678112109-652352 X-HE-Meta: U2FsdGVkX19YeRccNw9DKHdXNVqbND264bIy2BDc4aIacraQ4MzVy+TMgfllzWNe/1pjv+4DF/1TB0as+sDG5eSiZ4v2rlJA3/UHAt4gRtwW2SFv37J+q/253YqoxHZBX7gKavFgjEbWJLJep60qI0HU2joje5g1vIDma/kZD/3BTCMon13eVbNCHg69lsZlNQy1SCxgDHCf10UALwFjdDZ9zBuvzqt5wG8nsmpe6z3JgwfHoDJGi6fMFrDQ25DNyEqJN+7dKu15TAxdaSjbQCzxKBOoyvlzwxkCt8r9MAPqlhy4xucSof5R6eGW49RZoZK8OPmXcbDZshXv2zHLtqm/m8k0wc93l2wgH4kw/vjz83/+8QBCIDD4nvGHjsPRz85M7/PbzSJVlWc8QGgx4yQu0ZiWF29Vhet3wM7lOiHJfTxQaxLr7bd9RCkBJV7NiCUGuhGH0KrTvrwTDiZ5OwEdd9bwCRzSQssOHp9snJexmJWn2mc+/yZhaGzlDgS9UfEB4I3QRZZQ9SPQSGbTYYK2tmEQ8zyzWLzO4Qdzp0AIk3S63ghjtXvJPsOb/CWylKzz+nEPAf+9Tf1xY9f5jDcmizfxPk3AIHu4BKjEpBgoB8NhpGd0UcyNWJwQwHjj/8F0npHAyIzIxRGvnDidzLikVYh/7POmIvThUydWmzhcG5BIhP7eNDTqsL1Xq1KhNNzDI0uViMqHcT9obqXZl2bkFI7LMbOD0KzscxELraJzIqmyUpo+2o3/gHFqfs8HhkogkWcERe7YwbUsEdZbwUsMZ4q24lxRxd+ZV2uRg/ZvYdMLB24sK0Q2nrJOkrgiS8vDXzMtZD2LDzacrNtWBGh2i7VlKrMQZJ62UIcHsCANyFS+akmWMXKhLyXg284nL/1OX9vQbRVk4cqX/PdWjMUARKaUzQjm+Qw9IBCIt8JjqRDHUk8P31rmnyb6NAbL7cCVXzSzA8+dybBj0KI ooHae7cM pPe5c6a2bph664E0AufzJWVFLWHppn85HtfYDA3wYJj6jwH0uWCMOOfxcfz7glQ957HVeFVy+GC6/ZTIYBNWsa942F/75IiGUdukZj+7P4XAFuljsx+hu45TXdTiY3JMmG9jTPe8ZvhP5jqLNxWn+ln5xsEHGjHfkBi0CCnLyMu3k6E8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: After the kernel selects all TDX-usable memory regions, the kernel needs to pass those regions to the TDX module via data structure "TD Memory Region" (TDMR). Add a placeholder to construct a list of TDMRs (in multiple steps) to cover all TDX-usable memory regions. === Long Version === TDX provides increased levels of memory confidentiality and integrity. This requires special hardware support for features like memory encryption and storage of memory integrity checksums. Not all memory satisfies these requirements. As a result, TDX introduced the concept of a "Convertible Memory Region" (CMR). During boot, the firmware builds a list of all of the memory ranges which can provide the TDX security guarantees. The list of these ranges is available to the kernel by querying the TDX module. The TDX architecture needs additional metadata to record things like which TD guest "owns" a given page of memory. This metadata essentially serves as the 'struct page' for the TDX module. The space for this metadata is not reserved by the hardware up front and must be allocated by the kernel and given to the TDX module. Since this metadata consumes space, the VMM can choose whether or not to allocate it for a given area of convertible memory. If it chooses not to, the memory cannot receive TDX protections and can not be used by TDX guests as private memory. For every memory region that the VMM wants to use as TDX memory, it sets up a "TD Memory Region" (TDMR). Each TDMR represents a physically contiguous convertible range and must also have its own physically contiguous metadata table, referred to as a Physical Address Metadata Table (PAMT), to track status for each page in the TDMR range. Unlike a CMR, each TDMR requires 1G granularity and alignment. To support physical RAM areas that don't meet those strict requirements, each TDMR permits a number of internal "reserved areas" which can be placed over memory holes. If PAMT metadata is placed within a TDMR it must be covered by one of these reserved areas. Let's summarize the concepts: CMR - Firmware-enumerated physical ranges that support TDX. CMRs are 4K aligned. TDMR - Physical address range which is chosen by the kernel to support TDX. 1G granularity and alignment required. Each TDMR has reserved areas where TDX memory holes and overlapping PAMTs can be represented. PAMT - Physically contiguous TDX metadata. One table for each page size per TDMR. Roughly 1/256th of TDMR in size. 256G TDMR = ~1G PAMT. As one step of initializing the TDX module, the kernel configures TDX-usable memory regions by passing a list of TDMRs to the TDX module. Constructing the list of TDMRs consists below steps: 1) Fill out TDMRs to cover all memory regions that the TDX module will use for TD memory. 2) Allocate and set up PAMT for each TDMR. 3) Designate reserved areas for each TDMR. Add a placeholder to construct TDMRs to do the above steps. To keep things simple, just allocate enough space to hold maximum number of TDMRs up front. Always free the space of the TDMRs after the module initialization (no matter successful or not) as TDMRs are only used during the module initialization. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - Changed the TDMR list from static variable back to local variable as now TDX module isn't disabled when tdx_cpu_enable() fails. v8 -> v9: - Changes around 'struct tdmr_info_list' (Dave): - Moved the declaration from tdx.c to tdx.h. - Renamed 'first_tdmr' to 'tdmrs'. - 'nr_tdmrs' -> 'nr_consumed_tdmrs'. - Changed 'tdmrs' to 'void *'. - Improved comments for all structure members. - Added a missing empty line in alloc_tdmr_list() (Dave). v7 -> v8: - Improved changelog to tell this is one step of "TODO list" in init_tdx_module(). - Other changelog improvement suggested by Dave (with "Create TDMRs" to "Fill out TDMRs" to align with the code). - Added a "TODO list" comment to lay out the steps to construct TDMRs, following the same idea of "TODO list" in tdx_module_init(). - Introduced 'struct tdmr_info_list' (Dave) - Further added additional members (tdmr_sz/max_tdmrs/nr_tdmrs) to simplify getting TDMR by given index, and reduce passing arguments around functions. - Added alloc_tdmr_list()/free_tdmr_list() accordingly, which internally uses tdmr_size_single() (Dave). - tdmr_num -> nr_tdmrs (Dave). v6 -> v7: - Improved commit message to explain 'int' overflow cannot happen in cal_tdmr_size() and alloc_tdmr_array(). -- Andy/Dave. v5 -> v6: - construct_tdmrs_memblock() -> construct_tdmrs() as 'tdx_memblock' is used instead of memblock. - Added Isaku's Reviewed-by. - v3 -> v5 (no feedback on v4): - Moved calculating TDMR size to this patch. - Changed to use alloc_pages_exact() to allocate buffer for all TDMRs once, instead of allocating each TDMR individually. - Removed "crypto protection" in the changelog. - -EFAULT -> -EINVAL in couple of places. --- arch/x86/virt/vmx/tdx/tdx.c | 98 ++++++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 32 ++++++++++++ 2 files changed, 128 insertions(+), 2 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 9149144cd7e7..2b87cedc7fce 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -454,6 +455,80 @@ static int build_tdx_memlist(struct list_head *tmb_list) return ret; } +/* Calculate the actual TDMR size */ +static int tdmr_size_single(u16 max_reserved_per_tdmr) +{ + int tdmr_sz; + + /* + * The actual size of TDMR depends on the maximum + * number of reserved areas. + */ + tdmr_sz = sizeof(struct tdmr_info); + tdmr_sz += sizeof(struct tdmr_reserved_area) * max_reserved_per_tdmr; + + return ALIGN(tdmr_sz, TDMR_INFO_ALIGNMENT); +} + +static int alloc_tdmr_list(struct tdmr_info_list *tdmr_list, + struct tdsysinfo_struct *sysinfo) +{ + size_t tdmr_sz, tdmr_array_sz; + void *tdmr_array; + + tdmr_sz = tdmr_size_single(sysinfo->max_reserved_per_tdmr); + tdmr_array_sz = tdmr_sz * sysinfo->max_tdmrs; + + /* + * To keep things simple, allocate all TDMRs together. + * The buffer needs to be physically contiguous to make + * sure each TDMR is physically contiguous. + */ + tdmr_array = alloc_pages_exact(tdmr_array_sz, + GFP_KERNEL | __GFP_ZERO); + if (!tdmr_array) + return -ENOMEM; + + tdmr_list->tdmrs = tdmr_array; + + /* + * Keep the size of TDMR to find the target TDMR + * at a given index in the TDMR list. + */ + tdmr_list->tdmr_sz = tdmr_sz; + tdmr_list->max_tdmrs = sysinfo->max_tdmrs; + tdmr_list->nr_consumed_tdmrs = 0; + + return 0; +} + +static void free_tdmr_list(struct tdmr_info_list *tdmr_list) +{ + free_pages_exact(tdmr_list->tdmrs, + tdmr_list->max_tdmrs * tdmr_list->tdmr_sz); +} + +/* + * Construct a list of TDMRs on the preallocated space in @tdmr_list + * to cover all TDX memory regions in @tmb_list based on the TDX module + * information in @sysinfo. + */ +static int construct_tdmrs(struct list_head *tmb_list, + struct tdmr_info_list *tdmr_list, + struct tdsysinfo_struct *sysinfo) +{ + /* + * TODO: + * + * - Fill out TDMRs to cover all TDX memory regions. + * - Allocate and set up PAMTs for each TDMR. + * - Designate reserved areas for each TDMR. + * + * Return -EINVAL until constructing TDMRs is done + */ + return -EINVAL; +} + static int init_tdx_module(void) { static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, @@ -461,6 +536,7 @@ static int init_tdx_module(void) static struct cmr_info cmr_array[MAX_CMRS] __aligned(CMR_INFO_ARRAY_ALIGNMENT); struct tdsysinfo_struct *sysinfo = &PADDED_STRUCT(tdsysinfo); + struct tdmr_info_list tdmr_list; int ret; ret = tdx_get_sysinfo(sysinfo, cmr_array); @@ -483,11 +559,19 @@ static int init_tdx_module(void) if (ret) goto out; + /* Allocate enough space for constructing TDMRs */ + ret = alloc_tdmr_list(&tdmr_list, sysinfo); + if (ret) + goto out_free_tdx_mem; + + /* Cover all TDX-usable memory regions in TDMRs */ + ret = construct_tdmrs(&tdx_memlist, &tdmr_list, sysinfo); + if (ret) + goto out_free_tdmrs; + /* * TODO: * - * - Construct a list of "TD Memory Regions" (TDMRs) to cover - * all TDX-usable memory regions. * - Configure the TDMRs and the global KeyID to the TDX module. * - Configure the global KeyID on all packages. * - Initialize all TDMRs. @@ -495,6 +579,16 @@ static int init_tdx_module(void) * Return error before all steps are done. */ ret = -EINVAL; +out_free_tdmrs: + /* + * Free the space for the TDMRs no matter the initialization is + * successful or not. They are not needed anymore after the + * module initialization. + */ + free_tdmr_list(&tdmr_list); +out_free_tdx_mem: + if (ret) + free_tdx_memlist(&tdx_memlist); out: /* * @tdx_memlist is written here and read at memory hotplug time. diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 6518024fcb68..3ad1e06be0f1 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -89,6 +89,29 @@ struct tdsysinfo_struct { DECLARE_FLEX_ARRAY(struct cpuid_config, cpuid_configs); } __packed; +struct tdmr_reserved_area { + u64 offset; + u64 size; +} __packed; + +#define TDMR_INFO_ALIGNMENT 512 + +struct tdmr_info { + u64 base; + u64 size; + u64 pamt_1g_base; + u64 pamt_1g_size; + u64 pamt_2m_base; + u64 pamt_2m_size; + u64 pamt_4k_base; + u64 pamt_4k_size; + /* + * Actual number of reserved areas depends on + * 'struct tdsysinfo_struct'::max_reserved_per_tdmr. + */ + DECLARE_FLEX_ARRAY(struct tdmr_reserved_area, reserved_areas); +} __packed __aligned(TDMR_INFO_ALIGNMENT); + /* * Do not put any hardware-defined TDX structure representations below * this comment! @@ -107,6 +130,15 @@ struct tdx_memblock { unsigned long end_pfn; }; +struct tdmr_info_list { + void *tdmrs; /* Flexible array to hold 'tdmr_info's */ + int nr_consumed_tdmrs; /* How many 'tdmr_info's are in use */ + + /* Metadata for finding target 'tdmr_info' and freeing @tdmrs */ + int tdmr_sz; /* Size of one 'tdmr_info' */ + int max_tdmrs; /* How many 'tdmr_info's are allocated */ +}; + struct tdx_module_output; u64 __seamcall(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, struct tdx_module_output *out); From patchwork Mon Mar 6 14:13:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D886C61DA4 for ; Mon, 6 Mar 2023 14:15:17 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 2A1CB6B0074; Mon, 6 Mar 2023 09:15:17 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 22A66280002; Mon, 6 Mar 2023 09:15:17 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 0F1C3280001; Mon, 6 Mar 2023 09:15:17 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id F3D7A6B0074 for ; Mon, 6 Mar 2023 09:15:16 -0500 (EST) Received: from smtpin16.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id AD87FAAD51 for ; Mon, 6 Mar 2023 14:15:16 +0000 (UTC) X-FDA: 80538670632.16.CD207D9 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 840DD10001F for ; Mon, 6 Mar 2023 14:15:14 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=mzciYKko; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112114; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=rRvrcRkKrkDPjou+CddV54bMQQrJvECJP13jmFVeVn0=; b=kq7+xprDRYNCGxl4+3yDzQy/GMUaXfRjlTuW0PInRzq1BGiHN0vpFnAAs5Ln1QcqIIx1b+ f6uAWJzwok0VtPNh5xS0c55BjjmICHlaYhvYM8buWW2MY71MbXabWuGBO2T+JTQC3iiecw YTpbDwdpKYWI2vdv8H+CdcvM+5iGRvU= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=mzciYKko; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112114; a=rsa-sha256; cv=none; b=PG9oOvhIFxQWzMV4KAM53kJQTw0airZl7C4cFZcP9MhFpO2g/1q/VT7ExxOhT0/VbqJhTZ KYux1GoOMKW9BCJw4zsDXqP4mRW8jI3tNEv+dRGlMoKqQ3KT36YHGuAAcToJdo/OZq5Mgm SZk7u85j301JswXZ+YcWSbucvm7LNH4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112114; x=1709648114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Og4X3jpditcgwnDVUk17+Xq7VjKqW/puuAFTfSPP8E0=; b=mzciYKkorxfCIxRbM1nLNA/7cBatK7O2jBs9AaPTS5/1rCdrlWbZwPoa oZFH0XnjEwPOGrK5WrGspnlKuBKcB1s9S3MZZr10kFdv6PPhbUIySs2Ds q0k0UIkY2OuokguYiM7h5s0YgpLdV1lvUBuoE+TrDDMd40+D71SBpPsiN 6zRsqAG36cFZWHWxGWpwUZV77GjWVeKUnCoM1xjlECTJDXbQqSYUq3LAD mlclQ3oHPZ/gw0PhOV1UgD34P+4OWgUVcGeqNXNyzzrbnkoUwfy4Tm24m jZc+z8sKo3fQ0U7yjXC3nBjbXl0VseePoVXlhKy1H5dVGzKBpVlRiQBY8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080203" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080203" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232254" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232254" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:09 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 09/16] x86/virt/tdx: Fill out TDMRs to cover all TDX memory regions Date: Tue, 7 Mar 2023 03:13:54 +1300 Message-Id: <0e200d3110d4f7fce9c569156c5ec4c94fd13c1c.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 840DD10001F X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: adnti6ckx5zwwdgqgbtejf3bqfs14ynm X-HE-Tag: 1678112114-993781 X-HE-Meta: U2FsdGVkX1+/Wx6leOCBI+6ge76M8+rofPBOHRV5e0v1n6z1qW8IwssEmfzvBAQjDU6wEs1qJJbwrvFUZeB4XxxzgHLOZN1aAM/WMB3lOrPu5kWSAfu8KBPmBp6x+jABKXqCRbt7TTEE+7awCEgo0pzjGsbDxlmHKcu8IHKp+6onO2CRYHxxX/M7Kc7zufSQ/XJw8ThsDLPB54Iw0rQd7/lmvboHdBf2G/B7SNNxbrXvouLttWE9mnHGHK7M/ge9P8lf3nzOyUfZgdm0g4D2uly288YtlbGvProeZjrRcPob+oMA/xZkU+O7Pd7wgh6TJ2YAjCP/LMgHBrkDdLsgp2oEFCQik5jmfXFfPzO4tUptzL/1hJLsG5q8UUJnU874EOBZhVA+aBppFXvput2nfqUHYPYBhwZe0rezg9AEdFTwKlaS/phdJVYpaHtOWMtAIawu0HjzhJdsTRvNwcuNXM9wmWWAmy+Oxyey7xnmLt7AO4bO5U3lnOocCyfq8nqTUVd2D0gkVQcuMO/njgGWz+/AJ1cy8fuSLAopnW6AomKkSxb+1qpSRAp4pltrbARq+Lc0R9XmbY5IdNfnRQCTUoPMQ6OS1hGzh6HKXcunYqsieAwttVXamc/teB7UMi/hYQC+jyXra7StMbt+cOn6cI16QUvEQQM4RUG/6HVVUQ0i0HLulUlxki+UN4UhHz27uNLnacxtUdabtPQOcxK8jEEopKIYnKoaiuXLLQpqG3TkI1jzExE9RHymTJxslArLbUJmXOxeKuPOsGy+Z/KqIQUY0V+dp4aotG/f8rROdmbkZMfn9giI8YWJS8d0fVPD5FatGczgDeLfKbnJwjwvA0gvfhFs4OOaOx25BdsT0/K1q1+MfeDmKYEYAdcSqw8n8wvHZMirWVujIEZdcYJE7W6/KOKpvqfiIEqMro96ArksoYx45qEroz6mmlv1HVzoE/aQeduCrCDwVN1cB1V wDQftkHZ JQuesHa8X8lHWgkSd0OdeMN8T7ed9gQgZgXbqnLglwMFkg7nxAtUrI72VIcfgzdVv5FKXVXUs5R6Rtq+zrQkHB0SngnGxae/2lRw8sX2I49a3gjq1nLOcV/h0ZJdek0vCJ/IwKJdE5g6zWOgWlb1yzwQb5n3FKDT+sYdB7ZWuEYHSCvU= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000004, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Start to transit out the "multi-steps" to construct a list of "TD Memory Regions" (TDMRs) to cover all TDX-usable memory regions. The kernel configures TDX-usable memory regions by passing a list of TDMRs "TD Memory Regions" (TDMRs) to the TDX module. Each TDMR contains the information of the base/size of a memory region, the base/size of the associated Physical Address Metadata Table (PAMT) and a list of reserved areas in the region. Do the first step to fill out a number of TDMRs to cover all TDX memory regions. To keep it simple, always try to use one TDMR for each memory region. As the first step only set up the base/size for each TDMR. Each TDMR must be 1G aligned and the size must be in 1G granularity. This implies that one TDMR could cover multiple memory regions. If a memory region spans the 1GB boundary and the former part is already covered by the previous TDMR, just use a new TDMR for the remaining part. TDX only supports a limited number of TDMRs. Disable TDX if all TDMRs are consumed but there is more memory region to cover. There are fancier things that could be done like trying to merge adjacent TDMRs. This would allow more pathological memory layouts to be supported. But, current systems are not even close to exhausting the existing TDMR resources in practice. For now, keep it simple. Signed-off-by: Kai Huang --- v9 -> v10: - No change. v8 -> v9: - Added the last paragraph in the changelog (Dave). - Removed unnecessary type cast in tdmr_entry() (Dave). --- arch/x86/virt/vmx/tdx/tdx.c | 94 ++++++++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 2b87cedc7fce..e2487d872bbd 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -508,6 +508,93 @@ static void free_tdmr_list(struct tdmr_info_list *tdmr_list) tdmr_list->max_tdmrs * tdmr_list->tdmr_sz); } +/* Get the TDMR from the list at the given index. */ +static struct tdmr_info *tdmr_entry(struct tdmr_info_list *tdmr_list, + int idx) +{ + int tdmr_info_offset = tdmr_list->tdmr_sz * idx; + + return (void *)tdmr_list->tdmrs + tdmr_info_offset; +} + +#define TDMR_ALIGNMENT BIT_ULL(30) +#define TDMR_PFN_ALIGNMENT (TDMR_ALIGNMENT >> PAGE_SHIFT) +#define TDMR_ALIGN_DOWN(_addr) ALIGN_DOWN((_addr), TDMR_ALIGNMENT) +#define TDMR_ALIGN_UP(_addr) ALIGN((_addr), TDMR_ALIGNMENT) + +static inline u64 tdmr_end(struct tdmr_info *tdmr) +{ + return tdmr->base + tdmr->size; +} + +/* + * Take the memory referenced in @tmb_list and populate the + * preallocated @tdmr_list, following all the special alignment + * and size rules for TDMR. + */ +static int fill_out_tdmrs(struct list_head *tmb_list, + struct tdmr_info_list *tdmr_list) +{ + struct tdx_memblock *tmb; + int tdmr_idx = 0; + + /* + * Loop over TDX memory regions and fill out TDMRs to cover them. + * To keep it simple, always try to use one TDMR to cover one + * memory region. + * + * In practice TDX1.0 supports 64 TDMRs, which is big enough to + * cover all memory regions in reality if the admin doesn't use + * 'memmap' to create a bunch of discrete memory regions. When + * there's a real problem, enhancement can be done to merge TDMRs + * to reduce the final number of TDMRs. + */ + list_for_each_entry(tmb, tmb_list, list) { + struct tdmr_info *tdmr = tdmr_entry(tdmr_list, tdmr_idx); + u64 start, end; + + start = TDMR_ALIGN_DOWN(PFN_PHYS(tmb->start_pfn)); + end = TDMR_ALIGN_UP(PFN_PHYS(tmb->end_pfn)); + + /* + * A valid size indicates the current TDMR has already + * been filled out to cover the previous memory region(s). + */ + if (tdmr->size) { + /* + * Loop to the next if the current memory region + * has already been fully covered. + */ + if (end <= tdmr_end(tdmr)) + continue; + + /* Otherwise, skip the already covered part. */ + if (start < tdmr_end(tdmr)) + start = tdmr_end(tdmr); + + /* + * Create a new TDMR to cover the current memory + * region, or the remaining part of it. + */ + tdmr_idx++; + if (tdmr_idx >= tdmr_list->max_tdmrs) { + pr_warn("initialization failed: TDMRs exhausted.\n"); + return -ENOSPC; + } + + tdmr = tdmr_entry(tdmr_list, tdmr_idx); + } + + tdmr->base = start; + tdmr->size = end - start; + } + + /* @tdmr_idx is always the index of last valid TDMR. */ + tdmr_list->nr_consumed_tdmrs = tdmr_idx + 1; + + return 0; +} + /* * Construct a list of TDMRs on the preallocated space in @tdmr_list * to cover all TDX memory regions in @tmb_list based on the TDX module @@ -517,10 +604,15 @@ static int construct_tdmrs(struct list_head *tmb_list, struct tdmr_info_list *tdmr_list, struct tdsysinfo_struct *sysinfo) { + int ret; + + ret = fill_out_tdmrs(tmb_list, tdmr_list); + if (ret) + return ret; + /* * TODO: * - * - Fill out TDMRs to cover all TDX memory regions. * - Allocate and set up PAMTs for each TDMR. * - Designate reserved areas for each TDMR. * From patchwork Mon Mar 6 14:13:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02F11C61DA4 for ; Mon, 6 Mar 2023 14:15:23 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9091B280001; Mon, 6 Mar 2023 09:15:22 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 8B95B6B007D; Mon, 6 Mar 2023 09:15:22 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 75A79280001; Mon, 6 Mar 2023 09:15:22 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id 66DA26B0073 for ; Mon, 6 Mar 2023 09:15:22 -0500 (EST) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id 7F3E0805B4 for ; Mon, 6 Mar 2023 14:15:21 +0000 (UTC) X-FDA: 80538670842.12.498DB2F Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 0BA11100012 for ; Mon, 6 Mar 2023 14:15:18 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Up/NlEfM"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112119; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=kak/guiFE8dgdyqdGfekIGXhM+hXQlJmRFreXhLT3PE=; b=oq6g6yrfWxjB6mNjBsoRaT9QyJC5JplgvXVrHwg+7G94b7h1RWT5xsCTDqkUXU3OUTLTfW uw2bI7leXRAW/96KPibqf1f4mOAZWHdwH/KZvcs8eSAk451spwzNbdTsQ+/L7T1TqwlaJX 6w53tBYLCoMgiZj5qntk/M35+0k3x5s= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Up/NlEfM"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112119; a=rsa-sha256; cv=none; b=XG08FPGOZabaKh1xY7VwKoCoTOdiIAae/zcifhjM9vY+55zdfFtSrxH1BUZwvlPsraGx41 jDkiy/31BYDaWW9K0lzWwOk/Uhh9p+vZCHm8ioEZD3WMs15J2ct+9DUcwSUW2scS8/JhcA GqkebqAjM0leSoJ8fassRzVgr24nFwo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112119; x=1709648119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M21Mc0wv/Yyyik1h3DFHTjShUnbWeAaSMp6r3waXybo=; b=Up/NlEfMWfLbUJ5WsRfAQWh1VGzTM4xkWvtTJJXhBFKGNgKteLPUKN3j FiBeoo2RCiFjxgq5UAPMSDsXdZ9KL4ekBNf2e5tpQ+rPKipD31wMGXP0f DJnBB5YKNwk7gF3Z5VTHPtGaeADRHEvzQymf6GhLmpOyfbjmxye/WnmTh fIekRE4tBYuFHgGxGPqGTKidREEd6Eo1SghvSJIlSznZBVNP/dIAliD/T zBqhQQ2p+fi8965/yi5P/81TlZ3jOqIZib21KISklfEpE/Re0zYhAWIjw NdnF2Hhtg2JsGB0FsRPc5GEw7OiPzz3+iOZbI3M2CobEEFxNGeB/m8viN g==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080225" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080225" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232322" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232322" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:14 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 10/16] x86/virt/tdx: Allocate and set up PAMTs for TDMRs Date: Tue, 7 Mar 2023 03:13:55 +1300 Message-Id: <5192c24339960c11dcedd42fecb5d49128bbe072.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 0BA11100012 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 78t3h1bk6r8uyzw58a9w11rtqz7j61zq X-HE-Tag: 1678112118-219273 X-HE-Meta: U2FsdGVkX19ZdSiTsTYqmn9t/qfWguFOpyyjjkpVIeVXBUp/H9fLb9vHKkFrJjZwC0oUfYW4vMZNuIHPaogN+BBwUAxhYt5+k0PqcFKElskzEPWJ7KYNCWv52xA4kTsyRSArshJ+VXRmOq7vqcpiDD1p4FJJKOyzbJnN17PXW3rrkFWknhIvhs8PuFbM3KrqbCEzOZscLKtnORBDMzdBD6Xu3PRrcQRJ+Oyz6m6qidXh4b+xN6X8RTA6PfchRNbA3r5bXYaAProg0GTu/S1/iHkcAa5v+mY3+Pfp4XXQlcyH51h9LQsB8vQEIFribjRbV5TVyNMr1RKQG3J40EuC6H2MlVyJdDoczIyl2Og2oHJWznta5kn7qX8aT1knpGa9fNR4seMHr6cu53enmvU/6MNNtUVrMwg5LRUPU7lXVcyR3sDSSe8HghN+xQSZlNjs2cS83701AXsNehRStqZB7vcE/KK5BJdzu6A6qrv9bC4h//uuI2/cQP2BTO7IyUAcr+3YnSZ+X2ZXR4FBaViagREea1QZGbV36rJI8kCj3xwbBajLvHOrzSOkW3AGiFQj1/XCcfgd72O/utzYALDlfRUcV1aiZPKzhG7x8i4jNSY17Oe8w7YGuVMpynz0VY5uD59h43NoqgprOJHsLUlCRSxbl/o8fIpdn8eOFHZYCOlYmZKgBph4Yjr/hn7GZ8RAgi4UYJAi/C6emQ0lvh5wJTcdvunx1ocnLB6g4WfhEBc2xvYr4olqthgb5IzLXstEQdHTAqc5Z+r6Tfkx3Z2BCmodzsrQxfexapHR246zbhvGmLqq7RlIFR8QqVHAJQonOjSnU3nv7dx8E/WPsjrmVUj57IV0+xlw/BHyUePvJ+iQNq3MlKw61CKCxDtk4jrCM1jRoCSG0iXJUg3LedofTN0810L9IRWDacjm4ZUR/WP1A7bh0C1GWDiHCTLjnrCr1Rf9yypkYs3N43L5+62 I/LEmLC8 ku6BB2HcdCqCbPYuocX2mZilJmn90wqG9wNGzk96LpM+imYdhm5PMzBji8GLFynBCN9fqztaKEv+faQxYxF3GvGiq3PzSPHS2FE4zyG0wW5PVYpc5KUR5Wx6Er+HC4l5VcX1tGx/Jeo0MlZs6hlPqmDNodzl3JdbnawwHA+5DQCtdVh8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The TDX module uses additional metadata to record things like which guest "owns" a given page of memory. This metadata, referred as Physical Address Metadata Table (PAMT), essentially serves as the 'struct page' for the TDX module. PAMTs are not reserved by hardware up front. They must be allocated by the kernel and then given to the TDX module during module initialization. TDX supports 3 page sizes: 4K, 2M, and 1G. Each "TD Memory Region" (TDMR) has 3 PAMTs to track the 3 supported page sizes. Each PAMT must be a physically contiguous area from a Convertible Memory Region (CMR). However, the PAMTs which track pages in one TDMR do not need to reside within that TDMR but can be anywhere in CMRs. If one PAMT overlaps with any TDMR, the overlapping part must be reported as a reserved area in that particular TDMR. Use alloc_contig_pages() since PAMT must be a physically contiguous area and it may be potentially large (~1/256th of the size of the given TDMR). The downside is alloc_contig_pages() may fail at runtime. One (bad) mitigation is to launch a TDX guest early during system boot to get those PAMTs allocated at early time, but the only way to fix is to add a boot option to allocate or reserve PAMTs during kernel boot. It is imperfect but will be improved on later. TDX only supports a limited number of reserved areas per TDMR to cover both PAMTs and memory holes within the given TDMR. If many PAMTs are allocated within a single TDMR, the reserved areas may not be sufficient to cover all of them. Adopt the following policies when allocating PAMTs for a given TDMR: - Allocate three PAMTs of the TDMR in one contiguous chunk to minimize the total number of reserved areas consumed for PAMTs. - Try to first allocate PAMT from the local node of the TDMR for better NUMA locality. Also dump out how many pages are allocated for PAMTs when the TDX module is initialized successfully. This helps answer the eternal "where did all my memory go?" questions. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata Reviewed-by: Dave Hansen --- v9 -> v10: - Removed code change in disable_tdx_module() as it doesn't exist anymore. v8 -> v9: - Added TDX_PS_NR macro instead of open-coding (Dave). - Better alignment of 'pamt_entry_size' in tdmr_set_up_pamt() (Dave). - Changed to print out PAMTs in "KBs" instead of "pages" (Dave). - Added Dave's Reviewed-by. v7 -> v8: (Dave) - Changelog: - Added a sentence to state PAMT allocation will be improved. - Others suggested by Dave. - Moved 'nid' of 'struct tdx_memblock' to this patch. - Improved comments around tdmr_get_nid(). - WARN_ON_ONCE() -> pr_warn() in tdmr_get_nid(). - Other changes due to 'struct tdmr_info_list'. v6 -> v7: - Changes due to using macros instead of 'enum' for TDX supported page sizes. v5 -> v6: - Rebase due to using 'tdx_memblock' instead of memblock. - 'int pamt_entry_nr' -> 'unsigned long nr_pamt_entries' (Dave/Sagis). - Improved comment around tdmr_get_nid() (Dave). - Improved comment in tdmr_set_up_pamt() around breaking the PAMT into PAMTs for 4K/2M/1G (Dave). - tdmrs_get_pamt_pages() -> tdmrs_count_pamt_pages() (Dave). - v3 -> v5 (no feedback on v4): - Used memblock to get the NUMA node for given TDMR. - Removed tdmr_get_pamt_sz() helper but use open-code instead. - Changed to use 'switch .. case..' for each TDX supported page size in tdmr_get_pamt_sz() (the original __tdmr_get_pamt_sz()). - Added printing out memory used for PAMT allocation when TDX module is initialized successfully. - Explained downside of alloc_contig_pages() in changelog. - Addressed other minor comments. --- arch/x86/Kconfig | 1 + arch/x86/virt/vmx/tdx/tdx.c | 216 +++++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 1 + 3 files changed, 213 insertions(+), 5 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f23bc540778a..2a4d4097c5e6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1959,6 +1959,7 @@ config INTEL_TDX_HOST depends on KVM_INTEL depends on X86_X2APIC select ARCH_KEEP_MEMBLOCK + depends on CONTIG_ALLOC help Intel Trust Domain Extensions (TDX) protects guest VMs from malicious host and certain physical attacks. This option enables necessary TDX diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index e2487d872bbd..8f66cab1902e 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -388,7 +388,7 @@ static int tdx_get_sysinfo(struct tdsysinfo_struct *sysinfo, * overlap. */ static int add_tdx_memblock(struct list_head *tmb_list, unsigned long start_pfn, - unsigned long end_pfn) + unsigned long end_pfn, int nid) { struct tdx_memblock *tmb; @@ -399,6 +399,7 @@ static int add_tdx_memblock(struct list_head *tmb_list, unsigned long start_pfn, INIT_LIST_HEAD(&tmb->list); tmb->start_pfn = start_pfn; tmb->end_pfn = end_pfn; + tmb->nid = nid; /* @tmb_list is protected by mem_hotplug_lock */ list_add_tail(&tmb->list, tmb_list); @@ -426,9 +427,9 @@ static void free_tdx_memlist(struct list_head *tmb_list) static int build_tdx_memlist(struct list_head *tmb_list) { unsigned long start_pfn, end_pfn; - int i, ret; + int i, nid, ret; - for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { + for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, &nid) { /* * The first 1MB is not reported as TDX convertible memory. * Although the first 1MB is always reserved and won't end up @@ -444,7 +445,7 @@ static int build_tdx_memlist(struct list_head *tmb_list) * memblock has already guaranteed they are in address * ascending order and don't overlap. */ - ret = add_tdx_memblock(tmb_list, start_pfn, end_pfn); + ret = add_tdx_memblock(tmb_list, start_pfn, end_pfn, nid); if (ret) goto err; } @@ -595,6 +596,202 @@ static int fill_out_tdmrs(struct list_head *tmb_list, return 0; } +/* + * Calculate PAMT size given a TDMR and a page size. The returned + * PAMT size is always aligned up to 4K page boundary. + */ +static unsigned long tdmr_get_pamt_sz(struct tdmr_info *tdmr, int pgsz, + u16 pamt_entry_size) +{ + unsigned long pamt_sz, nr_pamt_entries; + + switch (pgsz) { + case TDX_PS_4K: + nr_pamt_entries = tdmr->size >> PAGE_SHIFT; + break; + case TDX_PS_2M: + nr_pamt_entries = tdmr->size >> PMD_SHIFT; + break; + case TDX_PS_1G: + nr_pamt_entries = tdmr->size >> PUD_SHIFT; + break; + default: + WARN_ON_ONCE(1); + return 0; + } + + pamt_sz = nr_pamt_entries * pamt_entry_size; + /* TDX requires PAMT size must be 4K aligned */ + pamt_sz = ALIGN(pamt_sz, PAGE_SIZE); + + return pamt_sz; +} + +/* + * Locate a NUMA node which should hold the allocation of the @tdmr + * PAMT. This node will have some memory covered by the TDMR. The + * relative amount of memory covered is not considered. + */ +static int tdmr_get_nid(struct tdmr_info *tdmr, struct list_head *tmb_list) +{ + struct tdx_memblock *tmb; + + /* + * A TDMR must cover at least part of one TMB. That TMB will end + * after the TDMR begins. But, that TMB may have started before + * the TDMR. Find the next 'tmb' that _ends_ after this TDMR + * begins. Ignore 'tmb' start addresses. They are irrelevant. + */ + list_for_each_entry(tmb, tmb_list, list) { + if (tmb->end_pfn > PHYS_PFN(tdmr->base)) + return tmb->nid; + } + + /* + * Fall back to allocating the TDMR's metadata from node 0 when + * no TDX memory block can be found. This should never happen + * since TDMRs originate from TDX memory blocks. + */ + pr_warn("TDMR [0x%llx, 0x%llx): unable to find local NUMA node for PAMT allocation, fallback to use node 0.\n", + tdmr->base, tdmr_end(tdmr)); + return 0; +} + +#define TDX_PS_NR (TDX_PS_1G + 1) + +/* + * Allocate PAMTs from the local NUMA node of some memory in @tmb_list + * within @tdmr, and set up PAMTs for @tdmr. + */ +static int tdmr_set_up_pamt(struct tdmr_info *tdmr, + struct list_head *tmb_list, + u16 pamt_entry_size) +{ + unsigned long pamt_base[TDX_PS_NR]; + unsigned long pamt_size[TDX_PS_NR]; + unsigned long tdmr_pamt_base; + unsigned long tdmr_pamt_size; + struct page *pamt; + int pgsz, nid; + + nid = tdmr_get_nid(tdmr, tmb_list); + + /* + * Calculate the PAMT size for each TDX supported page size + * and the total PAMT size. + */ + tdmr_pamt_size = 0; + for (pgsz = TDX_PS_4K; pgsz <= TDX_PS_1G ; pgsz++) { + pamt_size[pgsz] = tdmr_get_pamt_sz(tdmr, pgsz, + pamt_entry_size); + tdmr_pamt_size += pamt_size[pgsz]; + } + + /* + * Allocate one chunk of physically contiguous memory for all + * PAMTs. This helps minimize the PAMT's use of reserved areas + * in overlapped TDMRs. + */ + pamt = alloc_contig_pages(tdmr_pamt_size >> PAGE_SHIFT, GFP_KERNEL, + nid, &node_online_map); + if (!pamt) + return -ENOMEM; + + /* + * Break the contiguous allocation back up into the + * individual PAMTs for each page size. + */ + tdmr_pamt_base = page_to_pfn(pamt) << PAGE_SHIFT; + for (pgsz = TDX_PS_4K; pgsz <= TDX_PS_1G; pgsz++) { + pamt_base[pgsz] = tdmr_pamt_base; + tdmr_pamt_base += pamt_size[pgsz]; + } + + tdmr->pamt_4k_base = pamt_base[TDX_PS_4K]; + tdmr->pamt_4k_size = pamt_size[TDX_PS_4K]; + tdmr->pamt_2m_base = pamt_base[TDX_PS_2M]; + tdmr->pamt_2m_size = pamt_size[TDX_PS_2M]; + tdmr->pamt_1g_base = pamt_base[TDX_PS_1G]; + tdmr->pamt_1g_size = pamt_size[TDX_PS_1G]; + + return 0; +} + +static void tdmr_get_pamt(struct tdmr_info *tdmr, unsigned long *pamt_pfn, + unsigned long *pamt_npages) +{ + unsigned long pamt_base, pamt_sz; + + /* + * The PAMT was allocated in one contiguous unit. The 4K PAMT + * should always point to the beginning of that allocation. + */ + pamt_base = tdmr->pamt_4k_base; + pamt_sz = tdmr->pamt_4k_size + tdmr->pamt_2m_size + tdmr->pamt_1g_size; + + *pamt_pfn = PHYS_PFN(pamt_base); + *pamt_npages = pamt_sz >> PAGE_SHIFT; +} + +static void tdmr_free_pamt(struct tdmr_info *tdmr) +{ + unsigned long pamt_pfn, pamt_npages; + + tdmr_get_pamt(tdmr, &pamt_pfn, &pamt_npages); + + /* Do nothing if PAMT hasn't been allocated for this TDMR */ + if (!pamt_npages) + return; + + if (WARN_ON_ONCE(!pamt_pfn)) + return; + + free_contig_range(pamt_pfn, pamt_npages); +} + +static void tdmrs_free_pamt_all(struct tdmr_info_list *tdmr_list) +{ + int i; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) + tdmr_free_pamt(tdmr_entry(tdmr_list, i)); +} + +/* Allocate and set up PAMTs for all TDMRs */ +static int tdmrs_set_up_pamt_all(struct tdmr_info_list *tdmr_list, + struct list_head *tmb_list, + u16 pamt_entry_size) +{ + int i, ret = 0; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) { + ret = tdmr_set_up_pamt(tdmr_entry(tdmr_list, i), tmb_list, + pamt_entry_size); + if (ret) + goto err; + } + + return 0; +err: + tdmrs_free_pamt_all(tdmr_list); + return ret; +} + +static unsigned long tdmrs_count_pamt_pages(struct tdmr_info_list *tdmr_list) +{ + unsigned long pamt_npages = 0; + int i; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) { + unsigned long pfn, npages; + + tdmr_get_pamt(tdmr_entry(tdmr_list, i), &pfn, &npages); + pamt_npages += npages; + } + + return pamt_npages; +} + /* * Construct a list of TDMRs on the preallocated space in @tdmr_list * to cover all TDX memory regions in @tmb_list based on the TDX module @@ -610,10 +807,13 @@ static int construct_tdmrs(struct list_head *tmb_list, if (ret) return ret; + ret = tdmrs_set_up_pamt_all(tdmr_list, tmb_list, + sysinfo->pamt_entry_size); + if (ret) + return ret; /* * TODO: * - * - Allocate and set up PAMTs for each TDMR. * - Designate reserved areas for each TDMR. * * Return -EINVAL until constructing TDMRs is done @@ -670,7 +870,13 @@ static int init_tdx_module(void) * * Return error before all steps are done. */ + ret = -EINVAL; + if (ret) + tdmrs_free_pamt_all(&tdmr_list); + else + pr_info("%lu KBs allocated for PAMT.\n", + tdmrs_count_pamt_pages(&tdmr_list) * 4); out_free_tdmrs: /* * Free the space for the TDMRs no matter the initialization is diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 3ad1e06be0f1..65fe34f21025 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -128,6 +128,7 @@ struct tdx_memblock { struct list_head list; unsigned long start_pfn; unsigned long end_pfn; + int nid; }; struct tdmr_info_list { From patchwork Mon Mar 6 14:13:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F64EC61DA4 for ; Mon, 6 Mar 2023 14:15:27 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9CD40280002; Mon, 6 Mar 2023 09:15:26 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 97CCB6B0073; Mon, 6 Mar 2023 09:15:26 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 81DA0280002; Mon, 6 Mar 2023 09:15:26 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 740916B0071 for ; Mon, 6 Mar 2023 09:15:26 -0500 (EST) Received: from smtpin02.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay04.hostedemail.com (Postfix) with ESMTP id 1A9BB1A06FA for ; Mon, 6 Mar 2023 14:15:26 +0000 (UTC) X-FDA: 80538671052.02.77498F7 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id A96F1100022 for ; Mon, 6 Mar 2023 14:15:23 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=XmkXFWrg; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112124; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=YRRma2OhPr390AGf4Gk3ep5P9W7KsdniIp6ESwb/ncE=; b=W9ZcEblvyCeL+16M7SzP4eKjHzmb4xLIiWZmczBx8BTpjR8b7kAXTFYzYYKYGLPMoiMJq/ MXG+a+/hZ01Acm1Bt4CWNCf/RA7gyOmSuV6ywUl+bY7lbKMMjpMBLKcCafhDhexmDoJZXE 5i6DXir0sTyubqJi4ndqfZh5BIE4LPg= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=XmkXFWrg; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112124; a=rsa-sha256; cv=none; b=RcnMIOJ9SEdodlPDB4tyYr2v82CcATcyyowbC0+cF+zfy57kwVtXPWlE2jf1qqaD8o6GBO UBcQ5d7uztJUKvo4xD7pt6dRx5XQzrC9WXdjwKY/LqWR5h+rAhB9APuOQwVjjpO4XZwI15 cUum69IkSqi4PpFZxQRgsAAHEWppstQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112123; x=1709648123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xci5WG0k+f/0Um3+k+Oe8afMa9mtUe76NlmilpanBT8=; b=XmkXFWrgd2P+iPI2OHyT9QTqkJZrY8T+6EaWApKzcNnqQ4kkZSpuQw6D VClOI+Bwx2ixFzOW3HvcTMH0Wj0UwkOP5IH6YFoNIIgN9mvkCJFO0cdXi AAjdQe8x8FWOuZCdkuRjzaIC8GXCHSofBNMMhXh6QvdULbGQicpPdfP/2 xZ2SqxjTw6Pd3a32tNyJRQfNjWm3wNwci/SYnxpxDRfKT4+EDVLETMnL3 rW5spVMjurL7UaB5Uklk0DOACYbxBSUteOPucdbAkPiTaaxKhQr8WZDd0 uF+T8NBaiVnR6AmqNbtiv2MvgVve1sTC4VZLVptW7iPa5RBwBV2Hlt2yy w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080240" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080240" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232434" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232434" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:18 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 11/16] x86/virt/tdx: Designate reserved areas for all TDMRs Date: Tue, 7 Mar 2023 03:13:56 +1300 Message-Id: <602d53e58b15d0593a489f59ef27953d6b2b0ece.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: A96F1100022 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 6tz96ybwbupybj7dptmcnwfo6axo4zq5 X-HE-Tag: 1678112123-21287 X-HE-Meta: U2FsdGVkX1/Lx3hZUqSvchUOsqInlWSQf9kwOaDEM6bPO67aqifU6FacszZA6RlHxw+jJ7ULmDuQUzhg3/UApwng+kb+Rm8baSSAvSw17hpXAKYAfUH78p96vL+xUI+f2iUcBajNt36ZntwPLWQFDXE5u9zeozcm3T4yX17eOzGK5DFc8WwkFYTX3VTf0Fb0cuN4jgeiIVWReVX4mukiyAVphX0y8Dcv1m1oCXWkUaRakY+lnveHYiFYTjqcRhk2lTBdhY/fyXRla0eyRO8OswQV4vWydiU7nkD5/t1l00C43WBL/KbMkf3QS27NLkm4G1gmwwg+LfwlNQ0hydtsdvZbOCpViYBeY6ftzB2rnpSqTPUfK68Ll+EhITY36/yPiOfO59r0+4TLpZe4tNgz0om2xeJ5EyKB9rRZ3CQwjGFqhRD7j2Kh8qbfTbXXHAxgcDubYMV3rxlb+j0KjZfNlaTcdLLbCe/zjI76LyYuyw5OYQe/Wgvs566KysK1vrv1tmOl/JuGKWuUeLyKRJO2VYlybo+ja8oMa8CQ2DX44IIp79HwHIh4KHZ+YoQIW18rbCGR03tbfbIG973aaf+FOVxPGwK7Gj3g5F03PUaYK/t1x4S+uq7FQpNvbCfl8GMkl0fzbzNMksZcZyiqBlOI8fPJ2h4abxaAYEoKPArLJA906x/MabfowNbytV0byelLRoOFE5MuzZKKbIlIbOElnTRSeUmCkV6dE9I/CXy+qGe+Jm+awAf6HZB/gweoJYUmUvP7kKy3iWWqxuK3+CIwRu+/BSKKdzGcaOA+Kpbus+XT/JAGY7HfAkxR/5aEfi6C4Pfqw0I+2PiyBvcRa1dodwLiixvxnQYWka1/ejC+n0a+U3SfqBSzhWzzzxAnNmJmk0RUWE/3/drl10KjUllqqwLbJmUJDIcpoQFmnh4qdYOTbmQCVTPwsaYRFZYyFu789lLrl97ooFfySO1g/OF 9YcAYLS9 HteI4sPgQmQ1tzbgj+oBIZXkG2MsKBoiBhhzSqNnsf0qyfFs2jtlffee5zkoXzh062VACerq94b3s/eyIHek1PTgLCnMpZQaUUsDhAsOrytXno6Jvi2S+tJcQgDpVsoo9OgVqj4L0yZDiU1+3ZLvKOZQbwqxSpD+yklFgZvJ431O7LKI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: As the last step of constructing TDMRs, populate reserved areas for all TDMRs. For each TDMR, put all memory holes within this TDMR to the reserved areas. And for all PAMTs which overlap with this TDMR, put all the overlapping parts to reserved areas too. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - No change. v8 -> v9: - Added comment around 'tdmr_add_rsvd_area()' to point out it doesn't do optimization to save reserved areas. (Dave). v7 -> v8: (Dave) - "set_up" -> "populate" in function name change (Dave). - Improved comment suggested by Dave. - Other changes due to 'struct tdmr_info_list'. v6 -> v7: - No change. v5 -> v6: - Rebase due to using 'tdx_memblock' instead of memblock. - Split tdmr_set_up_rsvd_areas() into two functions to handle memory hole and PAMT respectively. - Added Isaku's Reviewed-by. --- arch/x86/virt/vmx/tdx/tdx.c | 220 ++++++++++++++++++++++++++++++++++-- 1 file changed, 212 insertions(+), 8 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 8f66cab1902e..99d2e8d939d3 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -792,6 +793,210 @@ static unsigned long tdmrs_count_pamt_pages(struct tdmr_info_list *tdmr_list) return pamt_npages; } +static int tdmr_add_rsvd_area(struct tdmr_info *tdmr, int *p_idx, u64 addr, + u64 size, u16 max_reserved_per_tdmr) +{ + struct tdmr_reserved_area *rsvd_areas = tdmr->reserved_areas; + int idx = *p_idx; + + /* Reserved area must be 4K aligned in offset and size */ + if (WARN_ON(addr & ~PAGE_MASK || size & ~PAGE_MASK)) + return -EINVAL; + + if (idx >= max_reserved_per_tdmr) { + pr_warn("initialization failed: TDMR [0x%llx, 0x%llx): reserved areas exhausted.\n", + tdmr->base, tdmr_end(tdmr)); + return -ENOSPC; + } + + /* + * Consume one reserved area per call. Make no effort to + * optimize or reduce the number of reserved areas which are + * consumed by contiguous reserved areas, for instance. + */ + rsvd_areas[idx].offset = addr - tdmr->base; + rsvd_areas[idx].size = size; + + *p_idx = idx + 1; + + return 0; +} + +/* + * Go through @tmb_list to find holes between memory areas. If any of + * those holes fall within @tdmr, set up a TDMR reserved area to cover + * the hole. + */ +static int tdmr_populate_rsvd_holes(struct list_head *tmb_list, + struct tdmr_info *tdmr, + int *rsvd_idx, + u16 max_reserved_per_tdmr) +{ + struct tdx_memblock *tmb; + u64 prev_end; + int ret; + + /* + * Start looking for reserved blocks at the + * beginning of the TDMR. + */ + prev_end = tdmr->base; + list_for_each_entry(tmb, tmb_list, list) { + u64 start, end; + + start = PFN_PHYS(tmb->start_pfn); + end = PFN_PHYS(tmb->end_pfn); + + /* Break if this region is after the TDMR */ + if (start >= tdmr_end(tdmr)) + break; + + /* Exclude regions before this TDMR */ + if (end < tdmr->base) + continue; + + /* + * Skip over memory areas that + * have already been dealt with. + */ + if (start <= prev_end) { + prev_end = end; + continue; + } + + /* Add the hole before this region */ + ret = tdmr_add_rsvd_area(tdmr, rsvd_idx, prev_end, + start - prev_end, + max_reserved_per_tdmr); + if (ret) + return ret; + + prev_end = end; + } + + /* Add the hole after the last region if it exists. */ + if (prev_end < tdmr_end(tdmr)) { + ret = tdmr_add_rsvd_area(tdmr, rsvd_idx, prev_end, + tdmr_end(tdmr) - prev_end, + max_reserved_per_tdmr); + if (ret) + return ret; + } + + return 0; +} + +/* + * Go through @tdmr_list to find all PAMTs. If any of those PAMTs + * overlaps with @tdmr, set up a TDMR reserved area to cover the + * overlapping part. + */ +static int tdmr_populate_rsvd_pamts(struct tdmr_info_list *tdmr_list, + struct tdmr_info *tdmr, + int *rsvd_idx, + u16 max_reserved_per_tdmr) +{ + int i, ret; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) { + struct tdmr_info *tmp = tdmr_entry(tdmr_list, i); + unsigned long pamt_start_pfn, pamt_npages; + u64 pamt_start, pamt_end; + + tdmr_get_pamt(tmp, &pamt_start_pfn, &pamt_npages); + /* Each TDMR must already have PAMT allocated */ + WARN_ON_ONCE(!pamt_npages || !pamt_start_pfn); + + pamt_start = PFN_PHYS(pamt_start_pfn); + pamt_end = PFN_PHYS(pamt_start_pfn + pamt_npages); + + /* Skip PAMTs outside of the given TDMR */ + if ((pamt_end <= tdmr->base) || + (pamt_start >= tdmr_end(tdmr))) + continue; + + /* Only mark the part within the TDMR as reserved */ + if (pamt_start < tdmr->base) + pamt_start = tdmr->base; + if (pamt_end > tdmr_end(tdmr)) + pamt_end = tdmr_end(tdmr); + + ret = tdmr_add_rsvd_area(tdmr, rsvd_idx, pamt_start, + pamt_end - pamt_start, + max_reserved_per_tdmr); + if (ret) + return ret; + } + + return 0; +} + +/* Compare function called by sort() for TDMR reserved areas */ +static int rsvd_area_cmp_func(const void *a, const void *b) +{ + struct tdmr_reserved_area *r1 = (struct tdmr_reserved_area *)a; + struct tdmr_reserved_area *r2 = (struct tdmr_reserved_area *)b; + + if (r1->offset + r1->size <= r2->offset) + return -1; + if (r1->offset >= r2->offset + r2->size) + return 1; + + /* Reserved areas cannot overlap. The caller must guarantee. */ + WARN_ON_ONCE(1); + return -1; +} + +/* + * Populate reserved areas for the given @tdmr, including memory holes + * (via @tmb_list) and PAMTs (via @tdmr_list). + */ +static int tdmr_populate_rsvd_areas(struct tdmr_info *tdmr, + struct list_head *tmb_list, + struct tdmr_info_list *tdmr_list, + u16 max_reserved_per_tdmr) +{ + int ret, rsvd_idx = 0; + + ret = tdmr_populate_rsvd_holes(tmb_list, tdmr, &rsvd_idx, + max_reserved_per_tdmr); + if (ret) + return ret; + + ret = tdmr_populate_rsvd_pamts(tdmr_list, tdmr, &rsvd_idx, + max_reserved_per_tdmr); + if (ret) + return ret; + + /* TDX requires reserved areas listed in address ascending order */ + sort(tdmr->reserved_areas, rsvd_idx, sizeof(struct tdmr_reserved_area), + rsvd_area_cmp_func, NULL); + + return 0; +} + +/* + * Populate reserved areas for all TDMRs in @tdmr_list, including memory + * holes (via @tmb_list) and PAMTs. + */ +static int tdmrs_populate_rsvd_areas_all(struct tdmr_info_list *tdmr_list, + struct list_head *tmb_list, + u16 max_reserved_per_tdmr) +{ + int i; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) { + int ret; + + ret = tdmr_populate_rsvd_areas(tdmr_entry(tdmr_list, i), + tmb_list, tdmr_list, max_reserved_per_tdmr); + if (ret) + return ret; + } + + return 0; +} + /* * Construct a list of TDMRs on the preallocated space in @tdmr_list * to cover all TDX memory regions in @tmb_list based on the TDX module @@ -811,14 +1016,13 @@ static int construct_tdmrs(struct list_head *tmb_list, sysinfo->pamt_entry_size); if (ret) return ret; - /* - * TODO: - * - * - Designate reserved areas for each TDMR. - * - * Return -EINVAL until constructing TDMRs is done - */ - return -EINVAL; + + ret = tdmrs_populate_rsvd_areas_all(tdmr_list, tmb_list, + sysinfo->max_reserved_per_tdmr); + if (ret) + tdmrs_free_pamt_all(tdmr_list); + + return ret; } static int init_tdx_module(void) From patchwork Mon Mar 6 14:13:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AB42C678D4 for ; Mon, 6 Mar 2023 14:15:31 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id EAF86280003; Mon, 6 Mar 2023 09:15:30 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id E5EF66B0073; Mon, 6 Mar 2023 09:15:30 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id D26B9280003; Mon, 6 Mar 2023 09:15:30 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0016.hostedemail.com [216.40.44.16]) by kanga.kvack.org (Postfix) with ESMTP id C1F4D6B0071 for ; Mon, 6 Mar 2023 09:15:30 -0500 (EST) Received: from smtpin27.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 6241AAAD51 for ; Mon, 6 Mar 2023 14:15:30 +0000 (UTC) X-FDA: 80538671220.27.D8A487B Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 399AF100014 for ; Mon, 6 Mar 2023 14:15:28 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Fbd/sutP"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112128; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=u5vNtzDXOazhHJgMjKZtV05G28Ic8ScGqx4FkjZOidc=; b=poJqnHPqBpHkb68AqCJ+fL/Wn4Z7mpryE8OdTAkG4U0m8hOKP5l2bkm0mUsQq8FWst8Z0U DIZzCu7XtYgflnSaPDPbbHxI+6RJUYkFDoxTt+4VMqojQqSkdUxPcg5Mw+wRW0g5lWJAcI U4DhfmA+LYsJydrXPihfaKr2qz/+5Ww= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Fbd/sutP"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112128; a=rsa-sha256; cv=none; b=o8Q5iFl4rVNqq2TNjg2/PuFWvhJ/Eomsz91YEMnk3IzJmjTluO0w6R1aTqWLwyH0C5Y2O4 FFZeCHHI8jUSz84jsYRblkPua5W7vL37D3O004oruvfU0nU38wswAgCESqG7yr6SmG9IWD JRFxHCFSB3rYnzOwQzRtM6juhKQFaYE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112128; x=1709648128; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q2ZzkvRd96FY3VJXKPI1qSfLMJtLptSGiDgztHPFXG0=; b=Fbd/sutPnSpZBV9VuPtdqEPpTX/jep3A5Jtq6c/t24gHTwLYGAjLpxp8 AbMLNnMHq8bXbKUrAJzdGlghMZ34kTRHSNlCwxncG5ItMIBVjikwINI6p fh+yy+7EICp9WPfrj1+uEy3sbG/8Q4cL1K/hW2D32jpogVF60Jj4ju1b7 Zl3HfijklaN4YU7aZpTJhcLk7OyRX0fZ73xWLJSKovKxFjUewPQpabyGn vGGWHQS4dXPs5pSTU/mnORd+RLRuhBO26I7dLFEAI5HquLy+TNjBRQS77 B+qpor4XYLlCl0WCc86CVL/GybUY+pSwy0pjEUdOHLtfGh5r3RCBV9IRZ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080261" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080261" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232461" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232461" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:23 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 12/16] x86/virt/tdx: Configure TDX module with the TDMRs and global KeyID Date: Tue, 7 Mar 2023 03:13:57 +1300 Message-Id: <1685ddaf26d80bc356cfe0d0d571d142293bbd34.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 399AF100014 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: qftfpsdfifpjhnyzu7457sn7nrg8tb1z X-HE-Tag: 1678112128-804347 X-HE-Meta: U2FsdGVkX1/khO2p8sEsaM7RuD+AmZjMthOvjPM8PNi+U3/Oj/RMbO7ERsvQYI2WWtm2pwsFhXGJFZZzpQkl7GgJhsgU3iMBesWmKK93v9Wur0Jcv1wfy2t4Nz8LJjUwPnL5MetI848wePWG8gyCQzAGoNtB+y13cAywLNiuOgg2tgACy0f9oX2fkTWu308SMcJllve1lEFmRGsr9mAzGP982+gZpHYyYRGh+XuUJHnr2YFIstS7P41jDnqxVPlY9BJgY6SJhAEq5Y75e45MrsihUlsuailgIwoyDMp0zttnm120ceEKsnIlixNLToR0u7PDb8GPSbngQAL/tHnAwB8gbRDyPeDASx1imEQX0aL2gRxPw27AxuWxdFbHPehP+OGLstLVvz7ofgwlOGvYfbUXfCMDAYVX8cC8wVVJL56Bzy4s6rlO0g7AVQRd+Mp4DiBNskk30agtiUccMO/IZRxwIGQbUPKD24OXwqj2j4kUDhqnZG4oPtfWETWWjtC2gPfNqG6alYVK2S1jdgvLEeDMQs83wKmHzyKFSGabPsINm4oE8yIqkzRf2Y2Vs6+E6yOrs0hT2XLEjxhIuhTysyMllRP5WA1cu1dt6qZ4y4gEr2vfdH/rKySapNvJC2aO62SBz3Jx8qtJibTe8+X0Z2vMWREMxcbFf5egx836hcbSYfNaIc+o4QQdhWIm6w8wNQ6DPTxE1hXAxTUXKcM4xdYJgio4zzn/afE05baHd+YBcRpwh7QfjHEST+y7g+ltQ4xX0aOyIQSFXsz0o721y9sjG4Z73sI48re8AII/nE8ac1y9bXWyMQHr4W7BZPFI9MHzOPgUNE7Q9Z/X4X8aWI6jb3bnhEUGlU0wq+82tW5E2grXQb8avRAnqKBl5lA4f/8XfwzLkUvCdPHRIIyEbFDN6WdBiYnUeQimg1UAZkXB+0ETGVSONEI6SqWq5F13CxOo1zlP1mSICZ6I6HY fXGTiGEn WdwTYeus4VyLze+3bvEfjIxz3KlaKNk3DwtUcuGLqqR1IOT1vDD7OSYp4ufGjEKrNkFP72w2w8FmmhN4j+Uq/i9p2lyYpLorpPSgbYo1bFEIdUlo+WO4gZa7QrQDEmosXYJ4AeKFYlaRJfzhBwTUlhbKWh1BLqLSG+AUE0fPnbLZ65X0= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The TDX module uses a private KeyID as the "global KeyID" for mapping things like the PAMT and other TDX metadata. This KeyID has already been reserved when detecting TDX during the kernel early boot. After the list of "TD Memory Regions" (TDMRs) has been constructed to cover all TDX-usable memory regions, the next step is to pass them to the TDX module together with the global KeyID. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - Code change due to change static 'tdx_tdmr_list' to local 'tdmr_list'. v8 -> v9: - Removed 'i.e.' in changelog and removed the passive voice (Dave). - Improved changelog (Dave). - Changed the way to allocate aligned PA array (Dave). - Moved reserving the TDX global KeyID to the second patch, and also changed 'tdx_keyid_start' and 'nr_tdx_keyid' to guest's KeyIDs in that patch (Dave). v7 -> v8: - Merged "Reserve TDX module global KeyID" patch to this patch, and removed 'tdx_global_keyid' but use 'tdx_keyid_start' directly. - Changed changelog accordingly. - Changed how to allocate aligned array (Dave). --- arch/x86/virt/vmx/tdx/tdx.c | 41 ++++++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 2 ++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 99d2e8d939d3..28562cf88414 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1025,6 +1026,39 @@ static int construct_tdmrs(struct list_head *tmb_list, return ret; } +static int config_tdx_module(struct tdmr_info_list *tdmr_list, u64 global_keyid) +{ + u64 *tdmr_pa_array; + size_t array_sz; + int i, ret; + + /* + * TDMRs are passed to the TDX module via an array of physical + * addresses of each TDMR. The array itself also has certain + * alignment requirement. + */ + array_sz = tdmr_list->nr_consumed_tdmrs * sizeof(u64); + array_sz = roundup_pow_of_two(array_sz); + if (array_sz < TDMR_INFO_PA_ARRAY_ALIGNMENT) + array_sz = TDMR_INFO_PA_ARRAY_ALIGNMENT; + + tdmr_pa_array = kzalloc(array_sz, GFP_KERNEL); + if (!tdmr_pa_array) + return -ENOMEM; + + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) + tdmr_pa_array[i] = __pa(tdmr_entry(tdmr_list, i)); + + ret = seamcall(TDH_SYS_CONFIG, __pa(tdmr_pa_array), + tdmr_list->nr_consumed_tdmrs, + global_keyid, 0, NULL, NULL); + + /* Free the array as it is not required anymore. */ + kfree(tdmr_pa_array); + + return ret; +} + static int init_tdx_module(void) { static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, @@ -1065,10 +1099,14 @@ static int init_tdx_module(void) if (ret) goto out_free_tdmrs; + /* Pass the TDMRs and the global KeyID to the TDX module */ + ret = config_tdx_module(&tdmr_list, tdx_global_keyid); + if (ret) + goto out_free_pamts; + /* * TODO: * - * - Configure the TDMRs and the global KeyID to the TDX module. * - Configure the global KeyID on all packages. * - Initialize all TDMRs. * @@ -1076,6 +1114,7 @@ static int init_tdx_module(void) */ ret = -EINVAL; +out_free_pamts: if (ret) tdmrs_free_pamt_all(&tdmr_list); else diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 65fe34f21025..6cab15184af5 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -19,6 +19,7 @@ #define TDH_SYS_INIT 33 #define TDH_SYS_LP_INIT 35 #define TDH_SYS_INFO 32 +#define TDH_SYS_CONFIG 45 struct cmr_info { u64 base; @@ -95,6 +96,7 @@ struct tdmr_reserved_area { } __packed; #define TDMR_INFO_ALIGNMENT 512 +#define TDMR_INFO_PA_ARRAY_ALIGNMENT 512 struct tdmr_info { u64 base; From patchwork Mon Mar 6 14:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F98AC61DA4 for ; Mon, 6 Mar 2023 14:15:36 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id EFD4A280004; Mon, 6 Mar 2023 09:15:35 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id EAFF96B0073; Mon, 6 Mar 2023 09:15:35 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id D7547280004; Mon, 6 Mar 2023 09:15:35 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id C46896B0071 for ; Mon, 6 Mar 2023 09:15:35 -0500 (EST) Received: from smtpin17.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 5F5691C5DA3 for ; Mon, 6 Mar 2023 14:15:35 +0000 (UTC) X-FDA: 80538671430.17.C27BC2C Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 0EE07100025 for ; Mon, 6 Mar 2023 14:15:32 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=P8w9SrHT; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112133; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=+Vc/PhdM024zJUXxCSh1JLWswFpOBxlvvWHvALWUrCE=; b=gHKK/jmWBuGc0lQEcJ7UKClQWZL5g57GrH1RxA/J/FNZ/jjsfXuNtZzBZf30DvgpkIv/qB 1BoHu/q9AqAtd7Zh7x9Yf03td+nignb3E+S2jjE8lltSq47L/HOfIU36qh+kOBb4/Evu34 oGohRrA+3T1AOlNfRLd71vtzzM0dXxc= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=P8w9SrHT; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112133; a=rsa-sha256; cv=none; b=VkCH6cCLlRuDTGMrng4LFtY68nxpP6ACaeY64O5yfQWH+IuRdzxruvUoCHt+QRWKZ1GOiF 8W41ZRqFlfXSV0cxmJiN6V56rsrWWTf8XLJ2d0WIalcoPpa08JfKZi6KHZ9BstXHjJ6WEW x4pHvBfgo5WzgBVQ7xJQ7/q4odowLtc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112133; x=1709648133; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyIxSyvqxe/Ll/ub5N3wAG+yNxCYWUHwwuM+uOyiu2c=; b=P8w9SrHTLz/7xsAa4sOx9+004a6h4BNmQl3hBj49b+aJqUqUYvnVG2Jz zvVZ1EjQChTrBVdOtlY1jfHk5ZYoE9fEOB0XBwMWcbCPtWqHNlhvxXCwj NzzopFtJxD8jo76K3zlnxoVNa0Wbse+ZzJjuUVYQLevirvMUF2bFozO96 Ahjt3w3uDMiBdVZy5ndDPZ4Xnakbks9UmGBOQjXhliFDRfM71JSPzG0SJ GqMWp7BFuPe+Y9DUT7s/TdvmJNgS2fibTuLbQkCdxkWd7P1EFSrVql/2D hlOeIx13Hqvicyw8GmYjf351FcB1sFcm3CRdehURF0XGJo/Z43bcuLMex A==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080280" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080280" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232484" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232484" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:27 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 13/16] x86/virt/tdx: Configure global KeyID on all packages Date: Tue, 7 Mar 2023 03:13:58 +1300 Message-Id: <857bc698517a66d45ef85d38efbbfb4e715bb77b.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 0EE07100025 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: wz5t8x8z6qu4xs5hnzq38bw7ykrncrpm X-HE-Tag: 1678112132-456723 X-HE-Meta: U2FsdGVkX182w/WSor3pUwCGGpmLC/hDRNG3qrC/fDZDdmu6tR6fgNkpGyUFTlngdkuYmQshj108luQp7W35m06SYMYtMAsennkrMTTFS1YI0PrHHZ1VTqaUORQFpCVVqAJBgEaaePvRImTC/LwROTF8m2srHT9wvln0Xa0/i8xN92OJLg2c9gsXW4QdjQ7JXr8Slm8g14H/qQxrlMvC6QIaZmfw3Kz8/VIhoUZsx6VVCHms9nbDYnXZftKjoy/PiyQbek+brpDANB7+HS/ngxwX0k5dVDyNRYc1n0dZhPYwow2Pnl3omCloD8qqEgj2m1TAQRMRQW0jUOdCfaPAgawX0yHCMovg2LEhnqAxqZFMm0UA7RtNDI730xL9zwNWzKk7B9sqK5kzIz2IMnlUWpHZSuMy9Kl0GKMr5L+9gn7YcncatsLBH1jaLXI6jfChKA69GKvZ+gKR1mlcPeAQZ2DVRXkz1Ml5au+HpZDDsc3l1BJmPetJOrKoqPLsd2nrNnNKNg3jF4JoVvJnaqZOkox6wO2LN9oMc423yM5mtQxmMViRUXtSeBUbyGtq7eD6l8FCGeFAV7HnDn7O1tKODj6uh2QgZ6DgnrtE4oJJ/JiiWzY+p1XMa7xITMYoOdA47H4EmXRtT5oLxapIjUylAadWCqRxPgepe2/Wj67086Tze5RD/RAfzBBIZuCL2f+KUm8lIErYcW7oVQPxfd08VIEfN5rYVaS0ckCXMSRi4vPRSemZjYfo56A9ayr+1DVQhkqFTgUl9mvMerA1QeLWETsXaADSPGcX/bqry4Taxeg9nvPM6QyA4TvB8WV681/8Tepz2uQhYq6H+Q65VV2gtG1lO7RpKi6aVt+c4jjQXRcfn7zlRm/2Ls2kJ0IttbGDcIbo1RaAmdpgDZkEIFrrDjocdZC105bJ8V5bLiFYY/DkZzMlLl9K7kzXMuljV/FPbC2RvnIAxDfFLcDtrYp HDXBCPsQ f/HTweSf0wlnVIPVgeT923BzPsZADoFnbBvOm2QCr9j4XQZHVDGWayLE0iDhps6yAKD4gFFtNKd5QOa7mzI7BuFL6iTjJP4E+KgqmT5RkTIg7yJuDvefKtWDDjFpHmDzcwaVyeh30+Un/sV2KDzHQ1Q0cm0WMU8FrWYABmRr56qTwlNE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: After the list of TDMRs and the global KeyID are configured to the TDX module, the kernel needs to configure the key of the global KeyID on all packages using TDH.SYS.KEY.CONFIG. Just use the helper, which conditionally calls function on all online cpus, to configure the global KeyID on all packages. Loop all online cpus, keep track which packages have been called and skip all cpus for those already called packages. To keep things simple, this implementation takes no affirmative steps to online cpus to make sure there's at least one cpu for each package. The callers (aka. KVM) can ensure success by ensuring that. Intel hardware doesn't guarantee cache coherency across different KeyIDs. The PAMTs are transitioning from being used by the kernel mapping (KeyId 0) to the TDX module's "global KeyID" mapping. This means that the kernel must flush any dirty KeyID-0 PAMT cachelines before the TDX module uses the global KeyID to access the PAMT. Otherwise, if those dirty cachelines were written back, they would corrupt the TDX module's metadata. Aside: This corruption would be detected by the memory integrity hardware on the next read of the memory with the global KeyID. The result would likely be fatal to the system but would not impact TDX security. Following the TDX module specification, flush cache before configuring the global KeyID on all packages. Given the PAMT size can be large (~1/256th of system RAM), just use WBINVD on all CPUs to flush. Note if any TDH.SYS.KEY.CONFIG fails, the TDX module may already have used the global KeyID to write any PAMT. Therefore, use WBINVD to flush cache before freeing the PAMTs back to the kernel. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - Changed to use 'smp_call_on_cpu()' directly to do key configuration. v8 -> v9: - Improved changelog (Dave). - Improved comments to explain the function to configure global KeyID "takes no affirmative action to online any cpu". (Dave). - Improved other comments suggested by Dave. v7 -> v8: (Dave) - Changelog changes: - Point out this is the step of "multi-steps" of init_tdx_module(). - Removed MOVDIR64B part. - Other changes due to removing TDH.SYS.SHUTDOWN and TDH.SYS.LP.INIT. - Changed to loop over online cpus and use smp_call_function_single() directly as the patch to shut down TDX module has been removed. - Removed MOVDIR64B part in comment. v6 -> v7: - Improved changelong and comment to explain why MOVDIR64B isn't used when returning PAMTs back to the kernel. --- arch/x86/virt/vmx/tdx/tdx.c | 80 ++++++++++++++++++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 1 + 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 28562cf88414..0a3b3374c5cb 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -1059,6 +1059,55 @@ static int config_tdx_module(struct tdmr_info_list *tdmr_list, u64 global_keyid) return ret; } +static int do_global_key_config(void *data) +{ + /* + * TDH.SYS.KEY.CONFIG may fail with entropy error (which is a + * recoverable error). Assume this is exceedingly rare and + * just return error if encountered instead of retrying. + * + * All '0's are just unused parameters. + */ + return seamcall(TDH_SYS_KEY_CONFIG, 0, 0, 0, 0, NULL, NULL); +} + +/* + * Attempt to configure the global KeyID on all physical packages. + * + * This requires running code on at least one CPU in each package. If a + * package has no online CPUs, that code will not run and TDX module + * initialization (TDMR initialization) will fail. + * + * This code takes no affirmative steps to online CPUs. Callers (aka. + * KVM) can ensure success by ensuring sufficient CPUs are online for + * this to succeed. + */ +static int config_global_keyid(void) +{ + cpumask_var_t packages; + int cpu, ret = -EINVAL; + + if (!zalloc_cpumask_var(&packages, GFP_KERNEL)) + return -ENOMEM; + + for_each_online_cpu(cpu) { + if (cpumask_test_and_set_cpu(topology_physical_package_id(cpu), + packages)) + continue; + + /* + * TDH.SYS.KEY.CONFIG cannot run concurrently on + * different cpus, so just do it one by one. + */ + ret = smp_call_on_cpu(cpu, do_global_key_config, NULL, true); + if (ret) + break; + } + + free_cpumask_var(packages); + return ret; +} + static int init_tdx_module(void) { static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, @@ -1104,10 +1153,24 @@ static int init_tdx_module(void) if (ret) goto out_free_pamts; + /* + * Hardware doesn't guarantee cache coherency across different + * KeyIDs. The kernel needs to flush PAMT's dirty cachelines + * (associated with KeyID 0) before the TDX module can use the + * global KeyID to access the PAMT. Given PAMTs are potentially + * large (~1/256th of system RAM), just use WBINVD on all cpus + * to flush the cache. + */ + wbinvd_on_all_cpus(); + + /* Config the key of global KeyID on all packages */ + ret = config_global_keyid(); + if (ret) + goto out_free_pamts; + /* * TODO: * - * - Configure the global KeyID on all packages. * - Initialize all TDMRs. * * Return error before all steps are done. @@ -1115,8 +1178,18 @@ static int init_tdx_module(void) ret = -EINVAL; out_free_pamts: - if (ret) + if (ret) { + /* + * Part of PAMT may already have been initialized by the + * TDX module. Flush cache before returning PAMT back + * to the kernel. + * + * No need to worry about integrity checks here. KeyID + * 0 has integrity checking disabled. + */ + wbinvd_on_all_cpus(); tdmrs_free_pamt_all(&tdmr_list); + } else pr_info("%lu KBs allocated for PAMT.\n", tdmrs_count_pamt_pages(&tdmr_list) * 4); @@ -1168,6 +1241,9 @@ static int __tdx_enable(void) * lock to prevent any new cpu from becoming online; 2) done both VMXON * and tdx_cpu_enable() on all online cpus. * + * This function requires there's at least one online cpu for each CPU + * package to succeed. + * * This function can be called in parallel by multiple callers. * * Return 0 if TDX is enabled successfully, otherwise error. diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 6cab15184af5..880e90dedb3f 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -20,6 +20,7 @@ #define TDH_SYS_LP_INIT 35 #define TDH_SYS_INFO 32 #define TDH_SYS_CONFIG 45 +#define TDH_SYS_KEY_CONFIG 31 struct cmr_info { u64 base; From patchwork Mon Mar 6 14:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93DF9C678D4 for ; Mon, 6 Mar 2023 14:15:42 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 38A826B0073; Mon, 6 Mar 2023 09:15:42 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 33B2A280007; Mon, 6 Mar 2023 09:15:42 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 202DC280005; Mon, 6 Mar 2023 09:15:42 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 0DDB36B0073 for ; Mon, 6 Mar 2023 09:15:42 -0500 (EST) Received: from smtpin18.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id A1D84C01A2 for ; Mon, 6 Mar 2023 14:15:41 +0000 (UTC) X-FDA: 80538671682.18.45A3C04 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 8D14E10000C for ; Mon, 6 Mar 2023 14:15:39 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=QTpprzmK; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112139; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=82UsUEXgm4/KQKJbveyF1q6egiYV3ZKoqLprAH6FkFw=; b=sL9feBYQcK4rrDadr6OrNiYjla9r/jdt/osx+R+cy9x0RTWluWOzsNalRrWyEdsUFQRG9H wc8+lfDlt6iid3X/MF0VXjUiqdmbEnp+Ucn0o+yUCJgTLg44TBYZZD4oN2BKkfvtEziLk4 5oVK2SVdk0b83TPUmTnUJDn/a3GUti8= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=QTpprzmK; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112139; a=rsa-sha256; cv=none; b=vBxgVUE183PVX3+QhnzTrX83jZr1uOkWtzNrVVEhS0WucdvC6XPiSNCCmvDKru38BZs+pw 8SWajXcgA96hW9AKLn/Z1ki2P0Q7vQEW8uzJvBaYE+ZCc9GnfUgKL+roHXzam1dnluAvYZ onibyMsidd8Yg4UFp1d3GJIq+fPWepI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112139; x=1709648139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zHYj/4Y5tzqrg8Uf+TD7J7htjEWwNRrJOSQ2jhIx+Zo=; b=QTpprzmKUUruigHe057z1FSUwg0cAgX0989zKfKs9GPLpLnBwN11TNPP UF4pzsBFJv+V+JXHDMFPfuFzX/OuLWqcoXYHdorrpU66uufmjjmHUgwDf hnvxZ3HZ8/7w5GKMieU2oaDymlLbdLnpkOinUTWQ98GtFETaQhG5Uzxcz pYPghD3OJKhbS1k2cOtUzQDZm/sin3RY41A2y6H0HhYhT5bwL3x53rxhV CgSJiuoFFUPn49wIQ+00I8vq7cT9eHxjW00nr8B0tUMmXulYxWpArtziH 86myZlQHSspgFmXE4IA5/s+mbUaX+etk9JugFZqxZKphN1vkowJTDXR7A A==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080309" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080309" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232506" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232506" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:32 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 14/16] x86/virt/tdx: Initialize all TDMRs Date: Tue, 7 Mar 2023 03:13:59 +1300 Message-Id: <7cee98d35f9d613e2dcaa86cd69b28583d2e2ee7.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 8D14E10000C X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: zrzkpqyhmc847jwmgin8knb9p1tp8ocq X-HE-Tag: 1678112139-550198 X-HE-Meta: U2FsdGVkX1+54B4oW3SXaqUe7jJcSQNZXjCilzYeH5CiCLTX6alT3AgYGt7R0Q193AXvs5FRIWZmLqyw0tv8nwxw9BtOKkaC7Vwiy4CXO/Lau7DCPtHK2Yud3Okcwubgyv6Bt6mcIQmCJYEwIJ7PFMRav2LMrZqmDCNCs+CgPZGSLJOIgh5kShoSWVb/A6mTPzBC2ZEvHE9StmUcQdeXugLS5bYMMCzNzOo0/5Qxn0Fm0Pc0SwNQYXi5ZLKbqqNXMpnshYAmTGXz+KkVyAqy+Z3T5GJu1Ceyy4WLL2TMuSANR0sL46oOfjCU0av9qAV0ujnUiiwbAZUOjzsO1khrWI8WLtJFdEJIh3+Or4lnibx4M5/JSRqDr1dOdSxih5oyVWmdsko6eYqDUethVal+vD8l0r+77JzIKnTAWMj3J0RO5oiMjQeBqF1GpF09B7QsExhhRBankzR/Ni8xdbv3bhZZXhz8c1HDZ/bOgT+IJSDQ64K0jLWwOI0nK7SiJo4L8t8A6YuHhBzYnx8cIMy6sWoz84zg5rMPyEvpRt5AvSFBd7JxFO6rswI07FOZjbqbAFzLhjY8pwBsi3C3WbjW8EqaL0aQN0LH50Mos/7Fntit1yN2XUXbdLJns2jQBXtYA15ANj4F8HuNUWPTm2kWGnJiRZ7RvYM2oStzEIPuru48F5crHrDVxCmvW2fbwyf18LpZW2RmAGWZIVa+ZnTUev8PMSdKC4vkmeS8p+jE9fSLgFsBSyY60/b9TfSttP0+pHbwi72iBhl3vBejfPPSG+hPCNsQZkBbOfD2sYx8h3Pz59Hbq66tPCOPYoARjJsAsLVIOmDABafiUOkUtgNj5c65Gl6uNHGF2xFGzL42x8CQHnuCN4ntXdS7/AP51el33emOI16TlCubi7fuX3J3Bb/AziwlAX+nkAGH2xoEC33LR00GH1Pke9BGz+ESBcVvkDkHhifGPdNzw/wSNtR uc6TwJai CvN+1DYraoBLmkfcrTjo5mjK1ynWsDyH3nPJ3NQVym5e1tiV0NPUJg4CMcVbsBt1tpB7dxwEiNGhVcVNf1laieao5mLKxVEmpeLIMUFzfOu3iMHKMpGKueC65CzAw5OIgpEcyVYP4Vo2u9gA4v0rFkQ1fUa4sDRKSGtpwiVmSlDxYqRU= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: After the global KeyID has been configured on all packages, initialize all TDMRs to make all TDX-usable memory regions that are passed to the TDX module become usable. This is the last step of initializing the TDX module. Initializing TDMRs can be time consuming on large memory systems as it involves initializing all metadata entries for all pages that can be used by TDX guests. Initializing different TDMRs can be parallelized. For now to keep it simple, just initialize all TDMRs one by one. It can be enhanced in the future. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - Code change due to change static 'tdx_tdmr_list' to local 'tdmr_list'. v8 -> v9: - Improved changlog to explain why initializing TDMRs can take long time (Dave). - Improved comments around 'next-to-initialize' address (Dave). v7 -> v8: (Dave) - Changelog: - explicitly call out this is the last step of TDX module initialization. - Trimed down changelog by removing SEAMCALL name and details. - Removed/trimmed down unnecessary comments. - Other changes due to 'struct tdmr_info_list'. v6 -> v7: - Removed need_resched() check. -- Andi. --- arch/x86/virt/vmx/tdx/tdx.c | 60 ++++++++++++++++++++++++++++++++----- arch/x86/virt/vmx/tdx/tdx.h | 1 + 2 files changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 0a3b3374c5cb..ee94a7327d93 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -1108,6 +1108,56 @@ static int config_global_keyid(void) return ret; } +static int init_tdmr(struct tdmr_info *tdmr) +{ + u64 next; + + /* + * Initializing a TDMR can be time consuming. To avoid long + * SEAMCALLs, the TDX module may only initialize a part of the + * TDMR in each call. + */ + do { + struct tdx_module_output out; + int ret; + + /* All 0's are unused parameters, they mean nothing. */ + ret = seamcall(TDH_SYS_TDMR_INIT, tdmr->base, 0, 0, 0, NULL, + &out); + if (ret) + return ret; + /* + * RDX contains 'next-to-initialize' address if + * TDH.SYS.TDMR.INIT did not fully complete and + * should be retried. + */ + next = out.rdx; + cond_resched(); + /* Keep making SEAMCALLs until the TDMR is done */ + } while (next < tdmr->base + tdmr->size); + + return 0; +} + +static int init_tdmrs(struct tdmr_info_list *tdmr_list) +{ + int i; + + /* + * This operation is costly. It can be parallelized, + * but keep it simple for now. + */ + for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) { + int ret; + + ret = init_tdmr(tdmr_entry(tdmr_list, i)); + if (ret) + return ret; + } + + return 0; +} + static int init_tdx_module(void) { static DECLARE_PADDED_STRUCT(tdsysinfo_struct, tdsysinfo, @@ -1168,15 +1218,9 @@ static int init_tdx_module(void) if (ret) goto out_free_pamts; - /* - * TODO: - * - * - Initialize all TDMRs. - * - * Return error before all steps are done. - */ + /* Initialize TDMRs to complete the TDX module initialization */ + ret = init_tdmrs(&tdmr_list); - ret = -EINVAL; out_free_pamts: if (ret) { /* diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 880e90dedb3f..48f830087e7e 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -21,6 +21,7 @@ #define TDH_SYS_INFO 32 #define TDH_SYS_CONFIG 45 #define TDH_SYS_KEY_CONFIG 31 +#define TDH_SYS_TDMR_INIT 36 struct cmr_info { u64 base; From patchwork Mon Mar 6 14:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95392C6FA99 for ; Mon, 6 Mar 2023 14:15:46 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 3152D280007; Mon, 6 Mar 2023 09:15:46 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 2C669280005; Mon, 6 Mar 2023 09:15:46 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 18DEC280007; Mon, 6 Mar 2023 09:15:46 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id 074EB280005 for ; Mon, 6 Mar 2023 09:15:46 -0500 (EST) Received: from smtpin03.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id B800DA04A7 for ; Mon, 6 Mar 2023 14:15:45 +0000 (UTC) X-FDA: 80538671850.03.1BE509C Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 4AB41100025 for ; Mon, 6 Mar 2023 14:15:43 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Cpj7SAb/"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112143; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=2/y7OlTMvTv1WIp8WMImwj3dQm+NWkcBzi4UylOENXQ=; b=eSthFKqwcpM3IqTJ38pCXJDu7ZxA/lsNBfhS43A1JV5UAMryjMld+sw3ROfP98ltNiKCqj 5isD6QZzrgWqVhcPQeU17qrBs0y+dNpIidDDNs/U8zdgGbFC2XSAsMUW2GDdMl0aztiHt5 N6EXGp5ZKzjP7Ndkzj5Hz8RAsOC6qac= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b="Cpj7SAb/"; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112143; a=rsa-sha256; cv=none; b=ysRCAW1/zELvhgrS23CaPcwNa5B7jHbDiFYfC75hrhSFIb4uOCfw9rM9/mjq4GokkdFFqp DW+I6f5hzLQ36v6k/ibpsWmCYEEQUpf+ccstrXuXjEzOWKpeBhiunv3lCMZV9oKXC0bkQQ I3IcBGEZZNduwQYZECX9rLWsw/L025U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112143; x=1709648143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GQvfu8vV/36Z9osC0CkzO5uRKQGb//01eRTjqXMgXtA=; b=Cpj7SAb/6aA6ZA1w7gO1UOjrpPiloQR+S2oa3MJDdQapDcKXo8ACyAhr M0xgm5Hf9jD43CqP2A4Cg5fX4T+XXM2mVAg1r+1zmfmc4c3QC0e1BxSLU 0Ygf2kNyCC4bPYQC3HR2sIqA2uLaQz17pa8TrK1LJUfC3IUs8kt3jAs/4 WmmQKwutgMBI/6oq4aDuYdTNdcsLArJg8dFYn9FmQOtKiVvq7GOEfvu95 X4ZojMRa7u8CRtMw4OtAUTfPr7OVeVvdF8YH1MAUfW4f1Q38SlheNrubw rie3dlYQT4YFZKCrBJX2AIhZHVBWJoVYCpZwhmJCVhEWF7f/rbUQWXuhA Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080328" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080328" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232550" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232550" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:38 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 15/16] x86/virt/tdx: Flush cache in kexec() when TDX is enabled Date: Tue, 7 Mar 2023 03:14:00 +1300 Message-Id: <95a37c2f09cbca9d91a858067d309279c714626a.1678111292.git.kai.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 4AB41100025 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 7if78sgsy4ypfjdm8mqe3f5hk6ee3y5x X-HE-Tag: 1678112143-146234 X-HE-Meta: U2FsdGVkX1/nps7GaD0Lv72BJYAhwIs9zrGjnONg6InEEs/DmEtnco9Avx0sD0G0Sr1tOz0+jg9XWb48WWIdvOfja5QvJ+pqYiwnPvFLGmErHprUS56uQt76pGkfF4apFsq7OPHGS5Gpem2U2FiiIxSXjRuhmHLjZOW6GWWnzWbn1cvYlJ8k+HvAbrM16fnTOktM8BIbL/DXPQawxbcOqAnaPgyCsdxCHkpEIfdwLezpmWEliySk5q2CzzKbcvk2xXRZsu+PqkHdqPWu9n1egefTvniodsFOSZzHDOnAHrbhTvrTTtf5dnTj2nc6jQkhiXs4TBiq4R2Tu80gLPpixdchdNidrCKyQGMRmStEFsogdcdTlORFBuaHIFok94laJcCeaz0E63tgEGKnao1sLuIptFhH6snCw/Yr0Lk9TeX7AVon8zhrWPvv9NnTNpixXchYouPs9CEt0Ceb3/++HFR1hfqpiUOZi1JPMD9T9G74zHzvljpIF7fPWHAHRLwe5gsGrDRrzM6jxbvn5o1/xtklR+QJ5kfUlnA6bIj3gko5nLLxmMy5CePT/R1033mjCnNxh0NQgUrVW9v5n940UHjHVOZ1wDdL6MOJx//FO+rvcqwU6W/uxu2rHEzzQzlmXEz/rdL0g+eNaLiTh0ELdvPnNj7g7C7FxqmAqtWZnHseTwv9s7QXDmVYEulrLC8hzphvyddFa3eFd2jE7lzCF+q0EL84+0JIz9ArFsMuoXDrQySeTx8TmoO0YdR9zy+M6kE1YQpTA+0y6c9zpWkS111OTRRYqUFvufOQo2EDOnYvG8ZS08VclfXelB/aSjMeMrR1RCTPOY0jIWtqqoeztZc7pSa2xwJ6sfxkGGAFZvgMDeam0j46YGSucsN+CTMNV+9LUxvPHoYJF2f2PuM+WIvhAgcvfsroy7kKT2HMkgtyyHmG2tdkf5ciF2XYcVgIGxrvpaR1OTwJxEwZine 35M13P7m BWk72zx+MHggLmeIzzikKcZTcQTRDMQCEgcSBLsGZeN+0HI89HzxWGKa3IoDM4w8vywhCbx7aKLu1HubCpXu5pFuseIRw2laaxhVcqBOzu7wmRCoiG8oVeaOIYfAv02U08p+Vsm8G6AdzWG/qEhLtxFaOhdJzgvmaSx1osudLr2WsWhg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: There are two problems in terms of using kexec() to boot to a new kernel when the old kernel has enabled TDX: 1) Part of the memory pages are still TDX private pages; 2) There might be dirty cachelines associated with TDX private pages. The first problem doesn't matter. KeyID 0 doesn't have integrity check. Even the new kernel wants to use any non-zero KeyID, it needs to convert the memory to that KeyID and such conversion would work from any KeyID. However the old kernel needs to guarantee there's no dirty cacheline left behind before booting to the new kernel to avoid silent corruption from later cacheline writeback (Intel hardware doesn't guarantee cache coherency across different KeyIDs). There are two things that the old kernel needs to do to achieve that: 1) Stop accessing TDX private memory mappings: a. Stop making TDX module SEAMCALLs (TDX global KeyID); b. Stop TDX guests from running (per-guest TDX KeyID). 2) Flush any cachelines from previous TDX private KeyID writes. For 2), use wbinvd() to flush cache in stop_this_cpu(), following SME support. And in this way 1) happens for free as there's no TDX activity between wbinvd() and the native_halt(). Theoretically, cache flush is only needed when the TDX module has been initialized. However initializing the TDX module is done on demand at runtime, and it takes a mutex to read the module status. Just check whether TDX is enabled by the BIOS instead to flush cache. Signed-off-by: Kai Huang Reviewed-by: Isaku Yamahata --- v9 -> v10: - No change. v8 -> v9: - Various changelog enhancement and fix (Dave). - Improved comment (Dave). v7 -> v8: - Changelog: - Removed "leave TDX module open" part due to shut down patch has been removed. v6 -> v7: - Improved changelog to explain why don't convert TDX private pages back to normal. --- arch/x86/kernel/process.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 40d156a31676..5876dda412c7 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -765,8 +765,13 @@ void __noreturn stop_this_cpu(void *dummy) * * Test the CPUID bit directly because the machine might've cleared * X86_FEATURE_SME due to cmdline options. + * + * The TDX module or guests might have left dirty cachelines + * behind. Flush them to avoid corruption from later writeback. + * Note that this flushes on all systems where TDX is possible, + * but does not actually check that TDX was in use. */ - if (cpuid_eax(0x8000001f) & BIT(0)) + if (cpuid_eax(0x8000001f) & BIT(0) || platform_tdx_enabled()) native_wbinvd(); for (;;) { /* From patchwork Mon Mar 6 14:14:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Kai" X-Patchwork-Id: 13161231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 006C6C61DA4 for ; Mon, 6 Mar 2023 14:15:50 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 97E15280008; Mon, 6 Mar 2023 09:15:50 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 92E86280005; Mon, 6 Mar 2023 09:15:50 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 7A999280008; Mon, 6 Mar 2023 09:15:50 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 665E5280005 for ; Mon, 6 Mar 2023 09:15:50 -0500 (EST) Received: from smtpin01.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 412181C5D80 for ; Mon, 6 Mar 2023 14:15:50 +0000 (UTC) X-FDA: 80538672060.01.999791D Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by imf05.hostedemail.com (Postfix) with ESMTP id 00EFC100012 for ; Mon, 6 Mar 2023 14:15:47 +0000 (UTC) Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=SFLMFDJ+; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1678112148; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=sJDUpZRkFdE1JvBPgkD3+gsgIMKIkVKhyBqOuwgOhF8=; b=g/7FfWtMTYhfDXuOB1GJGMkf3QTW8NWY/ymB5k6YoBqVM0KJxA7iNJPsWS9k3wqWhvGf8b e2D1hss3iYXBowfLgbWDLOjJ0ucOuwswIoVurf+IMQJK67Nk4xPZKWYwUbTT1oX4Eu3BAn dxUMKQ1yVJ4PbQaHXqwKU4RwgqA9VRA= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=SFLMFDJ+; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf05.hostedemail.com: domain of kai.huang@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=kai.huang@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1678112148; a=rsa-sha256; cv=none; b=mphRF/Kk4CZINNora979jwKkattViITNbjkECzQfZzemgPJKH8DN3A1GBLC6FOFBGSoWGI 8C3u8dnvUVDYebvMZOOzav1ZCDJ10Q28aby61LNYjFww8JS3SvSDqYheohS0lZ04jOOvVI xVAqVfBU6UBArDVArzvMcSNrR7qzxwM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112148; x=1709648148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=coSckihc/FGLGVwvcV+LqtmdmdjmpY1DZ81B3xj/jnI=; b=SFLMFDJ+AfmvFgFQyZ5owpVUmghfZPL0+vmfFp0lzaIEtAHiokKLIrOV em9NoFCr68icEbbR/lKoIw01X0pdkAtaFnfXnHZg/CkCYUN2BKLttCpRc 5Df1FOZ4ZIRRKClHu+T4Wp1U2dSeDV4eBIhGgIsosNg8etb+YeqFRC3/5 Lpk7xoNZTXKkbJy3LpFJaaj4TWG6e0dNJuyKMPokg9WV64ZbpJ1p4k1RN TkCrEEqKD+DskNvozVwHdTQjoyHI8tsM6bPmr/5jLnq5GJA4GE7nvFZOV UMwGplYwutSsjqjfBGVYYfNmAbTn+Bq/uUbCZrj/baTx3twcXqx+jkdYH A==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337080354" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337080354" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765232577" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765232577" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:15:43 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 16/16] Documentation/x86: Add documentation for TDX host support Date: Tue, 7 Mar 2023 03:14:01 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-Rspamd-Queue-Id: 00EFC100012 X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: 7c98b5fk7nnpftdm4xzwf3t4xcdjih1n X-HE-Tag: 1678112147-842700 X-HE-Meta: U2FsdGVkX1844DUeiWBfkTYKWrgEqNfmvhnM+Q/X5OZwFWnd61UmOiK5zwzj49UQTdNgfXqHHuLfR6dwusfAmyQknEoD7SAEsSD4nQom7xl99sl4H4kPXPSgaSY4AuKM6m7az+Dkrhu9L1pCvWigfNPhwo/OppsS6ExvXCGE+hpZHsF8XpC3GU6g4Kp4uRBOKGtgQV20WZtPK+BWlvoTxbtZjXyZXaHSl17eHkhvc9UknU+HYuSufh4PpVKzKHjv0RW6m2/uy9L+kiYE+OusmpqqwKfY0Z1qRc+zDGXIfWzsc92lMb/0MHgo67rOqIuDvvYO2R3z0xx+VWL0Rv2+R9oOHUwF5aDjeD4Aro10gwyHCIR2gwbYh0zJ937bKIjT7ZtqZ/Svse/GtnVnGTZDgPNW52Gk37clKo1qyPJzfuQ+p/kXY6QoSbi6MnQxll85oZz+dSAvPm3HyxIqoAYMoHNaryvhDy0bH7wB36S/8LfCvxYakMX3RQkEIZbPDodu2cIvgKzC/Qp2BMa++7Yez/ilCwZ9zjWYfE2kvfwWWTWwx8vNr50mnnguWtbzaCFRlG79X+vsIubVE20zw3cX1UEO+8FzFw4ogM9XpHKPlfr4eyRqaILiqgRJ1bD/+diC9+RsVvrvqFBb78sT9JlAV2sA3kTSJupeglYgniiPnvc6Zq1jN/dgSC2xIhK8ooCNMiGA4VLGCus74Sj0rOeh2prppTXX/y9VxNbO5yV0dKN2mOtxvWXxeg4dBQ2G7YA1deCr5yijZLjYq0C8+4APdnbIgk1yH+T5Zz4zgTq8bsmTCR0rcaVFIRFaIDndSEOjI4Lh81ps1dLLKm/2y4f1HPrPQvk/EfOyGmTInMRdYuflqxevvvwmnwV2DZraUQT8nlVfHM5pcE6CryDBw86uWaLiQqxiGnVD86YKcU+1NN4CW/KfzvaN/xpyvA6lgQjxofiP1N4yTLADg2jrdj4 4zsZbvLG cGPXpA6j/2rYAcsV9MDADY2d+ZH5QFwis15K8L6w2TGQO2zDtT5AbPXZ2UKwKCAX86FmVcdEBtmVL0yO96aJ22pHuJKyXqqTR5Dj040yYy5dtP6xABBA0fFIqOBCi+OwI/paR1TOIJICTdZd2pxYmzE7XgGJKt376CxIZvKeHuryGHj4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add documentation for TDX host kernel support. There is already one file Documentation/x86/tdx.rst containing documentation for TDX guest internals. Also reuse it for TDX host kernel support. Introduce a new level menu "TDX Guest Support" and move existing materials under it, and add a new menu for TDX host kernel support. Signed-off-by: Kai Huang --- Documentation/x86/tdx.rst | 186 +++++++++++++++++++++++++++++++++++--- 1 file changed, 175 insertions(+), 11 deletions(-) diff --git a/Documentation/x86/tdx.rst b/Documentation/x86/tdx.rst index dc8d9fd2c3f7..a6f66a28bef4 100644 --- a/Documentation/x86/tdx.rst +++ b/Documentation/x86/tdx.rst @@ -10,6 +10,170 @@ encrypting the guest memory. In TDX, a special module running in a special mode sits between the host and the guest and manages the guest/host separation. +TDX Host Kernel Support +======================= + +TDX introduces a new CPU mode called Secure Arbitration Mode (SEAM) and +a new isolated range pointed by the SEAM Ranger Register (SEAMRR). A +CPU-attested software module called 'the TDX module' runs inside the new +isolated range to provide the functionalities to manage and run protected +VMs. + +TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to +provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs +as TDX private KeyIDs, which are only accessible within the SEAM mode. +BIOS is responsible for partitioning legacy MKTME KeyIDs and TDX KeyIDs. + +Before the TDX module can be used to create and run protected VMs, it +must be loaded into the isolated range and properly initialized. The TDX +architecture doesn't require the BIOS to load the TDX module, but the +kernel assumes it is loaded by the BIOS. + +TDX boot-time detection +----------------------- + +The kernel detects TDX by detecting TDX private KeyIDs during kernel +boot. Below dmesg shows when TDX is enabled by BIOS:: + + [..] tdx: BIOS enabled: private KeyID range: [16, 64). + +TDX module detection and initialization +--------------------------------------- + +There is no CPUID or MSR to detect the TDX module. The kernel detects it +by initializing it. + +The kernel talks to the TDX module via the new SEAMCALL instruction. The +TDX module implements SEAMCALL leaf functions to allow the kernel to +initialize it. + +Initializing the TDX module consumes roughly ~1/256th system RAM size to +use it as 'metadata' for the TDX memory. It also takes additional CPU +time to initialize those metadata along with the TDX module itself. Both +are not trivial. The kernel initializes the TDX module at runtime on +demand. + +Besides initializing the TDX module, a per-cpu initialization SEAMCALL +must be done on one cpu before any other SEAMCALLs can be made on that +cpu. + +The kernel provides two functions, tdx_enable() and tdx_cpu_enable() to +allow the user of TDX to enable the TDX module and enable TDX on local +cpu. + +Making SEAMCALL requires the CPU already being in VMX operation (VMXON +has been done). For now both tdx_enable() and tdx_cpu_enable() don't +handle VMXON internally, but depends on the caller to guarantee that. + +To enable TDX, the user of TDX should: 1) hold read lock of CPU hotplug +lock; 2) do VMXON and tdx_enable_cpu() on all online cpus successfully; +3) call tdx_enable(). For example:: + + cpus_read_lock(); + on_each_cpu(vmxon_and_tdx_cpu_enable()); + ret = tdx_enable(); + cpus_read_unlock(); + if (ret) + goto no_tdx; + // TDX is ready to use + +And the user of TDX must be guarantee tdx_cpu_enable() has beene +successfully done on any cpu before it wants to run any other SEAMCALL. +A typical usage is do both VMXON and tdx_cpu_enable() in CPU hotplug +online callback, and refuse to online if tdx_cpu_enable() fails. + +User can consult dmesg to see the presence of the TDX module, and whether +it has been initialized. + +If the TDX module is not loaded, dmesg shows below:: + + [..] tdx: TDX module is not loaded. + +If the TDX module is initialized successfully, dmesg shows something +like below:: + + [..] tdx: TDX module: attributes 0x0, vendor_id 0x8086, major_version 1, minor_version 0, build_date 20211209, build_num 160 + [..] tdx: 262668 KBs allocated for PAMT. + [..] tdx: TDX module initialized. + +If the TDX module failed to initialize, dmesg also shows it failed to +initialize:: + + [..] tdx: TDX module initialization failed ... + +TDX Interaction to Other Kernel Components +------------------------------------------ + +TDX Memory Policy +~~~~~~~~~~~~~~~~~ + +TDX reports a list of "Convertible Memory Region" (CMR) to tell the +kernel which memory is TDX compatible. The kernel needs to build a list +of memory regions (out of CMRs) as "TDX-usable" memory and pass those +regions to the TDX module. Once this is done, those "TDX-usable" memory +regions are fixed during module's lifetime. + +To keep things simple, currently the kernel simply guarantees all pages +in the page allocator are TDX memory. Specifically, the kernel uses all +system memory in the core-mm at the time of initializing the TDX module +as TDX memory, and in the meantime, refuses to online any non-TDX-memory +in the memory hotplug. + +This can be enhanced in the future, i.e. by allowing adding non-TDX +memory to a separate NUMA node. In this case, the "TDX-capable" nodes +and the "non-TDX-capable" nodes can co-exist, but the kernel/userspace +needs to guarantee memory pages for TDX guests are always allocated from +the "TDX-capable" nodes. + +Physical Memory Hotplug +~~~~~~~~~~~~~~~~~~~~~~~ + +Note TDX assumes convertible memory is always physically present during +machine's runtime. A non-buggy BIOS should never support hot-removal of +any convertible memory. This implementation doesn't handle ACPI memory +removal but depends on the BIOS to behave correctly. + +CPU Hotplug +~~~~~~~~~~~ + +TDX module requires the per-cpu initialization SEAMCALL (TDH.SYS.LP.INIT) +must be done on one cpu before any other SEAMCALLs can be made on that +cpu, including those involved during the module initialization. + +The kernel provides tdx_cpu_enable() to let the user of TDX to do it when +the user wants to use a new cpu for TDX task. + +TDX doesn't support physical (ACPI) CPU hotplug. During machine boot, +TDX verifies all boot-time present logical CPUs are TDX compatible before +enabling TDX. A non-buggy BIOS should never support hot-add/removal of +physical CPU. Currently the kernel doesn't handle physical CPU hotplug, +but depends on the BIOS to behave correctly. + +Note TDX works with CPU logical online/offline, thus the kernel still +allows to offline logical CPU and online it again. + +Kexec() +~~~~~~~ + +There are two problems in terms of using kexec() to boot to a new kernel +when the old kernel has enabled TDX: 1) Part of the memory pages are +still TDX private pages; 2) There might be dirty cachelines associated +with TDX private pages. + +The first problem doesn't matter. KeyID 0 doesn't have integrity check. +Even the new kernel wants use any non-zero KeyID, it needs to convert +the memory to that KeyID and such conversion would work from any KeyID. + +However the old kernel needs to guarantee there's no dirty cacheline +left behind before booting to the new kernel to avoid silent corruption +from later cacheline writeback (Intel hardware doesn't guarantee cache +coherency across different KeyIDs). + +Similar to AMD SME, the kernel just uses wbinvd() to flush cache before +booting to the new kernel. + +TDX Guest Support +================= Since the host cannot directly access guest registers or memory, much normal functionality of a hypervisor must be moved into the guest. This is implemented using a Virtualization Exception (#VE) that is handled by the @@ -20,7 +184,7 @@ TDX includes new hypercall-like mechanisms for communicating from the guest to the hypervisor or the TDX module. New TDX Exceptions -================== +------------------ TDX guests behave differently from bare-metal and traditional VMX guests. In TDX guests, otherwise normal instructions or memory accesses can cause @@ -30,7 +194,7 @@ Instructions marked with an '*' conditionally cause exceptions. The details for these instructions are discussed below. Instruction-based #VE ---------------------- +~~~~~~~~~~~~~~~~~~~~~ - Port I/O (INS, OUTS, IN, OUT) - HLT @@ -41,7 +205,7 @@ Instruction-based #VE - CPUID* Instruction-based #GP ---------------------- +~~~~~~~~~~~~~~~~~~~~~ - All VMX instructions: INVEPT, INVVPID, VMCLEAR, VMFUNC, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD, VMRESUME, VMWRITE, VMXOFF, VMXON @@ -52,7 +216,7 @@ Instruction-based #GP - RDMSR*,WRMSR* RDMSR/WRMSR Behavior --------------------- +~~~~~~~~~~~~~~~~~~~~ MSR access behavior falls into three categories: @@ -73,7 +237,7 @@ trapping and handling in the TDX module. Other than possibly being slow, these MSRs appear to function just as they would on bare metal. CPUID Behavior --------------- +~~~~~~~~~~~~~~ For some CPUID leaves and sub-leaves, the virtualized bit fields of CPUID return values (in guest EAX/EBX/ECX/EDX) are configurable by the @@ -93,7 +257,7 @@ not know how to handle. The guest kernel may ask the hypervisor for the value with a hypercall. #VE on Memory Accesses -====================== +---------------------- There are essentially two classes of TDX memory: private and shared. Private memory receives full TDX protections. Its content is protected @@ -107,7 +271,7 @@ entries. This helps ensure that a guest does not place sensitive information in shared memory, exposing it to the untrusted hypervisor. #VE on Shared Memory --------------------- +~~~~~~~~~~~~~~~~~~~~ Access to shared mappings can cause a #VE. The hypervisor ultimately controls whether a shared memory access causes a #VE, so the guest must be @@ -127,7 +291,7 @@ be careful not to access device MMIO regions unless it is also prepared to handle a #VE. #VE on Private Pages --------------------- +~~~~~~~~~~~~~~~~~~~~ An access to private mappings can also cause a #VE. Since all kernel memory is also private memory, the kernel might theoretically need to @@ -145,7 +309,7 @@ The hypervisor is permitted to unilaterally move accepted pages to a to handle the exception. Linux #VE handler -================= +----------------- Just like page faults or #GP's, #VE exceptions can be either handled or be fatal. Typically, an unhandled userspace #VE results in a SIGSEGV. @@ -167,7 +331,7 @@ While the block is in place, any #VE is elevated to a double fault (#DF) which is not recoverable. MMIO handling -============= +------------- In non-TDX VMs, MMIO is usually implemented by giving a guest access to a mapping which will cause a VMEXIT on access, and then the hypervisor @@ -189,7 +353,7 @@ MMIO access via other means (like structure overlays) may result in an oops. Shared Memory Conversions -========================= +------------------------- All TDX guest memory starts out as private at boot. This memory can not be accessed by the hypervisor. However, some kernel users like device