From patchwork Mon Mar 6 17:22:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9A02C64EC4 for ; Mon, 6 Mar 2023 17:30:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 8D172C433D2; Mon, 6 Mar 2023 17:30:39 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.17.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id BBDEFC433A4; Mon, 6 Mar 2023 17:30:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org BBDEFC433A4 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MEFrX-1phB3609X3-00AHTH; Mon, 06 Mar 2023 18:23:13 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 1/8] dt-bindings: vendor-prefixes: add chargebyte Date: Mon, 6 Mar 2023 18:22:42 +0100 Message-Id: <20230306172249.74003-2-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:GmRbHadQVwqC+mg7raRvcxSwI16pBkcDjYkmfckT06Qp86+EKtq U79lbWonJTVU4EBP9bZ0OZllQyqlCpueGZSzYg8XHWk0L8t6PVjXH25qBdM/eirWQS0Sq2/ fQj9WVUUU1Nta5jp/TgFGzbBO2+qa5k+tnGZaz6A+2/YGGvggne7OudC6az/Up96ACb0tgd hBJSfLO6USTz00bj/gieg== UI-OutboundReport: notjunk:1;M01:P0:OqzwthfL5YI=;NHGEZ0WjEkwd5oPuG4HrGE23wX5 wNcAhHkTddcnvpoVT5oQDaJ+h4h7DbemUuWqsE2a3MhKf4qMsMbwEU8X+M1djJ0wpUJ7NjyvW y8zcqgBtaBl/saXebN/7KquSJDxRiB75QgV4sGxsIzMtr8c3sTWCszvbcuettLRtFj/JUQYDO 1d1s8W0HZTDxY7FaIJ5t4+OKVzTQV0qyX808lhujy3oiPV6/vQEZtp/5fEMgLdz4PLUsI9mOD Dhq3yygWBnU67mrs7usfHYdy6wsbLqjJRPpr6Av3CRVKi/HQ4wXYDag2qq2j4UoYcds1MDNp3 0YQAReaECw42+xKMJ+m9Qyw+owsgEFQG3B/y48lsUwapQ2bsvkuiWf2u/yJV/BUvWtOZQlNPr Z068M9+0L1xkOLR0aISDfMQTY8W7wHfiwFYQ8EvEDKI/ecsexgNDmGpXGnFGF9X/yOigvY46o qqU3u64xnhhZ+mGRt7u1ce/EbsItwmHhMjnruE2QFwhFWzgU144FczwsbxbpPUtOODabybtmX vKN84row3zDCYBZubGxWT++p4r+s4d035dxWYcuAzUNwFKuGnMSJH9XH1Q0NTSGu/I6W87nUq M15jaosRoc8tRPPjZKf0x6PSpqk4bhAMlMe6bT3KEqStx2ZWUaSIfJNVwoY5luir2S0LeiugM IXkP6+ToOV8sPzEg2k8y23sajFBQYECYK1Dtyf1b1A== From: Stefan Wahren chargebyte supplies hardware and software products for all aspects of charging communication. https://chargebyte.com/ Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..b8d8fa1d1fd6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -240,6 +240,8 @@ patternProperties: description: CellWise Microelectronics Co., Ltd "^ceva,.*": description: Ceva, Inc. + "^chargebyte,.*": + description: chargebyte GmbH "^checkpoint,.*": description: Check Point Software Technologies Ltd. "^chefree,.*": From patchwork Mon Mar 6 17:22:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34759C6FD1C for ; Mon, 6 Mar 2023 17:30:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 0348DC4339C; Mon, 6 Mar 2023 17:30:26 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [217.72.192.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 32326C433D2; Mon, 6 Mar 2023 17:30:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 32326C433D2 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MwQOx-1qPPlc3CFB-00sJUB; Mon, 06 Mar 2023 18:23:13 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren , Steffen Trumtrar Subject: [PATCH 2/8] dt-bindings: Add DS2482/DS2484 as trivial device Date: Mon, 6 Mar 2023 18:22:43 +0100 Message-Id: <20230306172249.74003-3-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:v9b3X29P5y5UzsVy968V/rYnVligG5hrFWkTJJqhBc6P5bT3Hja OuJPC/hzzWeTbBSD6bVfxc2xfZNPCsPVvB3GUm6EzyQKFycjQ6ahADYR8CgKuITfSNegaSc bfHwfIDqWwyRjrzR5noOlUhehCWJT1xr76Y3fEHvVU5sWM5CTva0mjGpAr+IjcRURV5W07b h0FNhZltncbKSnCIt8lvg== UI-OutboundReport: notjunk:1;M01:P0:LD2s6YOqI7U=;Nnh5nD5J+j9wSsPmtTvo8PZ9AVd ynPbd3ZLM+glzH7akk46HOXLkcDAf6EVMylWp7pM8kxBidPO8OrMVJfzZQ7IkKvMEDY/jN7Yo XWsa4SSM4KjX5hTVzNx1Hhf2Bv4Of6lVFavA49JAGX3y2zebyHwgycoykFU+Ks4CIdy0evdFD 9lcutVrmEPjdjI6CKEtZZyiTV/VfgLubxvjx5RIHQCKcF/7XPACrt+/ZK3aQUTdWmR3cG4j2v QpNBt9JqxwXcfR2u3mmwigku64x6rvZ/i3PqOk1/jBLTUqEkTD8ew4nKubSoQVbAy5M/ftTxc KYk//iOeiLmi+ZixJPxGKz3BYwaX73mIle8K2kwnsRClJgH7dbyHN3cuDYvwT2/I/lLkT73gG /KxO+KdPsWH7qjGdTS3a+xes9WGFkeHTPZqneWtAvHE/gft2OYyMnAYENyFv/1o7Qa2R5fViF lqVxcmftd7XoellEwLIKZpK9P+YdUVOgGni7TnoM6bLYQlIfb/wCR86ZE7U6qmo1F9v1dix+t J7bdEO+U7NzGErgpqUWQInoqaLX+kZrXegnBRbnYMQ4lTyoa88AIZD7q1A7wKzT5jUXOG8Z1G 1LzKKdWw38dxYQUVKyM1RqWUbgOhr6HIfuRZnYu2YfLXts5CnK/QO8cLRWdkshMTRGjKEOd3o wngfC1Gw1KTQE7iakWNQMxDykgLjNPAEzD7atGL+ml+CYmZlgp1G6MwSdmck6RTJBThKMCRMY jN7P2dTkZBSgu/cBLy9i/I2RRB86Ji7lQ== From: Stefan Wahren Both chips are I2C to 1-wire bridges. Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren Cc: Steffen Trumtrar Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/trivial-devices.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 6f482a254a1d..9b7b24989359 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -183,6 +183,10 @@ properties: - maxim,ds1803-050 # 100 kOhm digital potentiometer with I2C interface - maxim,ds1803-100 + # I2C to 1-wire bridge + - maxim,ds2482 + # I2C to 1-wire bridge + - maxim,ds2484 # 10 kOhm digital potentiometer with I2C interface - maxim,ds3502 # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs From patchwork Mon Mar 6 17:22:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C340C61DA4 for ; Mon, 6 Mar 2023 17:23:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id E0B0CC433A1; Mon, 6 Mar 2023 17:23:44 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [217.72.192.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 69FCDC433EF; Mon, 6 Mar 2023 17:23:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 69FCDC433EF Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MfYDO-1qFC5C1a8W-00g1vq; Mon, 06 Mar 2023 18:23:14 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 3/8] w1: ds2482: add i2c id for ds2484 Date: Mon, 6 Mar 2023 18:22:44 +0100 Message-Id: <20230306172249.74003-4-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:FpRTpt2ZzY6mienThTEbNRfHWBNdsZCyFr8kQjvCTI+RpIK2Uwa bnunZRwMmRHkOJxcVfa/1K6T4N0nJojbL4G8dF+v9dhYAX7gEj+4BQrOEQQnqs/7QZZLXdp m9eiMTBOWwcZ4/8bpDI4HF5dfcn+KrCIQxrE7HzqYo6SQo0Yjwt5d/ilrrCi0hpgqS9+BQJ f3hyNkJPRL1xpa8bEVriw== UI-OutboundReport: notjunk:1;M01:P0:Ia63qqu8ctE=;jrIe9L5aIyXvRzwzWne8iCjw4aU YhUqVmPr5iqvpuP3nwi9a/o1yNPb3wlOhqsNSOvADOChVvsBNn/w6NXN8MZ5o7edDCR9D+Soo q4DH+bK5IWVay2tUMc2qm48bOImDtvG/q8tnSI+fIzI/3B+wZYBXGnUaa1U0+fzrPhjzexSjx ttomjOHibxbjeGuTOSJSj/LyUC06vUUs5Do2W1ujEanU/4MBBtz3hjXWK6n++YIch1YYlFx2G wIgt+7uwfvrmxUVUVl3sHIhJCXnLGtP4KrssOciPkr3zyF7592JDSeF6inFn+Jy/EOQ0ItxMf zUrqAHFRzsXQt5N6yCJvvjF9IjmE+ml9gwtOMYzSs1hS4UZSPIVO5Q6N8ysFLWt3/Xi8nV/qj jFQDmyaATHEQd11Jgg9CkDb7TmkbdqLnS7fEyzGR4ZBzRyBMOuqo+OiKbhT9kv3qQIp8jPe9P 9IfEtwmDpqbzZ5oPGvhpPpi9UqRoQVxcA+mh4J2Jl/io0d/YXEDLrTzzsnBLGYHYyZdhbIDYH 7QFWTzQc2+yZ4xFuXgYSRL0M08HzhrOSkI6BID2AlFsSgBTkohEA1hx08acbX4ob6KYrDBVmD TvWnhB89uDVHJR9Wi3wWd57J8GDyerfT/kjr6McdABQD2ApdO/IyWtBnMNQhZbXsIrGzjYw9k rW2eGs8GSSyUccWDCelRyhl/yMwWmLC5geTt8NghuQ== From: Stefan Wahren The DS2484 is very similar to the DS2482-100, but also supports a pin-controlled power-saving sleep mode. Link: https://www.analog.com/media/en/technical-documentation/data-sheets/DS2484.pdf Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- drivers/w1/masters/ds2482.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/w1/masters/ds2482.c b/drivers/w1/masters/ds2482.c index 62c44616d8a9..6f6df686e9ad 100644 --- a/drivers/w1/masters/ds2482.c +++ b/drivers/w1/masters/ds2482.c @@ -545,6 +545,7 @@ static void ds2482_remove(struct i2c_client *client) */ static const struct i2c_device_id ds2482_id[] = { { "ds2482", 0 }, + { "ds2484", 0 }, { } }; MODULE_DEVICE_TABLE(i2c, ds2482_id); From patchwork Mon Mar 6 17:22:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A100C64EC4 for ; Mon, 6 Mar 2023 17:23:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 02CD9C433A0; Mon, 6 Mar 2023 17:23:44 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.17.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 04ADCC4339B; Mon, 6 Mar 2023 17:23:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 04ADCC4339B Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M3lkT-1pYxZQ0Hqd-000tYL; Mon, 06 Mar 2023 18:23:15 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 4/8] dt-bindings: iio: st-sensors: Add IIS328DQ accelerometer Date: Mon, 6 Mar 2023 18:22:45 +0100 Message-Id: <20230306172249.74003-5-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:wQRPex7XRzipPrnANRDADxZJE2vb54rgHl+nepAI703ge7CdZAd wBQQEv8D5RoFYWvTcdUDp8/wxCc0OVffAnl6LIf8bIjT/OQ5+j2PMyqSTNjOpeqI0rL6+23 2oT0eaxJKFcb5uHJtU9XR1Or0NwKNLIyEGEO7mgrjLURo94lhq0Aj+oKQK50DaIlPh8reIr 1RHw7cZPZfig5/B+kzmEw== UI-OutboundReport: notjunk:1;M01:P0:2sDwh7PkhG8=;M3XqNZ4rhms1Stj2/5vNtVLQwfl kpHEE1eayt996RXZyq/JLFEzualTgBHZrx1WVkoHAKuygRw5S4UzSLVS0XEurlHe8yzT9IAyR hvCKZV2FbGrjkWYwz+gDOh8ltdg4po0XQiMVPFjs1isB6MBpbB8QzmbqDUvVyr0DoxZtYwVsW dw9DAeMwukSI1qw6CIBeuPO/qwWeZKbpgppuDIOyphGOKJWdUnJlsWG+lCupO8342jMkzFanc ahDaqMr/hrmxolDgHzB+43q60Hf1KZimaY1if44ByDm+E2vZd6uTvlte7jHyjA+yw6VGFvPNg kcQqzxLhjF/bWK4mS/uUrEs61oZpX9zHKihsQfzR7FKr6CLtTrUwcerZsd5ZIgQ6nJCDw+xc5 70FK0567vr6bQkHcXBDdr0ut8FdSXoDzrh2wdRfT3Rob+DAXKFIQSihlITWj4WsGCCULDzEp8 hCgQ0882ndnYUE/rCHk931oTr0dih4Wi6gEe/9kpYAS0VktAcjB1LZa3KxyKdvjxiX3q2vSnx 9MycMde1j9gBZo4myRecY43SbnhiExxOqfdhIaZ9WDMA84SD64vF+0gNSKWXwayvv/Hu0vrKv RUgYHOKmZZh7+C/Cl3RKF4H7R8OmggB7mhDxTEmRVZEcU9CTpGsYc7vF7aVVUg+rLOMrmSZ+r +pqdM76w4Jfb4+UO7fb5ritG4Q0Pi9a2H9YnsKMQ91Yh3Azq8213XjNKonxpWG0fMhQyqgE1K 04rjKx7D2xjcRUJdx5jHwBF/P4nebMydA== From: Stefan Wahren The ST IIS328DQ is an accelerometer sensor compatible with the existing ST sensor binding. Link: https://lore.kernel.org/linux-iio/2bac9ecf-9d2e-967e-9020-1c950487d781@i2se.com/ Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/iio/st,st-sensors.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml index c6201976378f..247700537aa8 100644 --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml @@ -25,6 +25,7 @@ properties: - description: STMicroelectronics Accelerometers enum: - st,h3lis331dl-accel + - st,iis328dq - st,lis2de12 - st,lis2dw12 - st,lis2hh12 From patchwork Mon Mar 6 17:22:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4590C6FD1D for ; Mon, 6 Mar 2023 17:30:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 9EA85C4339C; Mon, 6 Mar 2023 17:30:33 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [217.72.192.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id B3682C433D2; Mon, 6 Mar 2023 17:30:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org B3682C433D2 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MCbR7-1phj0q3Nit-009jEz; Mon, 06 Mar 2023 18:23:15 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 5/8] iio: accel: add support for IIS328DQ variant Date: Mon, 6 Mar 2023 18:22:46 +0100 Message-Id: <20230306172249.74003-6-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:8pOSVs5pr3qo5I8gRJ4mnb4mzsthHgbkNTMbUsy+rAaH8Tcqei4 1nJJeYoOAlsnTs5CYx7U1BlLvzhb8SGehE1/OZn5fRLsm9jU7byYi5dcZ1jyaoaxkBZd9IX NTz7ElNVj2hIwUyMvNtjnSUwD5Mv7zp5Bs1Z4R96niKL6ZS5TiZ+mKuPzUecb38L5hShpV1 G9g7EXMnmqV+QmXt86snA== UI-OutboundReport: notjunk:1;M01:P0:7tgHV863EpY=;wRmrbcL0LDkeKRfkDjntSIwxaWN ROdAs1js6d5bVIdpNe6xXTmYa1NHZ9BAmpET9MYHMGJPO+bNKTpg5CIepdoqPK0kqeWI1xL+4 Mo1tU4atqSFkk+SZME5p/TCwS5RMyODUBpDi51Pboa3H5jbUEy8MGT6+3NifhebwjTvlwlRSN mdFnk2IWoupePlo728DZN/zBEPMCGxCgMDOOubRs4f3sEUEjm7LTEW+zIMzE//gQ9BTNWAblr 3k860LiFgA2oH9lwn6pMY/OnVMsiCjr3BzEdxftdIYUs1TFJnaCqClwJwWXgC1Dz+hTei+/J6 JJnpCseXvfd9w68vQ5gCaq6ZeR2X+1G/Qs+wwA8mdlfH4Dj3m+C6QL8RVBA7t0nfWfaT1zr2G grKl31u6pgkZrcsOr72oCXNfiTVcMViTbMnVPuYEvyVmMZPbyb2AM+TnZOdF38EfsPNFuWO26 SynX4TDHnDUJuve+eOnFH1HpOPgdZ4/uA8rLB3gjQOF/Jr7BGP5dwM6SrE1y4OLrCG7sTYJ/y pNq2BPwlyCAtymeW3vFsCYDMbu+AbDqA2/SqZiLYrQvAHa3AIo9C27XXZhzllVsmn5WE1sYm2 sxSrwL4V7UXgMIEb1CF5O7dOIwd/DoI9+WSMOqbFxF+3Ty5Jtk1cGYuxsC2vQx+2GHRPHpprm C5bKAx70z3shhVZ+Q19GWihaKKsE+sw6hbMPZYGQlw== From: Stefan Wahren Add support for ST IIS328DQ accelerometer to the st_accel framework. The chip is compatible to the LIS331DL. Link: https://www.st.com/resource/en/datasheet/iis328dq.pdf Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- drivers/iio/accel/st_accel.h | 1 + drivers/iio/accel/st_accel_core.c | 1 + drivers/iio/accel/st_accel_i2c.c | 5 +++++ drivers/iio/accel/st_accel_spi.c | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/drivers/iio/accel/st_accel.h b/drivers/iio/accel/st_accel.h index 56ed0c776d4a..e7525615712b 100644 --- a/drivers/iio/accel/st_accel.h +++ b/drivers/iio/accel/st_accel.h @@ -39,6 +39,7 @@ #define LIS302DL_ACCEL_DEV_NAME "lis302dl" #define LSM303C_ACCEL_DEV_NAME "lsm303c_accel" #define SC7A20_ACCEL_DEV_NAME "sc7a20" +#define IIS328DQ_ACCEL_DEV_NAME "iis328dq" #ifdef CONFIG_IIO_BUFFER diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index 6b8562f684d5..5f7d81b44b1d 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -517,6 +517,7 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, .sensors_supported = { [0] = H3LIS331DL_ACCEL_DEV_NAME, + [1] = IIS328DQ_ACCEL_DEV_NAME, }, .ch = (struct iio_chan_spec *)st_accel_12bit_channels, .odr = { diff --git a/drivers/iio/accel/st_accel_i2c.c b/drivers/iio/accel/st_accel_i2c.c index 3f02fd5d5946..fb9e2d6f4210 100644 --- a/drivers/iio/accel/st_accel_i2c.c +++ b/drivers/iio/accel/st_accel_i2c.c @@ -119,6 +119,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "silan,sc7a20", .data = SC7A20_ACCEL_DEV_NAME, }, + { + .compatible = "st,iis328dq", + .data = IIS328DQ_ACCEL_DEV_NAME, + }, {}, }; MODULE_DEVICE_TABLE(of, st_accel_of_match); @@ -157,6 +161,7 @@ static const struct i2c_device_id st_accel_id_table[] = { { LIS302DL_ACCEL_DEV_NAME }, { LSM303C_ACCEL_DEV_NAME }, { SC7A20_ACCEL_DEV_NAME }, + { IIS328DQ_ACCEL_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(i2c, st_accel_id_table); diff --git a/drivers/iio/accel/st_accel_spi.c b/drivers/iio/accel/st_accel_spi.c index 5740dc1820bd..f72a24f45322 100644 --- a/drivers/iio/accel/st_accel_spi.c +++ b/drivers/iio/accel/st_accel_spi.c @@ -100,6 +100,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "st,lsm303c-accel", .data = LSM303C_ACCEL_DEV_NAME, }, + { + .compatible = "st,iis328dq", + .data = IIS328DQ_ACCEL_DEV_NAME, + }, {} }; MODULE_DEVICE_TABLE(of, st_accel_of_match); @@ -157,6 +161,7 @@ static const struct spi_device_id st_accel_id_table[] = { { LIS3DE_ACCEL_DEV_NAME }, { LIS302DL_ACCEL_DEV_NAME }, { LSM303C_ACCEL_DEV_NAME }, + { IIS328DQ_ACCEL_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(spi, st_accel_id_table); From patchwork Mon Mar 6 17:22:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BE58C61DA4 for ; Mon, 6 Mar 2023 17:24:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 6D4ECC4339E; Mon, 6 Mar 2023 17:24:04 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.17.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id B222EC433D2; Mon, 6 Mar 2023 17:24:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org B222EC433D2 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M1Hi8-1patW21u94-002pUa; Mon, 06 Mar 2023 18:23:16 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 6/8] dt-bindings: ARM: fsl: Add chargebyte Tarragon Date: Mon, 6 Mar 2023 18:22:47 +0100 Message-Id: <20230306172249.74003-7-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:FS/4/qcr5NmZKckgW7zlmnMsGwEvDOoLosNndOZo3iPI/pUGk5L QRBdr6KZmgoIW21oww7AAIE2OvP4G2ExcMY9W4491dIo1EMS3benQ7yyBgj1Suva+NhZ1d0 v8299dgBPrWoYSRACET5FUw8SY70yRyxEJIOKsly4Y4EdQukfhOa7pKC0466BuQjNHVo/rx /AU7xZrNXSCgM56GxotpA== UI-OutboundReport: notjunk:1;M01:P0:Bc659OuMOwQ=;Llz3lIdtaaCgD/S7kK8AmYMlU9g k+bQtZ5WRG7M3lgoC3gXA7wzm1awcgSDE0DPP1Gw4vSdpD/Io6FVIEJ1y9l2Bu9m1w17RQte+ /DtiBfLumTSPt0dMWFK4m77MS/w+l12BrQffsMwmXojC8hl8Pi98ApQuj+SvtBzKx4mQ1JHw9 IGdP0YllM3pZUpxb3YjQ5As2cx3K3p6mOPSW+pKq9/IiNNWn4vSRdi1JIxo87gc/68G2vb4T3 wxmf0KbaXG2tzQKSjltamqFBDDK8JR8j6f+dauJYSHP8CaGFZiPj42hCVgvj/PkmXScR5BeBK sFRz2J3yUO4lxtT3CRCP9b4YU1T+/ms1HkZeKr43K8TZanS/rf63BQ92n0Q0U47MCQjIIbfhM ISawMOuJS5ZfjDEQyZ3O3gn0QqXnGtdMCWRtPKSstX9BHgfIjaDby6QP6VWvewhOKc+vACrkS biTNQ0gjIvfkgCS2JzzhKf8WfwWeE6BqZfEZc0OghPDstiSxaLr1XmwWIscFLotTmoumzGD9F 3eUTmH3Y0Tb9QDnFhg02r5+qWSMlc63Zyi5UiMHjil1N5OsRHcYYGyHZVLL4NFiBHDHXsGCfr B1UdPljx85r8JMWDQYDMJ2nOJyd3QgKAPq6+SdSmMG0LZ6FgqvH6tYm0bqQ64vQuKQVbZTjDm lNFdQYvyGGxCBzALV3CR6I15F1XzpNVECVNhqvo4Tw== From: Stefan Wahren This adds the compatibles for the chargebyte Tarragon boards. Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index dece3e9ba7fd..2b430e20a7a6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -781,6 +781,15 @@ properties: - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant - const: fsl,imx6ull + - description: chargebyte Tarragon Boards + items: + - enum: + - chargebyte,imx6ull-tarragon-master + - chargebyte,imx6ull-tarragon-micro + - chargebyte,imx6ull-tarragon-slave + - chargebyte,imx6ull-tarragon-slavext + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: From patchwork Mon Mar 6 17:22:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C248FC61DA4 for ; Mon, 6 Mar 2023 17:23:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id A523BC433A1; Mon, 6 Mar 2023 17:23:48 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.17.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id D78E0C433D2; Mon, 6 Mar 2023 17:23:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org D78E0C433D2 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N79ly-1qeX0L0Rhc-017Uxu; Mon, 06 Mar 2023 18:23:17 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 7/8] ARM: dts: imx6ull: Add chargebyte Tarragon support Date: Mon, 6 Mar 2023 18:22:48 +0100 Message-Id: <20230306172249.74003-8-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:ErkC1hCD923LMyJISgaXdyPPR7O3qKYGs7UlCfoUDde/9Il6/dg Mfkqha85ZNsa8Qh8jttjFsBMwgyKKQy7WlVWLeBQk2uT/U5Kul4RX9zLcyr1JKsjH5YuVNX HaNvcyEZ7poeaQgnZNbK64w1qgjVF3KZEMvWEIhWlBgK9/JKZBLqZaeMZW/Wi5U93YxuWjL lfQIgMCB1P81sNNMMhYjA== UI-OutboundReport: notjunk:1;M01:P0:fOMgDhWXsZw=;De5zXZ2oC9Eh7xTu9PvZLN1my2i xcJzvFhig34s9zBl+2wV5L8npndtUBSm8GFGrLFKvyUSB2I6Ep/f3dVYIcQnKqHPXP/763BJl m8ejH84WvBs5e8j8VKNbDj+rb7cShN+tTAHCMhagfV8zg0YPp0Ovh+zsLEr7KQFwdzRNe/vNR fe749WuiiLPXHDph4QoolyzZx8a6KCo6aOQSFcKnD4YXu+oo3Azsfd94XnLqAULpp5dvVKimI BvVATeAWzkjceJSXCPKlaNdii+n80GEsLalrzHZDsEHax8i6W5+6XISEN1qY/6ApLmj/A+0+C msnjcD2I+mJk0n0B482BqoG2FlQLBDGRZ+pqDc0uC2ON/5rNVwNVdI/e7Pfz67XgOg4UoOg8q MpbDzNo+IOihm3aO0qEp5nVX9YrJXJTrEjA5bcHescxDJimociiaGZFczpY4n4m/hsmtUBOXU cq7aCSKySQIWUEavfVJ8PSpa7fBXISZ/BakIo28UcEBTrj7G43pS3tDRL0Ku702Fot/Yb8gsP 4qCirMGCmTWMHjsTfaJLpTwBif/RJecCNKX92pDe95NSHhQSjfUB4YgQe2odbFx83fQke2Z7D AGsNz6iCu8GY9Dx7d+kpjWstho4eKiebi9I26shQ1Dy4e5zUOAXzDY/Fjh2U2J6zcfDtQxV9z SbquJLniNSurMf6F5U60BvApWJqgaTx0/yZSTkJckA== From: Stefan Wahren This adds the support for chargebyte Tarragon, which is an Electrical Vehicle Supply Equipment (EVSE) for AC charging stations (according to IEC 61851, ISO 15118). The Tarragon board is based on an i.MX6ULL SoC and is available in 4 variants (Master, Slave, SlaveXT, Micro), which provide more or less peripherals. Supported features: * 512 MB DDR RAM * eMMC * Debug UART * 100 Mbit Ethernet * USB 2.0 Host interface * Powerline communication (QCA700x) * 2x RS485 * Digital in- and outputs (12 V) * One-Wire master for external temp sensors * 2x relay outputs * 2x motor interfaces Link: https://chargebyte.com/products/charging-station-communication/charge-control-c Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- arch/arm/boot/dts/Makefile | 4 + .../arm/boot/dts/imx6ull-tarragon-common.dtsi | 858 ++++++++++++++++++ arch/arm/boot/dts/imx6ull-tarragon-master.dts | 82 ++ arch/arm/boot/dts/imx6ull-tarragon-micro.dts | 10 + arch/arm/boot/dts/imx6ull-tarragon-slave.dts | 32 + .../arm/boot/dts/imx6ull-tarragon-slavext.dts | 64 ++ 6 files changed, 1050 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-master.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-micro.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-slave.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-slavext.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..aae52a6380bc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -755,6 +755,10 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-phytec-tauri-emmc.dtb \ imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tarragon-master.dtb \ + imx6ull-tarragon-micro.dtb \ + imx6ull-tarragon-slave.dtb \ + imx6ull-tarragon-slavext.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi new file mode 100644 index 000000000000..1099dd688e80 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi @@ -0,0 +1,858 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +/dts-v1/; + +#include +#include +#include +#include "imx6ull.dtsi" + +/ { + aliases { + mmc0 = &usdhc2; /* eMMC */ + }; + + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&pinctrl_emmc_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + }; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "dcdc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "ldo-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_status_leds>; + + led1 { + label = "evse:green:led1"; + function = LED_FUNCTION_BOOT; + color = ; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + led2 { + label = "evse:yellow:led2"; + function = LED_FUNCTION_PROGRAMMING; + color = ; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + }; + + led3 { + label = "evse:red:led3"; + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_motor + &pinctrl_adc_cp + &pinctrl_adc_pp>; + vref-supply = <&vgen1_reg>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <3>; + cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH + &gpio3 2 GPIO_ACTIVE_HIGH + &gpio3 4 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_mains_spi>; + num-cs = <1>; + cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 + &pinctrl_enet1_phy_rst + &pinctrl_enet_mdio>; + phy-supply = <®_dcdc_3v3>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-handle = <ðphy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy_int>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + max-speed = <100>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "CP_INVERT", + "", + "", /* 15 */ + "", + "", + "", + "MOTOR_1_FAULT_N", + "", /* 20 */ + "", + "ROTARY_SWITCH_1_2_N", + "ROTARY_SWITCH_1_4_N", + "ROTARY_SWITCH_1_8_N", + "MOTOR_2_FAULT_N"; /* 25 */ +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "EXT_GPIO", + "MOTOR_1_DRIVER_IN1_N", + "MOTOR_1_DRIVER_IN2", + "MOTOR_2_DRIVER_IN1", + "STM32_BOOT0", /* 10 */ + "STM32_RST_N", + "RELAY_1_ENABLE", + "RELAY_2_ENABLE", + "", + "", /* 15 */ + "QCA700X_MAINS_BOOTLOADER_N", + "QCA700X_CP_RST_N", + "QCA700X_CP_BOOTLOADER_N", + "", + "DIGITAL_OUT_1", /* 20 */ + "DIGITAL_OUT_2", + "DIGITAL_OUT_3", + "DIGITAL_OUT_4", + "DIGITAL_OUT_5", + "DIGITAL_OUT_6", /* 25 */ + "ROTARY_SWITCH_2_8_N", + "ROTARY_SWITCH_2_4_N", + "ROTARY_SWITCH_2_2_N"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "BOARD_VARIANT_1", + "BOARD_VARIANT_2", + "BOARD_VARIANT_0", /* 15 */ + "BOARD_VARIANT_3", + "", + "ROTARY_SWITCH_2_1_N", + "", + "DIGITAL_IN_5", /* 20 */ + "", + "", + "DIGITAL_IN_6", + "", + "DIGITAL_IN_1", /* 25 */ + "DIGITAL_IN_2", + "DIGITAL_IN_4", + "DIGITAL_IN_3"; + + pmic-int-hog { + gpio-hog; + gpios = <19 0>; + input; + }; +}; + +&gpio5 { + gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */ + "", + "RELAY_2_SENSE", + "RELAY_1_SENSE", + "", + "", /* 5 */ + "", + "QCA700X_MAINS_RST_N", + "MOTOR_2_DRIVER_IN2", + "", + "CP_POSITIVE_PEAK_RST", /* 10 */ + "CP_NEGATIVE_PEAK_RST"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3001: pmic@8 { + compatible = "fsl,pfuze3001"; + reg = <0x08>; + + regulators { + sw1_reg: sw1 { + regulator-name = "SW1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-name = "VSNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-name = "VLDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-name = "VLDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-name = "VCCSD"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-name = "V33"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-name = "VLDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-name = "VLDO4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + onewire@18 { + compatible = "maxim,ds2484"; + reg = <0x18>; + }; + + accelerometer@19 { + compatible = "st,iis328dq"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>; + vdd-supply = <®_dcdc_3v3>; + vddio-supply = <®_dcdc_3v3>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_pins + &pinctrl_gpio_motor + &pinctrl_board_var + &pinctrl_digital_input + &pinctrl_digital_output + &pinctrl_rotary_switch1 + &pinctrl_rotary_switch2>; + + tarragon { + pinctrl_status_leds: status-ledsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0 + >; + }; + + pinctrl_adc_motor: adc-motorgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_gpio_motor: gpio-motorgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0 + >; + }; + + pinctrl_adc_cp: adc-cpgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_adc_pp: adc-ppgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0 + >; + }; + + pinctrl_usb_pwr: usb-pwrgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0 + MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0 + >; + }; + + pinctrl_enet_mdio: enet-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0 + >; + }; + + pinctrl_enet1_phy_int: enet1-phy-intgrp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0 + >; + }; + + pinctrl_fan_enable: fan-enablegrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0 + >; + }; + + pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0 + >; + }; + + pinctrl_pwm_fan: pwm-fangrp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0 + >; + }; + + pinctrl_pwm_cp: pinctrl-pwm-cpgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0 + >; + }; + + pinctrl_rs485_1: rs485-1grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0 + >; + }; + + pinctrl_rs485_2: rs485-2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0 + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0 + >; + }; + + pinctrl_stm32: stm32grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0 + MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0 + >; + }; + + pinctrl_ext_uart: ext-uartgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0 + MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0 + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0 + >; + }; + + pinctrl_qca700x_cp_int: qca700x-cp-intgrp { + fsl,pins = < + MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0 + >; + }; + + pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0 + >; + }; + + pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0 + >; + }; + + pinctrl_qca700x_mains_spi: qca700x-mains-spigrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0 + >; + }; + + pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0 + MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0 + >; + }; + + pinctrl_digital_input: digital-inputgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0 + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0 + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0 + >; + }; + + pinctrl_board_var: board-vargrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0 + MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0 + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0 + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0 + >; + }; + + pinctrl_digital_output: digital-outputgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0 + MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1 + >; + }; + + pinctrl_emmc_rst: emmc-rstgrp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0 + >; + }; + + pinctrl_rotary_switch1: rotary-switch1grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0 + >; + }; + + pinctrl_rotary_switch2: rotary-switch2grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0 + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0 + >; + }; + + pinctrl_wdog2: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0 + >; + }; + + pinctrl_hog_pins: hog-pinsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_cp_peak_snvs + &pinctrl_gpio_motor_snvs + &pinctrl_rotary_switch1_snvs + &pinctrl_relay_sense_snvs>; + + tarragon { + pinctrl_cp_peak_snvs: cp-peak-snvsgrp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x400010b0 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x400010b0 + >; + }; + + pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400000b0 + >; + }; + + pinctrl_enet1_phy_rst: enet1-phy-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x400010b0 + >; + }; + + pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400000b0 + >; + }; + + pinctrl_qca700x_mains_int: qca700x-mains-intgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x10b0 + >; + }; + + pinctrl_fan_sense_snvs: fan-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0 + >; + }; + + pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x10b0 + >; + }; + + pinctrl_relay_sense_snvs: relay-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0 + >; + }; + + pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0xb0 + >; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_digital_input_ref>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_cp>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,dte-mode; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_2>; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stm32>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ext_uart>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb + &pinctrl_usb_pwr>; + dr_mode = "host"; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usbphy2 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <&sw2_reg>; + vqmmc-supply = <®_1v8>; + mmc-pwrseq = <&emmc_pwrseq>; + bus-width = <8>; + broken-cd; + non-removable; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog2>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/imx6ull-tarragon-master.dts new file mode 100644 index 000000000000..67007ce383e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-master.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Master"; + compatible = "chargebyte,imx6ull-tarragon-master", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&ecspi4 { + status = "okay"; + + qca700x_mains: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_mains_int + &pinctrl_qca700x_mains_rst + &pinctrl_qca700x_mains_btld>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts new file mode 100644 index 000000000000..e471c2005bee --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Micro"; + compatible = "chargebyte,imx6ull-tarragon-micro", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts new file mode 100644 index 000000000000..cee223b5f8e1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Slave"; + compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull"; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts new file mode 100644 index 000000000000..7fd53b7a4372 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon SlaveXT"; + compatible = "chargebyte,imx6ull-tarragon-slavext", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; From patchwork Mon Mar 6 17:22:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 13161936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58D00C6FA99 for ; Mon, 6 Mar 2023 17:23:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 2998CC4339B; Mon, 6 Mar 2023 17:23:45 +0000 (UTC) Received: from mout.kundenserver.de (mout.kundenserver.de [217.72.192.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 76A53C4339C; Mon, 6 Mar 2023 17:23:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 76A53C4339C Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=i2se.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=i2se.com Received: from stefanw-SCHENKER ([37.4.248.41]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M4b5s-1pXaex3NmY-001j20; Mon, 06 Mar 2023 18:23:17 +0100 From: Stefan Wahren To: Rob Herring , Krzysztof Kozlowski , Jonathan Cameron , Lars-Peter Clausen , Arnd Bergmann , Olof Johansson , Evgeniy Polyakov , Shawn Guo , Sascha Hauer , Fabio Estevam List-Id: Cc: linux-imx@nxp.com, Li Yang , Denis Ciocca , soc@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Stefan Wahren Subject: [PATCH 8/8] ARM: imx_v6_v7_defconfig: Enable Tarragon peripheral drivers Date: Mon, 6 Mar 2023 18:22:49 +0100 Message-Id: <20230306172249.74003-9-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306172249.74003-1-stefan.wahren@i2se.com> References: <20230306172249.74003-1-stefan.wahren@i2se.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:apHcp3EmZDFHmusTpF0RTcwoyJeqPvigk6+aX2bNJECC+tUgQ/N KUbP1kVDBGdaW8jNnatNLV01ny0L8kAQblGyGQ1ONpnD8q2kEPfIupcKhRxrLgNvYFFEpba bkBoeW7BaH8TJc+K47y+GOiQncB3rqNB+tuM1iVk6uezW8MUDzfmiKnScEvr6uOC0UwMNVP PnufDfoFk2bjgy2s0myfg== UI-OutboundReport: notjunk:1;M01:P0:a4m4bis2SwU=;axYlHSs0Zq4zPdsGn/qRKITU4rJ d/p/xFSrTK736liY0EaIN9oNQo77dfVlirVDI9XoQC3gEvfKrIYuIGi2Cw+bAa0iiOp4P399e RLNnQdwcTsmM7ZrrJ7OizDEa8402VlmgaZFDD4aoePhviIQB2GtuEknoDunBVqepsVNSxEmcY IxVuEjaTmbZw+8IAPpE3cCJXcPD1OJzykM2MU9tq199EEdfFj62t8f1ojIeeqAcsZ5WbD3zmK gD5mX8qXnTXRSKuecsmvVIHkw44NsDu/UPx4GieYHWxJMngf6QDHdGTY5MmPB7KxTenVUSN5C vqJlxUsH6Kt3hiRXETUMqzHj76IShO1XSV56SxibluyLFzVv/1jeOXmWBqEM/6dT5JC8mVLmb M1+ZDY+h+9Su1iofzMar0imtgMmtUlvENhJZsC7gXb0IfL6XMal29/czhl7YLGkwrLBHmHzl1 dx1yrI+zjwNvdDaUKDOquQwlczqJMcMcH/nlsI4YrUxIWkrPBM/j8v+/jwWSn8UhHbG5qgY8e IasH22IGLHHukL6Oj8A4UvYIbArkMhKqCyhPAoSm+FXDWcnfVPyMBiwzibIZWCTwkZbZPaPbm FffbLQR6Lgn9XLh1oPwyMWyhMT2gPnO/SKR/gSgkWWOvvC13xze4ZADeiY9tdcTEoGxLY+sM+ 3O7c3hmccmHmIuXVhV61A2g5hlxe1t92Yyf17iAw+g== From: Stefan Wahren We need to enable some drivers in order to use the following peripherals of Tarragon: * QCA7000/7005 Powerline chip * One-Wire Master DS2484 with external thermal sensors * external 4 pin PWM fan * ST IIS328DQ I2C accelerometer Signed-off-by: Stefan Wahren Signed-off-by: Stefan Wahren --- arch/arm/configs/imx_v6_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6dc6fed12af8..c854b03fabf2 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -128,6 +128,7 @@ CONFIG_CS89x0_PLATFORM=y # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_QCA7000_SPI=m # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y CONFIG_SMC911X=y @@ -215,6 +216,9 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_74X164=y +CONFIG_W1=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_SLAVE_THERM=m CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y @@ -223,6 +227,7 @@ CONFIG_RN5T618_POWER=m CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SY7636A=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -403,6 +408,7 @@ CONFIG_CLK_IMX8MQ=y CONFIG_SOC_IMX8M=y CONFIG_EXTCON_USB_GPIO=y CONFIG_IIO=y +CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y CONFIG_RN5T618_ADC=y