From patchwork Wed Mar 8 05:33:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dixit, Ashutosh" X-Patchwork-Id: 13165244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CD78C678D5 for ; Wed, 8 Mar 2023 05:33:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7404E10E23C; Wed, 8 Mar 2023 05:33:28 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2725910E309; Wed, 8 Mar 2023 05:33:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678253607; x=1709789607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L77nGrkX09htK6OOMq92wxbOoKCiw1KxlZZzJBkmSu4=; b=P/xdDUEbWcETrzmS6H+uRiw38hP74zicy9YAZmeJ3PWPvyKxir7qih0u yrHBlEg1a/t2ROT5qQ0sVdGHrKhw9A9Atstr7NJwCKj0S9yyiJaiLjxsV BzkXteqRdcxlmWP3/0iYJ1axUOAeacuei4dokgYGKv2wOy6NeEgwi4s6O zjVKtXi8/+wbBLd0t8z70rU42nVgDKbTuhR5FGE9lcrnAp8GE97BtLHPJ KZVFZWz+7yDxyUdMUkBV7l2dZopEIAw+HwS+YcKeOiXkLDM3XOWYPtb3F ZA0P9hIv/JmbGn8ljUJu45Xgr/kijnzRlb0svylkALawJFMOgD2Vr4HKJ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="334781364" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="334781364" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="820071519" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="820071519" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:26 -0800 From: Ashutosh Dixit To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/3] drm/i915/rps: Expose read_actual_frequency_fw for PMU Date: Tue, 7 Mar 2023 21:33:19 -0800 Message-Id: <20230308053321.939906-2-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230308053321.939906-1-ashutosh.dixit@intel.com> References: <20230308053321.939906-1-ashutosh.dixit@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vinay Belgaumkar , Rodrigo Vivi , dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Expose intel_rps_read_actual_frequency_fw to read the actual/granted freq without taking forcewake. This is done for use by PMU which does not take forcewake when reading freq. The code is refactored to use a common set of functions across sysfs and PMU. It also allows PMU to support MTL as well as older generations (before Gen6) which were previously missed due to the non-use of common functions across sysfs and PMU. Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/i915/gt/intel_rps.c | 36 +++++++++++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 4d0dc9de23f9..0a8e24bcb874 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2089,10 +2089,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) return cagf; } -static u32 read_cagf(struct intel_rps *rps) +static u32 __read_cagf(struct intel_rps *rps, bool take_fw) { struct drm_i915_private *i915 = rps_to_i915(rps); struct intel_uncore *uncore = rps_to_uncore(rps); + i915_reg_t r = INVALID_MMIO_REG; u32 freq; /* @@ -2100,22 +2101,30 @@ static u32 read_cagf(struct intel_rps *rps) * registers will return 0 freq when GT is in RC6 */ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { - freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); + r = MTL_MIRROR_TARGET_WP1; } else if (GRAPHICS_VER(i915) >= 12) { - freq = intel_uncore_read(uncore, GEN12_RPSTAT1); + r = GEN12_RPSTAT1; } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { vlv_punit_get(i915); freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); vlv_punit_put(i915); + goto exit; } else if (GRAPHICS_VER(i915) >= 6) { - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); + r = GEN6_RPSTAT1; } else { - freq = intel_uncore_read(uncore, MEMSTAT_ILK); + r = MEMSTAT_ILK; } + freq = take_fw ? intel_uncore_read(uncore, r) : intel_uncore_read_fw(uncore, r); +exit: return intel_rps_get_cagf(rps, freq); } +static u32 read_cagf(struct intel_rps *rps) +{ + return __read_cagf(rps, true); +} + u32 intel_rps_read_actual_frequency(struct intel_rps *rps) { struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; @@ -2128,6 +2137,23 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps) return freq; } +static u32 read_cagf_fw(struct intel_rps *rps) +{ + return __read_cagf(rps, false); +} + +u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps) +{ + struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; + intel_wakeref_t wakeref; + u32 freq = 0; + + with_intel_runtime_pm_if_in_use(rpm, wakeref) + freq = intel_gpu_freq(rps, read_cagf_fw(rps)); + + return freq; +} + u32 intel_rps_read_punit_req(struct intel_rps *rps) { struct intel_uncore *uncore = rps_to_uncore(rps); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index c622962c6bef..63511b826a97 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -39,6 +39,7 @@ int intel_gpu_freq(struct intel_rps *rps, int val); int intel_freq_opcode(struct intel_rps *rps, int val); u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); u32 intel_rps_read_actual_frequency(struct intel_rps *rps); +u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps); u32 intel_rps_get_requested_frequency(struct intel_rps *rps); u32 intel_rps_get_min_frequency(struct intel_rps *rps); u32 intel_rps_get_min_raw_freq(struct intel_rps *rps); From patchwork Wed Mar 8 05:33:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dixit, Ashutosh" X-Patchwork-Id: 13165246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 823EFC678D5 for ; Wed, 8 Mar 2023 05:33:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27C5C10E56C; Wed, 8 Mar 2023 05:33:32 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47B0710E23C; Wed, 8 Mar 2023 05:33:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678253607; x=1709789607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+u2Ic/Vcx427dB70f4AYlQGXrGHxir6gKM+/33N0gT8=; b=eSvBrxcwGE9N3n4qeTVB/dlBYK2hbGmpw44aWzHXpMaBSyXKCzJkMhP4 aiC2BgD6RQHpBiGVnmCyVVH4MH7ScFYxsnMFgcSNEYPc6pZj5cI6MP62h q04k+/vscSvVYxFHJl+YEfCgR68hZU1ETlG9b08xghW526fKKM3HTEPQf 3/9CwZ65Xs6LhoAcmLgMPKoJrClb4ak0J8wd8nghzBzDSe0zDU2igTxto E6oii/G67wgMXikhPc8UZABCZesVWcadpz/ivBHoESqQhjDc55OapchMe PdMf5idMMqJpUsPolwOedIb/us3D8ExWz/pTxpSXCNWrz7GWa1V1p9HrY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="334781365" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="334781365" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="820071523" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="820071523" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:26 -0800 From: Ashutosh Dixit To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/3] drm/i915/rps: Expose get_requested_frequency_fw for PMU Date: Tue, 7 Mar 2023 21:33:20 -0800 Message-Id: <20230308053321.939906-3-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230308053321.939906-1-ashutosh.dixit@intel.com> References: <20230308053321.939906-1-ashutosh.dixit@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vinay Belgaumkar , Rodrigo Vivi , dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Expose intel_rps_get_requested_frequency_fw to read the requested freq without taking forcewake. This is done for use by PMU which does not take forcewake when reading freq. The code is refactored to use a common set of functions across sysfs and PMU. It also allows PMU to support both host turbo (rps) and slpc which was previously missed due to the non-use of common functions across sysfs and PMU. Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++++++++++++++++--- drivers/gpu/drm/i915/gt/intel_rps.h | 2 +- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 0a8e24bcb874..49df31927c0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2154,7 +2154,7 @@ u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps) return freq; } -u32 intel_rps_read_punit_req(struct intel_rps *rps) +static u32 intel_rps_read_punit_req(struct intel_rps *rps, bool take_fw) { struct intel_uncore *uncore = rps_to_uncore(rps); struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; @@ -2162,7 +2162,8 @@ u32 intel_rps_read_punit_req(struct intel_rps *rps) u32 freq = 0; with_intel_runtime_pm_if_in_use(rpm, wakeref) - freq = intel_uncore_read(uncore, GEN6_RPNSWREQ); + freq = take_fw ? intel_uncore_read(uncore, GEN6_RPNSWREQ) : + intel_uncore_read_fw(uncore, GEN6_RPNSWREQ); return freq; } @@ -2176,7 +2177,7 @@ static u32 intel_rps_get_req(u32 pureq) u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) { - u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps)); + u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps, true)); return intel_gpu_freq(rps, freq); } @@ -2189,6 +2190,21 @@ u32 intel_rps_get_requested_frequency(struct intel_rps *rps) return intel_gpu_freq(rps, rps->cur_freq); } +static u32 intel_rps_read_punit_req_frequency_fw(struct intel_rps *rps) +{ + u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps, false)); + + return intel_gpu_freq(rps, freq); +} + +u32 intel_rps_get_requested_frequency_fw(struct intel_rps *rps) +{ + if (rps_uses_slpc(rps)) + return intel_rps_read_punit_req_frequency_fw(rps); + else + return intel_gpu_freq(rps, rps->cur_freq); +} + u32 intel_rps_get_max_frequency(struct intel_rps *rps) { struct intel_guc_slpc *slpc = rps_to_slpc(rps); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index 63511b826a97..a990f985ab23 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -41,6 +41,7 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); u32 intel_rps_read_actual_frequency(struct intel_rps *rps); u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps); u32 intel_rps_get_requested_frequency(struct intel_rps *rps); +u32 intel_rps_get_requested_frequency_fw(struct intel_rps *rps); u32 intel_rps_get_min_frequency(struct intel_rps *rps); u32 intel_rps_get_min_raw_freq(struct intel_rps *rps); int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val); @@ -50,7 +51,6 @@ int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val); u32 intel_rps_get_rp0_frequency(struct intel_rps *rps); u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); -u32 intel_rps_read_punit_req(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); u32 intel_rps_read_rpstat(struct intel_rps *rps); u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); From patchwork Wed Mar 8 05:33:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dixit, Ashutosh" X-Patchwork-Id: 13165245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E56C5C74A44 for ; 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a="334781366" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="334781366" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="820071526" X-IronPort-AV: E=Sophos;i="5.98,242,1673942400"; d="scan'208";a="820071526" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 21:33:26 -0800 From: Ashutosh Dixit To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915/pmu: Use common freq functions with sysfs Date: Tue, 7 Mar 2023 21:33:21 -0800 Message-Id: <20230308053321.939906-4-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230308053321.939906-1-ashutosh.dixit@intel.com> References: <20230308053321.939906-1-ashutosh.dixit@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vinay Belgaumkar , Rodrigo Vivi , dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Using common freq functions with sysfs in PMU (but without taking forcewake) solves the following issues (a) missing support for MTL (b) missing support for older generation (prior to Gen6) (c) missing support for slpc when freq sampling has to fall back to requested freq. It also makes the PMU code future proof where sometimes code has been updated for sysfs and PMU has been missed. Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/i915/gt/intel_rps.c | 10 ---------- drivers/gpu/drm/i915/gt/intel_rps.h | 1 - drivers/gpu/drm/i915/i915_pmu.c | 10 ++++------ 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 49df31927c0e..b03bfbe7ee23 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2046,16 +2046,6 @@ void intel_rps_sanitize(struct intel_rps *rps) rps_disable_interrupts(rps); } -u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) -{ - struct drm_i915_private *i915 = rps_to_i915(rps); - i915_reg_t rpstat; - - rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; - - return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); -} - u32 intel_rps_read_rpstat(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index a990f985ab23..60ae27679011 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -53,7 +53,6 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); u32 intel_rps_read_rpstat(struct intel_rps *rps); -u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); void intel_rps_raise_unslice(struct intel_rps *rps); void intel_rps_lower_unslice(struct intel_rps *rps); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index a76c5ce9513d..1a4c9fed257c 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -392,14 +392,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) * case we assume the system is running at the intended * frequency. Fortunately, the read should rarely fail! */ - val = intel_rps_read_rpstat_fw(rps); - if (val) - val = intel_rps_get_cagf(rps, val); - else - val = rps->cur_freq; + val = intel_rps_read_actual_frequency_fw(rps); + if (!val) + val = intel_rps_get_requested_frequency_fw(rps), add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT], - intel_gpu_freq(rps, val), period_ns / 1000); + val, period_ns / 1000); } if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {