From patchwork Wed Mar 8 15:39:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 13166007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99024C678D5 for ; Wed, 8 Mar 2023 15:40:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 20B9710E61B; Wed, 8 Mar 2023 15:39:52 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id C30A710E610; Wed, 8 Mar 2023 15:39:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289988; x=1709825988; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=UFsc11qcv0An3YTgsx2jUXx1nEcHzBdMgxW2w6BVW+0=; b=OKBocwngBdvTZveqUmBsJhRaFQizq1w0db24LoKVCUE/+65660Omtk/q FkVcrfl5GfY5z1Y+tLRpWuDAb7Lqp3A86w1Pxr+Fs2NDbJvcB4fJm1NV7 ByZK7dQPoCGl1P8JGe7jXswTf1gaJnXCnyiiQQsEt0vauaN++QVT3CM6J 6wSV4/Zz5sjA9R0qMJJm7J7xXr2dAruCCx5WA+xuIat+3LJeSXw16RoDW OjmOZykulnQPej95C2qwZdvs/QCGb5nE2TT6IOw3US9uoh3Pn6xWIcKHF inmLJfF5Gb8oAxKHM+6A5JkNwedi6jueuKEgE7Rci+9AJ/Qo9sGsQ2Cet Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703538" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703538" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160246" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160246" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:44 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:03 +0100 Subject: [PATCH v5 1/4] drm/i915/gt: make nop_clear_range public MIME-Version: 1.0 Message-Id: <20230308-guard_error_capture-v5-1-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin X-Mailer: b4 0.11.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andi Shyti , Chris Wilson , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Function nop_clear_range can be used instead of local implementations. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 842e69c7b21e49..b925da42c7cfc4 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -345,8 +345,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, ggtt->invalidate(ggtt); } -static void nop_clear_range(struct i915_address_space *vm, - u64 start, u64 length) +void nop_clear_range(struct i915_address_space *vm, u64 start, u64 length) { } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 5a775310d3fcb5..c15a4892e9f45d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -672,4 +672,6 @@ static inline struct sgt_dma { return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; } +void nop_clear_range(struct i915_address_space *vm, u64 start, u64 length); + #endif From patchwork Wed Mar 8 15:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 13166008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D904C6FD1E for ; Wed, 8 Mar 2023 15:40:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5176010E618; Wed, 8 Mar 2023 15:39:53 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D901F10E610; Wed, 8 Mar 2023 15:39:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289989; x=1709825989; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Se/biot0lVFjHYoy6HUt2Ws+mFr0uN1AGnXhhRrqKoQ=; b=eQF3cUZkaONnArQ3/cLOCk8JJSrEYKm02OqjUyJ3rstHF4YSmuJqgVCS JmNf9XRCYk4SVKBYVcfDUjeb+xMH45qkHIrbZQ84Cf+qu8AGtO2+F/tcG 2XBRsKVN3Xf2GwIImv+zK2xgzDwe7ggcvpalhO7RmIQeC0G4fmt/cvmAl zbe5rUrakFRKNl82Clx08otZHNoShCLyN38m4n9+bTzVHgPQ0ehwdae65 gMvs2XE1TiFEjaK8j4lYAK+HslBpqGhjoD1FhpQUdRa+ikOKsmmTPD0pg RirjLpC8KNvMaC+rumn9ADa7htlMxttezYp8P+Gh1qy8+oEypveoza+Uf Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703560" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703560" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160261" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160261" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:46 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:04 +0100 Subject: [PATCH v5 2/4] drm/i915/display: use nop_clear_range instead of local function MIME-Version: 1.0 Message-Id: <20230308-guard_error_capture-v5-2-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin X-Mailer: b4 0.11.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andi Shyti , Chris Wilson , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since nop_clear_range is visible it can be used here. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/display/intel_dpt.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index ad1a37b515fb1c..eb9d1a6cbfb9dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -73,11 +73,6 @@ static void dpt_insert_entries(struct i915_address_space *vm, gen8_set_pte(&base[i++], pte_encode | addr); } -static void dpt_clear_range(struct i915_address_space *vm, - u64 start, u64 length) -{ -} - static void dpt_bind_vma(struct i915_address_space *vm, struct i915_vm_pt_stash *stash, struct i915_vma_resource *vma_res, @@ -291,7 +286,7 @@ intel_dpt_create(struct intel_framebuffer *fb) i915_address_space_init(vm, VM_CLASS_DPT); vm->insert_page = dpt_insert_page; - vm->clear_range = dpt_clear_range; + vm->clear_range = nop_clear_range; vm->insert_entries = dpt_insert_entries; vm->cleanup = dpt_cleanup; From patchwork Wed Mar 8 15:39:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 13166010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7092C678D5 for ; Wed, 8 Mar 2023 15:40:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 361A310E624; Wed, 8 Mar 2023 15:40:00 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA9F210E616; Wed, 8 Mar 2023 15:39:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289991; x=1709825991; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=wG3vf2+xlpzOKdj5dCj9/rgBBguHqYIRNINuZ3j1/Dc=; b=B/H5xVnw5dK5S0V3k4FIXXu51SOH/RcZ6clyaFwkzkky976nDUTTtiNT o+kqaPE9Z8Pncd/1OnJO9OBzPX4hqBcFtqWZaN2rzVJVfguGUmhGr7GQc FOfo73djKMCU5nHS2c1U4ADQLxuBXOGZZkeB7or10O5t4kB+tSDUGbQAY pfgCcZDm8JITYqo2pGGYAnbvqx8rYBnSKQzMzDEpHJiR/ILKd9ZzMrGmj sL2Ee8/kWuiBToy9EGIugZ/MYTv1c520AzMFTNoU01ArqvADdQ/JjwU9B UTGSsDQjZ0CBOaEGehanxf+IdM9MKzhbT4NtzEiZ97PYMSNPvys3zSHyu A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703577" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703577" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160279" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160279" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:49 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:05 +0100 Subject: [PATCH v5 3/4] drm/i915/selftests: use nop_clear_range instead of local function MIME-Version: 1.0 Message-Id: <20230308-guard_error_capture-v5-3-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin X-Mailer: b4 0.11.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andi Shyti , Chris Wilson , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since nop_clear_range is visible it can be used here. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index ece97e4faacb97..89119e3970279f 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -57,11 +57,6 @@ static void mock_cleanup(struct i915_address_space *vm) { } -static void mock_clear_range(struct i915_address_space *vm, - u64 start, u64 length) -{ -} - struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) { struct i915_ppgtt *ppgtt; @@ -80,7 +75,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) ppgtt->vm.alloc_pt_dma = alloc_pt_dma; ppgtt->vm.alloc_scratch_dma = alloc_pt_dma; - ppgtt->vm.clear_range = mock_clear_range; + ppgtt->vm.clear_range = nop_clear_range; ppgtt->vm.insert_page = mock_insert_page; ppgtt->vm.insert_entries = mock_insert_entries; ppgtt->vm.cleanup = mock_cleanup; @@ -119,7 +114,7 @@ void mock_init_ggtt(struct intel_gt *gt) ggtt->vm.alloc_pt_dma = alloc_pt_dma; ggtt->vm.alloc_scratch_dma = alloc_pt_dma; - ggtt->vm.clear_range = mock_clear_range; + ggtt->vm.clear_range = nop_clear_range; ggtt->vm.insert_page = mock_insert_page; ggtt->vm.insert_entries = mock_insert_entries; ggtt->vm.cleanup = mock_cleanup; From patchwork Wed Mar 8 15:39:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 13166009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB4B4C678D5 for ; Wed, 8 Mar 2023 15:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31EC810E61E; Wed, 8 Mar 2023 15:39:58 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D30610E61E; Wed, 8 Mar 2023 15:39:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289994; x=1709825994; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=W+jwVlTRdjvktA1nEkWNcAT5iygeBJ8dB2aSEBElQ1U=; b=csvQDlhokR5QCJmRhryHrkhtbXIO4qAFkofp/Se/T7Nlg+EvA4Y4D9Q7 p60uC3+U6xnhjnEiqnVBv8DMfcZCSfTwUcUjztb8PobBnWTr9uryONIVE Hg0Hc7X97k6hMUnELfHZ0GIwzA2anAisyCYhAw6rcQpkxD7+b+JAJrdNE 781q6mX05gjQJBIAlf6at6Ae2Ys7f5cXMapOz++L8hS7k3LL4t3rF+8fA fW7Kwt2eQteh1Zc6nbEfgGI4fJqqAl+oaaRuin8MY/w+ftf6Hlg2RLOYz LCHdSwpTGbKh9cYf9XOYeMg+WFnLEgKYgNAn6OF8XPgZ6qGN+Nr7ol1RR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703593" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703593" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160296" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160296" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:51 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:06 +0100 Subject: [PATCH v5 4/4] drm/i915: add guard page to ggtt->error_capture MIME-Version: 1.0 Message-Id: <20230308-guard_error_capture-v5-4-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin X-Mailer: b4 0.11.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andi Shyti , Chris Wilson , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Write-combining memory allows speculative reads by CPU. ggtt->error_capture is WC mapped to CPU, so CPU/MMU can try to prefetch memory beyond the error_capture, ie it tries to read memory pointed by next PTE in GGTT. If this PTE points to invalid address DMAR errors will occur. This behaviour was observed on ADL and RPL platforms. To avoid it, guard scratch page should be added after error_capture. The patch fixes the most annoying issue with error capture but since WC reads are used also in other places there is a risk similar problem can affect them as well. v2: - modified commit message (I hope the diagnosis is correct), - added bug checks to ensure scratch is initialized on gen3 platforms. CI produces strange stacktrace for it suggesting scratch[0] is NULL, to be removed after resolving the issue with gen3 platforms. v3: - removed bug checks, replaced with gen check. v4: - change code for scratch page insertion to support all platforms, - add info in commit message there could be more similar issues v5: - check for nop_clear_range instead of gen8 (Tvrtko), - re-insert scratch pages on resume (Tvrtko) Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index b925da42c7cfc4..8fb700fde85c8f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -502,6 +502,21 @@ static void cleanup_init_ggtt(struct i915_ggtt *ggtt) mutex_destroy(&ggtt->error_mutex); } +static void +ggtt_insert_scratch_pages(struct i915_ggtt *ggtt, u64 offset, u64 length) +{ + struct i915_address_space *vm = &ggtt->vm; + + if (vm->clear_range != nop_clear_range) + return vm->clear_range(vm, offset, length); + + while (length > 0) { + vm->insert_page(vm, px_dma(vm->scratch[0]), offset, I915_CACHE_NONE, 0); + offset += I915_GTT_PAGE_SIZE; + length -= I915_GTT_PAGE_SIZE; + } +} + static int init_ggtt(struct i915_ggtt *ggtt) { /* @@ -550,8 +565,12 @@ static int init_ggtt(struct i915_ggtt *ggtt) * paths, and we trust that 0 will remain reserved. However, * the only likely reason for failure to insert is a driver * bug, which we expect to cause other failures... + * + * Since CPU can perform speculative reads on error capture + * (write-combining allows it) add scratch page after error + * capture to avoid DMAR errors. */ - ggtt->error_capture.size = I915_GTT_PAGE_SIZE; + ggtt->error_capture.size = 2 * I915_GTT_PAGE_SIZE; ggtt->error_capture.color = I915_COLOR_UNEVICTABLE; if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture)) drm_mm_insert_node_in_range(&ggtt->vm.mm, @@ -561,11 +580,15 @@ static int init_ggtt(struct i915_ggtt *ggtt) 0, ggtt->mappable_end, DRM_MM_INSERT_LOW); } - if (drm_mm_node_allocated(&ggtt->error_capture)) + if (drm_mm_node_allocated(&ggtt->error_capture)) { + u64 start = ggtt->error_capture.start; + u64 size = ggtt->error_capture.size; + + ggtt_insert_scratch_pages(ggtt, start, size); drm_dbg(&ggtt->vm.i915->drm, "Reserved GGTT:[%llx, %llx] for use by error capture\n", - ggtt->error_capture.start, - ggtt->error_capture.start + ggtt->error_capture.size); + start, start + size); + } /* * The upper portion of the GuC address space has a sizeable hole @@ -1256,6 +1279,10 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt) flush = i915_ggtt_resume_vm(&ggtt->vm); + if (drm_mm_node_allocated(&ggtt->error_capture)) + ggtt_insert_scratch_pages(ggtt, ggtt->error_capture.start, + ggtt->error_capture.size); + ggtt->invalidate(ggtt); if (flush)