From patchwork Fri Mar 10 08:05:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C3A2C74A4B for ; Fri, 10 Mar 2023 08:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbjCJIFs (ORCPT ); Fri, 10 Mar 2023 03:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbjCJIFq (ORCPT ); Fri, 10 Mar 2023 03:05:46 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83F7FADC1A; Fri, 10 Mar 2023 00:05:44 -0800 (PST) Received: from cryzen.lan (cpc87451-finc19-2-0-cust61.4-2.cable.virginm.net [82.11.51.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: tanureal) by madras.collabora.co.uk (Postfix) with ESMTPSA id 770016603057; Fri, 10 Mar 2023 08:05:42 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435542; bh=ebCM08ufe5E1iAUMnwY8wnvvUUxgSIMI/R2bN0GLQpg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Maju10yWI03tnIoSxVSfo7QR92+4mOr9qV0DlC536arN4Em9X9GPJswonO7+I6phb B8uLGXv6E0EkEMIvpuUexz0S0XJMz+W+aMt5dX1IVcYnWM4gDItUq352e/IDfTaDZo 3/lVnUNHECJm4h5IW/lPwb1ing4D5wMVUXzX8vgtNKbvUhbfHgaJCtTnty9fcRTSf4 WZNW1/Nt4ctJwCgqe6N8dycf6jaORaV3YCGjYIbjyFlbptufWEzluAuojFw+DfNZvC K1wmtPOf2ocTJ5xpE553vZ8UCIK3VM/7fm8abE35VpJTIJlutSeTfo9P1R1jzw9hGm fG06Ni0L5hMKA== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com, Robin Murphy Subject: [PATCH 1/7] irqchip/gic-v3: Add a DMA Non-Coherent flag Date: Fri, 10 Mar 2023 08:05:12 +0000 Message-Id: <20230310080518.78054-2-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The GIC600 integration in RK356x, used in rk3588, doesn't support any of the shareability or cacheability attributes, and requires both values to be set to 0b00 for all the ITS and Redistributor tables. This is loosely based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Suggested-by: Robin Murphy Signed-off-by: Lucas Tanure --- drivers/irqchip/irq-gic-v3-its.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 973ede0197e3..1c334dfeb647 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -42,6 +42,7 @@ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) +#define ITS_FLAGS_DMA_NON_COHERENT (1ULL << 3) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) @@ -2359,6 +2360,13 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, its_write_baser(its, baser, val); tmp = baser->val; + if (its->flags & ITS_FLAGS_DMA_NON_COHERENT) { + if (tmp & GITS_BASER_SHAREABILITY_MASK) + tmp &= ~GITS_BASER_SHAREABILITY_MASK; + else + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); + } + if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { /* * Shareability didn't stick. Just use @@ -3055,6 +3063,7 @@ static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set) static void its_cpu_init_lpis(void) { + struct its_node *its = list_first_entry(&its_nodes, struct its_node, entry); void __iomem *rbase = gic_data_rdist_rd_base(); struct page *pend_page; phys_addr_t paddr; @@ -3096,6 +3105,9 @@ static void its_cpu_init_lpis(void) gicr_write_propbaser(val, rbase + GICR_PROPBASER); tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); + if (its->flags & ITS_FLAGS_DMA_NON_COHERENT) + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; + if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { /* @@ -3120,6 +3132,9 @@ static void its_cpu_init_lpis(void) gicr_write_pendbaser(val, rbase + GICR_PENDBASER); tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); + if (its->flags & ITS_FLAGS_DMA_NON_COHERENT) + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; + if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { /* * The HW reports non-shareable, we must remove the @@ -5005,6 +5020,7 @@ static int __init its_compute_its_list_map(struct resource *res, static int __init its_probe_one(struct resource *res, struct fwnode_handle *handle, int numa_node) { + struct device_node *np = to_of_node(handle); struct its_node *its; void __iomem *its_base; u64 baser, tmp, typer; @@ -5076,6 +5092,9 @@ static int __init its_probe_one(struct resource *res, its->get_msi_base = its_irq_get_msi_base; its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; + if (np && !of_dma_is_coherent(np)) + its->flags |= ITS_FLAGS_DMA_NON_COHERENT; + its_enable_quirks(its); err = its_alloc_tables(its); @@ -5095,6 +5114,9 @@ static int __init its_probe_one(struct resource *res, gits_write_cbaser(baser, its->base + GITS_CBASER); tmp = gits_read_cbaser(its->base + GITS_CBASER); + if (its->flags & ITS_FLAGS_DMA_NON_COHERENT) + tmp &= ~GITS_CBASER_SHAREABILITY_MASK; + if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { /* From patchwork Fri Mar 10 08:05:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94192C6FD19 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435543; bh=aXDW9FM3v6N1gp/G6svdu0Iv9rfB/0Z8Inu2S3xCf4E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fh+3hbrZX63tbEgCu8QMhiNdvHIvJ5tdpSdE3dTMSQQ1IHv3G/OkOYp587KeXjw0H Wte5VVGJez2NsEGK//ZaFmtSdyvqpRqlNGd7BxI2OxdywTkzTBcj2qWXu9Zc8hBS1t FyczdNcZcgqYA4btHApUzWydm858U28q8YtAtjFDOVpP+MyWBBJRQ2i0NqHit/qcBX VSzsvPi0sDRbrE9J3wtfLgV23V7UUqmjgl/pv5JkKll+vXESPsWGCTLuVCjr9ieAfb VC2gm6t8YHh6OfxNeo0Ldu2Q55JyQ43MM23j7Cjmc0ZF8JdZLn183AXvtbY8sI+t2/ /QBgzL9dAMtFg== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com Subject: [PATCH 2/7] PCI: rockchip-dwc: Add rk3588 compatible line Date: Fri, 10 Mar 2023 08:05:13 +0000 Message-Id: <20230310080518.78054-3-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org RK3588 can use the same PCIe driver as rk3568 Signed-off-by: Lucas Tanure --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index c1e7653e508e..435b717e5bc6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -354,6 +354,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) static const struct of_device_id rockchip_pcie_of_match[] = { { .compatible = "rockchip,rk3568-pcie", }, + { .compatible = "rockchip,rk3588-pcie", }, {}, }; From patchwork Fri Mar 10 08:05:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168849 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65604C6FD19 for ; Fri, 10 Mar 2023 08:05:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjCJIFt (ORCPT ); Fri, 10 Mar 2023 03:05:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230111AbjCJIFq (ORCPT ); Fri, 10 Mar 2023 03:05:46 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0209CB1B3D; Fri, 10 Mar 2023 00:05:45 -0800 (PST) Received: from cryzen.lan (cpc87451-finc19-2-0-cust61.4-2.cable.virginm.net [82.11.51.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: tanureal) by madras.collabora.co.uk (Postfix) with ESMTPSA id 65BC46603083; Fri, 10 Mar 2023 08:05:43 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435543; bh=+ZX7vYLxaBazI08zF5lNguc40/rFNVo9sCm+2OiHagA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q6hA6R1SqYQZ8YdpMwHANgLV+I9hzt66+OemjAwE845VtxO74K9Po0yR/hVpmVMyu f6TgbY9c6KP0RDpUg410/rYRZ+GOdjEpA2EQqx3gefaidQAsb1eD3Q8hE7Fq/+GFHm OeTDg5c54bmdFCsPx3xsrqHpDCFrSkfOr5OWemVy2McvZwdhtmPWBQ8piV02l/QsAC iFNLsZIStXoDWuJURmmWRetliS5IV2EvNx3bjf3rDAl2/nJQmI25U7/JeQXiifJAl6 LwysFb/wruv0JXp1RVe8oFJ8Mf/cLKf0XGbWgdgxdl55E79Vf6mV/vyR97+SmkeQKN uG839CYQzQbTA== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com Subject: [PATCH 3/7] dt-bindings: phy: rockchip: Add rk3588 compatible line Date: Fri, 10 Mar 2023 08:05:14 +0000 Message-Id: <20230310080518.78054-4-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org RK3568 Naneng Combo Phy driver can support RK3588 with the additional clocks and initial configuration, so add the compatible line. Signed-off-by: Lucas Tanure Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 8d8698412de0..9ae514fa7533 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -13,6 +13,7 @@ properties: compatible: enum: - rockchip,rk3568-naneng-combphy + - rockchip,rk3588-naneng-combphy reg: maxItems: 1 From patchwork Fri Mar 10 08:05:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168853 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92934C64EC4 for ; Fri, 10 Mar 2023 08:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229817AbjCJIFy (ORCPT ); Fri, 10 Mar 2023 03:05:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230155AbjCJIFr (ORCPT ); Fri, 10 Mar 2023 03:05:47 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D164B718B; Fri, 10 Mar 2023 00:05:45 -0800 (PST) Received: from cryzen.lan (cpc87451-finc19-2-0-cust61.4-2.cable.virginm.net [82.11.51.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: tanureal) by madras.collabora.co.uk (Postfix) with ESMTPSA id D95BB66030A1; Fri, 10 Mar 2023 08:05:43 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435544; bh=Ugt/cIk2aYivDAu6VNt7dUsTeai7krVEsAmcZ9e7wWs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CevpKLSirdoo2LRhQoamcTSJtt7F++p/wpiqgJW7eBklKIdW4EJ4vfYNY0kUZClX9 +YMt0O23e8kqR31xxPwcmoiFvvJXoIc9U/dugfsZhmhU4+RDxSARFdSC+s1tO8ai2n WsAfeDzQm+E/bbgdbS8v441+Mm0LGU5WnpGtGFRDOPVeE4jAsfA7yKtJm8bWlkKSPf VbB8Oq6kBpIQGe0gqCi1SYUzJO7HE/8Y2OCQxU64oj8TjCcVeyJCymwiEBb0gKrl7W qlO8JCZ0PM5V+j0xXwXmmDzCQk/87w4aAM9fzYmxij1wS3Rx1LsfFom03zQojeSx3/ 3JgO9x9VrouMA== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com, Andrew Powers-Holmes Subject: [PATCH 4/7] phy: rockchip: Add naneng combo phy support for RK3588 Date: Fri, 10 Mar 2023 08:05:15 +0000 Message-Id: <20230310080518.78054-5-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for RK3588 combo phy This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Co-developed-by: Andrew Powers-Holmes Signed-off-by: Andrew Powers-Holmes Signed-off-by: Lucas Tanure --- .../rockchip/phy-rockchip-naneng-combphy.c | 184 ++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 7b213825fb5d..7b8b001e4f9e 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -63,6 +63,9 @@ #define PHYREG18 0x44 #define PHYREG18_PLL_LOOP 0x32 +#define PHYREG27 0x6C +#define PHYREG27_RX_TRIM_RK3588 0x4C + #define PHYREG32 0x7C #define PHYREG32_SSC_MASK GENMASK(7, 4) #define PHYREG32_SSC_DIR_SHIFT 4 @@ -114,7 +117,10 @@ struct rockchip_combphy_grfcfg { struct combphy_reg con2_for_sata; struct combphy_reg con3_for_sata; struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_con1_for_sata; struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg pipe_pcie1l0_sel; + struct combphy_reg pipe_pcie1l1_sel; }; struct rockchip_combphy_cfg { @@ -559,11 +565,189 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, }; +static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->type) { + case PHY_TYPE_PCIE: + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, + PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + PHYREG15); + val |= PHYREG15_CTLE_EN; + writel(val, priv->mmio + PHYREG15); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, + PHYREG33); + + /* Enable controlling random jitter. */ + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, + PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, + PHYREG6); + + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + PHYREG15); + val |= PHYREG15_CTLE_EN; + writel(val, priv->mmio + PHYREG15); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; + val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; + writel(val, priv->mmio + PHYREG7); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, + val, PHYREG15); + + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = 4 << PHYREG33_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + val, PHYREG33); + + /* Enable controlling random jitter. */ + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); + + /* Set up su_trim: */ + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + } else if (priv->type == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; + val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; + val |= PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); + + val = readl(priv->mmio + PHYREG14); + val |= PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + PHYREG14); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + PHYREG8); + val |= PHYREG8_SSC_EN; + writel(val, priv->mmio + PHYREG8); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, + .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, + .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, + .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, +}; + +static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { + .grfcfg = &rk3588_combphy_grfcfgs, + .combphy_cfg = rk3588_combphy_cfg, +}; + static const struct of_device_id rockchip_combphy_of_match[] = { { .compatible = "rockchip,rk3568-naneng-combphy", .data = &rk3568_combphy_cfgs, }, + { + .compatible = "rockchip,rk3588-naneng-combphy", + .data = &rk3588_combphy_cfgs, + }, { }, }; MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); From patchwork Fri Mar 10 08:05:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B311C76186 for ; Fri, 10 Mar 2023 08:05:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbjCJIFw (ORCPT ); Fri, 10 Mar 2023 03:05:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230167AbjCJIFr (ORCPT ); Fri, 10 Mar 2023 03:05:47 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2F4AB04BC; Fri, 10 Mar 2023 00:05:46 -0800 (PST) Received: from cryzen.lan (cpc87451-finc19-2-0-cust61.4-2.cable.virginm.net [82.11.51.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: tanureal) by madras.collabora.co.uk (Postfix) with ESMTPSA id 56DAF66030BE; Fri, 10 Mar 2023 08:05:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435544; bh=iZfz5TvdpibqFz6qT4kNJtS6iMl9+BPz7aSCwohid2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g2ao3nkFY4N1PCsl0X3CjrEoTMMZ8bcZmmRThO5eZRp1ayRCTRgJw48hhFw5uqvVi lgln1/6maYEc7xGSGnP3aiCn6k2dWuK+v1lHIC7sBgezy/12aTYMdckKiYsMmjjs/h jLGWhpnxK93wiCGyAgZ6WCNYEJvDhINy4jFtCOLB1neIMjZSo3te/Xwl2K7POLy/mJ pZB7W+iN1EoGKe87QkQvSBAuz9Q7jPIhn2nCEYQOowXvsS4Jf00Gj9qCzGP6CUqzkA iMKDuEgvE85OsVvCgTU8Ghb0da4JPij1iZOVw4lZKank0NZd5rOEvobswjnvDwDMBs 7GSp1xvZKlLRw== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com Subject: [PATCH 5/7] arm64: dts: rockchip: Add ITS GIC600 configuration for rk3588s Date: Fri, 10 Mar 2023 08:05:16 +0000 Message-Id: <20230310080518.78054-6-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for Interrupts to be translated by the GIC-600 Interrupt Translation Service (ITS). ITS provides a software mechanism for translating message-based interrupts into Locality-specific Peripheral Interrupts (LPIs). This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Plus comments of Robin Murphy about Non-Coherent properties. Signed-off-by: Lucas Tanure --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 24919cb5c153..695aed05eba2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1594,6 +1594,25 @@ gic: interrupt-controller@fe600000 { mbi-ranges = <424 56>; msi-controller; #interrupt-cells = <4>; + ranges; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + dma-noncoherent; + #msi-cells = <1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + power-domains = <&power RK3588_PD_PCIE>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + msi-controller; + dma-noncoherent; + #msi-cells = <1>; + reg = <0x0 0xfe660000 0x0 0x20000>; + power-domains = <&power RK3588_PD_PCIE>; + }; ppi-partitions { ppi_partition0: interrupt-partition-0 { From patchwork Fri Mar 10 08:05:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A0D2C6FA99 for ; Fri, 10 Mar 2023 08:05:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbjCJIFv (ORCPT ); Fri, 10 Mar 2023 03:05:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230181AbjCJIFs (ORCPT ); Fri, 10 Mar 2023 03:05:48 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3111B1B38; Fri, 10 Mar 2023 00:05:46 -0800 (PST) Received: from cryzen.lan (cpc87451-finc19-2-0-cust61.4-2.cable.virginm.net [82.11.51.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: tanureal) by madras.collabora.co.uk (Postfix) with ESMTPSA id C3A0166030DE; Fri, 10 Mar 2023 08:05:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435545; bh=MCl+JS4GYShkMG1kJrLBfxKIMkW5axgopzJ3+UFInTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YlJoeCfaLeQ5K0EfrokN/aIYO4G5hpSxm4BIz3TP33eSay1Cn/x/QIwTiT8dxUhOz zDCngdYFFxczyTS+17tmjlFndUmISr0m3pMs/k9vXXHx9hT3aBxQtNnL+xwW6W3FKz GVUu3henJBgLw4F978mqt2RIp7phtozVWX2hQGYdstjpUzyqRBMjn99v7236dnAFnA HAg4iIzP2AoSAm+tKzLbTkPhK+Nva15UmX2rN1wUw6oEFJ3rP43/VU13exOryyVJa0 bOYX2ggSSR0UQogIgB7m1W5vLAOsBBuJDnIKRZMlvxtUXhqTBwuaNU6HoJJg/+swwy NMOzlvO0kIfeg== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com Subject: [PATCH 6/7] arm64: dts: rockchip: Add PCIE2.0x1 lane @fe190000 for RK3588s Date: Fri, 10 Mar 2023 08:05:17 +0000 Message-Id: <20230310080518.78054-7-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIE2.0x1 lane @fe190000 phy node for RK3588s. This lane is used for network controller RTL8125 in ROCK 5B. This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Signed-off-by: Lucas Tanure --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 78 +++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 695aed05eba2..bb66a8252d1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3588"; @@ -878,6 +879,83 @@ cru: clock-controller@fd7c0000 { rockchip,grf = <&php_grf>; #clock-cells = <1>; #reset-cells = <1>; + + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; i2c0: i2c@fd880000 { From patchwork Fri Mar 10 08:05:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 13168850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A680AC76188 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1678435545; bh=LOi/siaqM76rHO4gX21yMZsTjTCPrx6+roVKTERlr6Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FbW3Tac8MSWHsTylUudxehstgS7z+O257JcutLLEmD5INT4MH2QtgyZbVEy5pCt66 MRxJ+De2AlznRsy52qpwJqrjUknHC2dlA4FpYxbdIGKJnNLqa+yuyuNVeIcP8ufRh5 zxU9H/kEVM7X27C1cqXcbOzYUxxclLJ4jEr6Mf6VTQywRMyyXSXYFCWN394LhLVZQa dmNii/CIGrhpYdRqQEBTyNV276lzeZxyA9pQOGh39KOsOis2SNWYZ1oYrgGgwZbZEb nT9F6xjO8g+1c12jBOyusPtID0w8jWmu4CIpZWFdYx+oZqGk+TnjAmBVrqTeMsAcHh DB6L0qSbs4i4g== From: Lucas Tanure To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Krzysztof Wilczynski , Bjorn Helgaas Cc: Qu Wenruo , Piotr Oniszczuk , Peter Geis , Kever Yang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Lucas Tanure , kernel@collabora.com Subject: [PATCH 7/7] arm64: dts: rockchip: RK3588s: Enable PCIE2.0x1 @fe190000 Date: Fri, 10 Mar 2023 08:05:18 +0000 Message-Id: <20230310080518.78054-8-lucas.tanure@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310080518.78054-1-lucas.tanure@collabora.com> References: <20230310080518.78054-1-lucas.tanure@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIE2.0x1 @fe190000 for RTL8125 network controller in Rock 5B board. This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Signed-off-by: Lucas Tanure --- .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index df8b135cf223..c4ae20ad2fd7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -36,6 +36,15 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { regulator-max-microvolt = <1100000>; vin-supply = <&vcc5v0_sys>; }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; }; &sdhci { @@ -70,3 +79,12 @@ &sdmmc { status = "okay"; }; +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +};