From patchwork Sun Mar 12 16:59:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9989C6FD19 for ; Sun, 12 Mar 2023 17:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjCLRDF (ORCPT ); Sun, 12 Mar 2023 13:03:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231219AbjCLRC5 (ORCPT ); Sun, 12 Mar 2023 13:02:57 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00194392B8 for ; Sun, 12 Mar 2023 10:02:42 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id h9so10317470ljq.2 for ; Sun, 12 Mar 2023 10:02:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640561; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=bMzb4+f+2BylShTzIH+kD9h/2l/yJ2pk3VVMD+904ak=; b=opTkg4/pM4iFDUfQ7RQLLTuXPkbRDqLNmRLCBFpniSvDiwxAf1/ttMjEMDo/aPkePx 1iVXJpIef22xalCd8EKVQJ/GFS+FLl7hZZQFEvT+zyOwTxHK0MGSqntc6V+AEx2UEE/h AQmJtQXo7fB/3Z7GG1eLmfaSsWr8p+WpPDc1Dy8GKbS50eKPWG1E+iHpJ9fmQZto40rR YDkbi7aoMjtIzVw2yj33aQ/TXg6xp4ycVo1iBX2uKWPstXJAcF/Fn8PRvzDs+SGvnFx+ bj6zH4XUj6xP0CbdKuzCUDz5lUzjFyLCoORBDkkSayq6pUK8yqLXdzpqYsrw4rHbVCyL 8QVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640561; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=bMzb4+f+2BylShTzIH+kD9h/2l/yJ2pk3VVMD+904ak=; b=0DRTRviB6huSAsG/xK3rwDW29oj3Yb/uSDIyAOxYXXLjKhJnqcOykyi1HeAnrIlL4d fdzPH4VTz+LyXj+FwcV4ppWVG7Sg2Qx6o57HVlkSTYJLUacec89Rdu5lsNodUCjoPUgS xr6VcgqhAsM0W0qhe1+gVJfmITVi6F46ftY6MfDYGZaRMw3vJrJK2qBhkVu74Ip2P2fg FDdGbKreZYhJjVcPhYexmK4sau2/j3w17kAbQ/CYKqIRuSzEzfMxhj99SFg+i2M/rmGL 5O2HE47+Z1JtxuufdRDeYHYpfu/4myZVCKUbxHjES+41E+czyCFvr1W80WQjjFJ3LIpn 1qKw== X-Gm-Message-State: AO0yUKVyJjDmpnUNQ7Hq6wrLxZowNRmybRJzeL1UlKnSkhc4REF9eQhe bnzys5LMvzIgL9huCrtu8QYjxQM/dqRna+IM X-Google-Smtp-Source: AK7set+ekRAKV143eBaUpaiijxY+5TrJiLv0lrAfNVCAZ//HN3hOJZHcNBbpOuVG2fN9Ez5iHXtdMA== X-Received: by 2002:a05:651c:1987:b0:295:a32b:9537 with SMTP id bx7-20020a05651c198700b00295a32b9537mr12077435ljb.43.1678640561062; Sun, 12 Mar 2023 10:02:41 -0700 (PDT) Received: from 0001-dt-bindings-exynos-dw-mshc-common-add-exynos78xx-var.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id e16-20020a2e8ed0000000b0029571d505a1sm701384ljl.80.2023.03.12.10.02.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:02:40 -0700 (PDT) Message-Id: <1678640497.9030156-1-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:29 +0300 Subject: [PATCH v4 1/3] dt-bindings: exynos-dw-mshc-common: add exynos78xx variants To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. Add two new compatible strings, "samsung,exynos78xx-dw-mshc" and "samsung,exynos78xx-dw-mshc-smu" respectively, to denote exynos78xx boards that need this quirk. But it's very possible that all "samsung,exynos7-dw-mshc" boards are actually affected. --- .../devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index fdaa18481..a72a67792 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -22,6 +22,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos78xx-dw-mshc + - samsung,exynos78xx-dw-mshc-smu - axis,artpec8-dw-mshc reg: From patchwork Sun Mar 12 16:59:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2831C6FD1C for ; Sun, 12 Mar 2023 17:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229845AbjCLRDR (ORCPT ); Sun, 12 Mar 2023 13:03:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231232AbjCLRDK (ORCPT ); Sun, 12 Mar 2023 13:03:10 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3786C1024E for ; Sun, 12 Mar 2023 10:03:08 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id m6so12869408lfq.5 for ; Sun, 12 Mar 2023 10:03:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640586; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=yNccjh9ehO5GzEa2MK08HfZDjH6EdpZB9/Uqslpa9j8=; b=GBebKeXkPCIvN9CvF9Uv06Be+Od1C8V2cwgfOHMDFEunwxnsijCUcOZIA5UFEX0RIA 19LKlsxMcVe6zazuKH4HxO6A3cYlrl0Ti84OXr2in9b7m15wBBHmia/TLHpgbnDBglad KYMVZq+6HLmCD93vqhqttIw5UhNd4b95Uo6tQo0LgfRG03Yp42ot0jXJyqCwrEBOH561 WKnflqDeQhWXVuplaypwj7q7+2ItHfkNZ86vDLo15nME0jdndWgEoIyGlotOcEJ5zol0 ya37y+UkY7IcSzvCH+xR4LFWHgsjpz/oX9b+NBXFRL4i4WDIeEJ9A1bun3/4ce1Axrlk 05lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640586; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=yNccjh9ehO5GzEa2MK08HfZDjH6EdpZB9/Uqslpa9j8=; b=uw/EAxfN3mXkyiXH+Di1XzN2VIxwoIsUaSRcSFnABjm2i0LeOcn1OqM1uRt5S5tipl sReIxYAfUPHK1lKJQQ46U8eUeEB2POSCwXEdZ7Fxt/oL1f9V6v5t6cN7dSvs02vDIJF+ 6+9j6tKeq6/AYsgP2lC1boMebcf5QXE7NfXq1C0R36/7v13OMEPY1RlDipodjnek+wSt YVRsxTFheFu3wS5MDI07JhhmZrYxnALwAzcPxkDMWuVrycPbmzYiNGYOc8I4KB2FuMgT CyhNkghP5ILRTTK+/DrYER4VQkGxKRejAEZsrtonl7Nz34rrNzacG9LH69smoDVJBslm HGkA== X-Gm-Message-State: AO0yUKWI0Jt8AyzYshnQo5X7w0wosb8h6t6uoEM+a7zGtftBmJyE75h6 EEbkW0hmj/Qv7hyRejPtPE5ELXLwVFm9Lu4d X-Google-Smtp-Source: AK7set+d427OnZV5tUz+Hop1WyeOExN3uza9xAgETWDMBsT6dUAEwPT8nVDYk2koaXKIzt//Rc+DZQ== X-Received: by 2002:ac2:5103:0:b0:4db:3848:86af with SMTP id q3-20020ac25103000000b004db384886afmr8505415lfb.12.1678640586292; Sun, 12 Mar 2023 10:03:06 -0700 (PDT) Received: from 0002-arm64-dts-exynos-fix-wrong-mmc-compatible-in-exynos7.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id l23-20020ac24317000000b004d8584970b8sm698249lfh.226.2023.03.12.10.03.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:03:06 -0700 (PDT) Message-Id: <1678640497.9030156-2-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:29 +0300 Subject: [PATCH v4 2/3] arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This DW-MMC variant is not actually compatible with "samsung,exynos7-dw-mshc-smu", and requires an additional quirk to handle very short data transfers. Update the compatible string to "samsung,exynos78xx-dw-mshc-smu" to reflect this fact. --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0..4b94ac9da 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -294,7 +294,7 @@ pmu_system_controller: system-controller@11c80000 { }; mmc_0: mmc@13500000 { - compatible = "samsung,exynos7-dw-mshc-smu"; + compatible = "samsung,exynos78xx-dw-mshc-smu"; reg = <0x13500000 0x2000>; interrupts = ; #address-cells = <1>; From patchwork Sun Mar 12 16:59:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C87C6FA99 for ; Sun, 12 Mar 2023 17:03:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230419AbjCLRDr (ORCPT ); Sun, 12 Mar 2023 13:03:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231236AbjCLRDn (ORCPT ); Sun, 12 Mar 2023 13:03:43 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A11321968C for ; Sun, 12 Mar 2023 10:03:36 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id bi9so12870234lfb.2 for ; Sun, 12 Mar 2023 10:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640616; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=cPk/h023+CvWv4LEM2Nr7aafr5OCIjbP3l84sbGJHt4=; b=D0+TCYayZtfKkpdrpjHQMVuUsjpxG6KnrOL/Em4l02aFJqlXCS0yAtsMZoW//He5Hg AOqm+RsrzSDRCS6vNmESHKZ39JbUZWIui8QUH6HM3RK4/9CI0xMWU/Thvrzn3GaMenO9 ph6CPJRDdnIaN8a3rBb14kKEHRTJFAlmVt7bOISVpiFF3zpaRlXTZN8/HvT8y9biMtET cqVmYMEHVX6rXMQ48Uvb+ti4WVQt/04Bk4b4QlyL6Ob2b0JNkWBgpRdJoyeYmeuh1zk/ LsH0imhM89QRTBVNtn50ShOW9jaDmciXXV6SFaFaOklEDjAksnrqZ3J84pPVTlvxo5LI r+vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640616; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=cPk/h023+CvWv4LEM2Nr7aafr5OCIjbP3l84sbGJHt4=; b=JHgGBR+OCYiVM7IHo1fA3DZp+mrdPsF9WnjYj6Po1FYblC8ImY7Ft+1NwdUl29bAHh 6UekoOmNJgYk9/bfWZ5+tGiKZdN7zXwdrWmXGo9RiA9QPdjtYgNzvEpwX2Wpt632M9HO QFaXtINs8o8wj2bpGMYF0Fag6G9RZv61/urVXUUwVmnvbG6hPAuxnu9mqKtS21rvPXVb kqlKuSHoR6d3UbTs8c6MVgAmoXmmMIYqxTxF/WzUmjteD1IXpSeBFPa200UHQsoqYyR7 BE90i2fyIm8we6eOcbm/U9E03q+47uVi4Q8Qyo+lIhIdVhmxgIiOCWXC+PGsZ6yMdOWD XdCw== X-Gm-Message-State: AO0yUKW6cQyfuqeWyfInn4AfczXkqKIigY6jJK+zrU6qRmqecPEgxy0X DlPIW2xAuHmpAueSlf4QBNLS7vDel/uBwrEq X-Google-Smtp-Source: AK7set8BKdZPfrteRZnPg/lwsut4ffxb3i/DNLgo7z8HmNyuZ3dwJOAYPow/YKljy8iSHfcJcF9xxg== X-Received: by 2002:ac2:555a:0:b0:4de:6973:82aa with SMTP id l26-20020ac2555a000000b004de697382aamr9119751lfk.68.1678640615852; Sun, 12 Mar 2023 10:03:35 -0700 (PDT) Received: from 0003-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id i4-20020ac25d24000000b004b7033da2d7sm302873lfb.128.2023.03.12.10.03.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:03:35 -0700 (PDT) Message-Id: <1678640497.9030156-3-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:30 +0300 Subject: [PATCH v4 3/3] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc-exynos.c | 41 ++++++++++- drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 3 files changed, 162 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 9f20ac524..768774f22 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,8 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_EXYNOS78XX, + DW_MCI_TYPE_EXYNOS78XX_SMU, DW_MCI_TYPE_ARTPEC8, }; @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos7-dw-mshc-smu", .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible = "samsung,exynos78xx-dw-mshc", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX, + }, { + .compatible = "samsung,exynos78xx-dw-mshc-smu", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX_SMU, }, { .compatible = "axis,artpec8-dw-mshc", .ctrl_type = DW_MCI_TYPE_ARTPEC8, @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else @@ -101,7 +111,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *host) * set for non-ecryption mode at this time. */ if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { mci_writel(host, MPSBEGIN0, 0); mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | @@ -127,6 +138,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { + /* Quirk needed for certain Exynos SoCs */ + host->quirks |= DW_MMC_QUIRK_FIFO64_32; + } + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { /* Quirk needed for the ARTPEC-8 SoC */ host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; @@ -144,6 +161,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -153,6 +172,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -223,6 +244,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -231,6 +254,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -410,6 +435,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else @@ -423,6 +450,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -430,6 +459,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -444,6 +475,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -454,6 +487,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -633,6 +668,10 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos7-dw-mshc-smu", .data = &exynos_drv_data, }, + { .compatible = "samsung,exynos78xx-dw-mshc", + .data = &exynos_drv_data, }, + { .compatible = "samsung,exynos78xx-dw-mshc-smu", + .data = &exynos_drv_data, }, { .compatible = "axis,artpec8-dw-mshc", .data = &artpec_drv_data, }, {}, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..9fe816c61 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) } } +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] = mci_fifo_readl(addr); + proxy[1] = mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data = host->data; + int init_cnt = cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len = dw_mci_push_part_bytes(host, buf, cnt); + + buf += len; + cnt -= len; + + if (host->part_buf_count == 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count = 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf += len; + cnt -= len; + /* push data from aligned buffer into fifo */ + for (i = 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf = pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) == + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + + for (i = 0; i < items; ++i) + aligned_buf[i] = mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf += len; + cnt -= len; + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + *pdata++ = mci_fifo_readq_32(host->fifo_reg); + buf = pdata; + } + if (cnt) { + host->part_buf = mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3367,8 +3480,13 @@ int dw_mci_probe(struct dw_mci *host) width = 16; host->data_shift = 1; } else if (i == 2) { - host->push_data = dw_mci_push_data64; - host->pull_data = dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data = dw_mci_push_data64_32; + host->pull_data = dw_mci_pull_data64_32; + } else { + host->push_data = dw_mci_push_data64; + host->pull_data = dw_mci_pull_data64; + } width = 64; host->data_shift = 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a