From patchwork Mon Mar 13 12:40:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172428 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F5F8C74A4B for ; Mon, 13 Mar 2023 12:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230097AbjCMMnB (ORCPT ); Mon, 13 Mar 2023 08:43:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230117AbjCMMmz (ORCPT ); Mon, 13 Mar 2023 08:42:55 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27C5664E8; Mon, 13 Mar 2023 05:42:20 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6OxcI020021; Mon, 13 Mar 2023 05:42:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=QJOWFJmvLNjPQ3cK/VFiHx9zeHs9QVtLszvjB+5MdRM=; b=dESX45KFJYcFjRIFl7+4CD8CZlvr8xvixUnVeUhmG57G0373NHF+9CUc/n/pczDnT1lx iHWpHp8+psFnw0HGmgehZiN67TDzUs+tbSvYCYSgZjMK4Wf7gAUUuj/wD6SLYqGljDAI uWxGjLix9YlRgTYcSJZsKoqvKx5S3SJZig/CDBNvF0yKqwqlMIEF2EzQnpd+iKmZQeE+ S0F1ac6occap9xS1RzVsp/gVLDVLGiwYDJ/Rqql0fUeXGZa6vYBS2ozGfFM1jq2JZMLK Lr9kwa0ZDhiQ9t89ce32ebFIk9dJE/rWEVUc9sbPrxqFpFH0nxpagLxeQ4g2/gQygXIj 4Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p8t1t5gex-8 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 05:42:06 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:40:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:40:55 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 903725B6921; Mon, 13 Mar 2023 05:40:51 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Vadym Kochan Subject: [PATCH v4 1/8] dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC Date: Mon, 13 Mar 2023 14:40:09 +0200 Message-ID: <20230313124016.17102-2-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: XI55rmSjiSveaP3dlq5zNOwxQhqp1rFa X-Proofpoint-ORIG-GUID: XI55rmSjiSveaP3dlq5zNOwxQhqp1rFa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Vadym Kochan AC5 SoC has armada8k PCIe IP so add compatible string for it. Signed-off-by: Vadym Kochan Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index ff25a134befa..b272fa4f08b5 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -4,7 +4,9 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. Required properties: -- compatible: "marvell,armada8k-pcie" +- compatible: Should be set to one of the following: + - "marvell,armada8k-pcie" : For A7K/8K family of SoCs + - "marvell,ac5-pcie" : For AC5 family of SoCs - reg: must contain two register regions - the control register region - the config space region From patchwork Mon Mar 13 12:40:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172425 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EE3BC7618B for ; Mon, 13 Mar 2023 12:42:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230014AbjCMMmk (ORCPT ); Mon, 13 Mar 2023 08:42:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229830AbjCMMmj (ORCPT ); Mon, 13 Mar 2023 08:42:39 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAEF36A9CF; Mon, 13 Mar 2023 05:41:59 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6Tkuu028699; Mon, 13 Mar 2023 05:41:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=qDCZ7zFyU4bHlmdw+iEtezqf0gOsQQPNRg0V800jwlo=; b=NK2ewfnrwZMqsVKt8DY3u/lk1rQ75BxJ6XhcwWA+DhtzGv5Gyh3bdsaQkdYkBskz3cAb kVUPxZhYcMIELoIp7JgvV4+avJVUD7TJGLPiuSenx7UIMJ9DMYLFZMMjCTt6h4lcy6WH /9rDve57OP66/t223g9VKX7mOQ+poOQx5rgv/V0egXC5ZUQrVO6oWOfZetXQ1owTAgIt +MY8O6wN5qf44NQkjRhNEz/2A4gz8ewCpbHmn4ge8ZA9F/u5/eMVbssfAdWDGR/L5WFz mleAZVazD8R2NPhXTXa3f4rG/ETm5AAoB7s1eKqhtBbPiImxrkBeAd6Y/0ajsOiZxa4l Yg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p8t1t5gd8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 05:41:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:01 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id DE8125B6921; Mon, 13 Mar 2023 05:40:57 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Raz Adashi Subject: [PATCH v4 2/8] PCI: armada8k: Add AC5 SoC support Date: Mon, 13 Mar 2023 14:40:10 +0200 Message-ID: <20230313124016.17102-3-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: q0EI__3OLPeUDzuN9iAYwMWub_Ug9cRv X-Proofpoint-ORIG-GUID: q0EI__3OLPeUDzuN9iAYwMWub_Ug9cRv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Raz Adashi pcie-armada8k driver is utilized to serve also AC5. Driver assumes interrupt mask registers are located in the same address inboth CPUs. This assumption is incorrect - fix it for AC5. Co-developed-by: Yuval Shaia Signed-off-by: Yuval Shaia Signed-off-by: Raz Adashi Signed-off-by: Vadym Kochan --- v2: 1) fix W1 warnings which caused by unused leftover code 2) Use one xlate function to translate ac5 dbi access. Also add mode description in comments about this translation. 3) Use correct name of Raz 4) Use matching data to pass the SoC specific params (type & ops) drivers/pci/controller/dwc/pcie-armada8k.c | 145 +++++++++++++++++---- 1 file changed, 120 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 5c999e15c357..b9fb1375dc58 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,15 +27,26 @@ #define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4 +enum armada8k_pcie_type { + ARMADA8K_PCIE_TYPE_A8K, + ARMADA8K_PCIE_TYPE_AC5 +}; + struct armada8k_pcie { struct dw_pcie *pci; struct clk *clk; struct clk *clk_reg; struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; unsigned int phy_count; + enum armada8k_pcie_type pcie_type; }; -#define PCIE_VENDOR_REGS_OFFSET 0x8000 +struct armada8k_pcie_of_data { + enum armada8k_pcie_type pcie_type; + const struct dw_pcie_ops *pcie_ops; +}; + +#define PCIE_VENDOR_REGS_OFFSET 0x8000 /* in ac5 is 0x10000 */ #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) @@ -48,10 +60,17 @@ struct armada8k_pcie { #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) +#define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) #define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_B_ASSERT_MASK BIT(10) #define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_D_ASSERT_MASK BIT(12) +#define PCIE_INT_A_ASSERT_MASK_AC5 BIT(12) +#define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) +#define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) +#define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) + +#define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) @@ -169,6 +188,7 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct armada8k_pcie *pcie = to_armada8k_pcie(pci); if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ @@ -177,32 +197,41 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } - /* Set the device to root complex mode */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); - reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_A8K) { + /* Set the device to root complex mode */ + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); + reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); - /* Set the PCIe master AxCache attributes */ - dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); - dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); + /* Set the PCIe master AxCache attributes */ + dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); - /* Set the PCIe master AxDomain attributes */ - reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); - reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); + /* Set the PCIe master AxDomain attributes */ + reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); + reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); + reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); - reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); - reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); + reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); + reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + } /* Enable INT A-D interrupts */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); - reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | - PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) { + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + reg |= PCIE_INT_A_ASSERT_MASK_AC5 | PCIE_INT_B_ASSERT_MASK_AC5 | + PCIE_INT_C_ASSERT_MASK_AC5 | PCIE_INT_D_ASSERT_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, reg); + } else { + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | + PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + } return 0; } @@ -258,9 +287,61 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, return 0; } -static const struct dw_pcie_ops dw_pcie_ops = { +static u32 ac5_xlate_dbi_reg(u32 reg) +{ + /* Handle AC5 ATU access */ + if ((reg & ~0xfffff) == PCIE_ATU_ACCESS_MASK_AC5) { + reg &= 0xfffff; + /* ATU registers offset is 0xC00 + 0x200 * n, + * from RFU registers. + */ + reg = 0xc000 | (0x200 * (reg >> 9)) | (reg & 0xff); + } else if ((reg & 0xfffff000) == PCIE_VENDOR_REGS_OFFSET) { + /* PCIe RFU registers in A8K are at offset 0x8000 from base + * (0xf2600000) while in AC5 offset is 0x10000 from base + * (0x800a0000) therefore need the addition of 0x8000. + */ + reg += PCIE_VENDOR_REGS_OFFSET; + } + + return reg; +} + +static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + u32 val; + + dw_pcie_read(base + ac5_xlate_dbi_reg(reg), size, &val); + return val; +} + +static void ac5_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + dw_pcie_write(base + ac5_xlate_dbi_reg(reg), size, val); +} + +static const struct dw_pcie_ops armada8k_dw_pcie_ops = { + .link_up = armada8k_pcie_link_up, + .start_link = armada8k_pcie_start_link, +}; + +static const struct dw_pcie_ops ac5_dw_pcie_ops = { .link_up = armada8k_pcie_link_up, .start_link = armada8k_pcie_start_link, + .read_dbi = ac5_pcie_read_dbi, + .write_dbi = ac5_pcie_write_dbi, +}; + +static const struct armada8k_pcie_of_data a8k_pcie_of_data = { + .pcie_type = ARMADA8K_PCIE_TYPE_A8K, + .pcie_ops = &armada8k_dw_pcie_ops, +}; + +static const struct armada8k_pcie_of_data ac5_pcie_of_data = { + .pcie_type = ARMADA8K_PCIE_TYPE_AC5, + .pcie_ops = &ac5_dw_pcie_ops, }; static int armada8k_pcie_probe(struct platform_device *pdev) @@ -268,9 +349,15 @@ static int armada8k_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct armada8k_pcie *pcie; struct device *dev = &pdev->dev; + const struct armada8k_pcie_of_data *data; struct resource *base; int ret; + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -279,9 +366,10 @@ static int armada8k_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + pci->ops = data->pcie_ops; pci->dev = dev; - pci->ops = &dw_pcie_ops; + pcie->pcie_type = data->pcie_type; pcie->pci = pci; pcie->clk = devm_clk_get(dev, NULL); @@ -334,7 +422,14 @@ static int armada8k_pcie_probe(struct platform_device *pdev) } static const struct of_device_id armada8k_pcie_of_match[] = { - { .compatible = "marvell,armada8k-pcie", }, + { + .compatible = "marvell,armada8k-pcie", + .data = &a8k_pcie_of_data, + }, + { + .compatible = "marvell,ac5-pcie", + .data = &ac5_pcie_of_data, + }, {}, }; From patchwork Mon Mar 13 12:40:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172427 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 209F1C6FD19 for ; Mon, 13 Mar 2023 12:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230174AbjCMMnA (ORCPT ); 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Mon, 13 Mar 2023 05:42:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:08 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 5F9725B692A; Mon, 13 Mar 2023 05:41:04 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Yuval Shaia Subject: [PATCH v4 3/8] PCI: armada8k: Add AC5 MSI support Date: Mon, 13 Mar 2023 14:40:11 +0200 Message-ID: <20230313124016.17102-4-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ssu20ViTP4SDOzJwL_cAsAz3DlZ2xhBl X-Proofpoint-ORIG-GUID: ssu20ViTP4SDOzJwL_cAsAz3DlZ2xhBl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Yuval Shaia AC5 requires different handling for MSI as with armada8k. Fix it by: 1. Enabling the relevant bits in init phase 2. Dispatch virtual IRQ handlers when MSI interrupts are received Also enable/disable PCIE_APP_LTSSM for AC5. Signed-off-by: Yuval Shaia Signed-off-by: Vadym Kochan --- v4: Fix commit subject to be aligned with previous patch in series v2: 1) fix W1 warnings which caused by unused leftover code 2) fix type in "requieres" word in the description drivers/pci/controller/dwc/pcie-armada8k.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index b9fb1375dc58..02481ecadd25 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -50,6 +50,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) +#define PCIE_APP_LTSSM_EN_AC5 BIT(24) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ @@ -69,6 +70,7 @@ struct armada8k_pcie_of_data { #define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) #define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) #define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) +#define PCIE_MSI_MASK_AC5 BIT(11) #define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) @@ -184,6 +186,16 @@ static int armada8k_pcie_start_link(struct dw_pcie *pci) return 0; } +static void ac5_pcie_msi_init(struct dw_pcie *pci) +{ + u32 val; + + /* Set MSI bit in interrupt mask */ + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + val |= PCIE_MSI_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val); +} + static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; @@ -193,7 +205,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_APP_LTSSM_EN); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) + reg &= ~(PCIE_APP_LTSSM_EN_AC5); + else + reg &= ~(PCIE_APP_LTSSM_EN); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } @@ -233,6 +248,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); } + if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + ac5_pcie_msi_init(pci); + return 0; } @@ -249,6 +267,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + dw_handle_msi_irq(&pci->pp); return IRQ_HANDLED; } From patchwork Mon Mar 13 12:40:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172435 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D34C6FD19 for ; Mon, 13 Mar 2023 12:43:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjCMMnO (ORCPT ); Mon, 13 Mar 2023 08:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230086AbjCMMm6 (ORCPT ); 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Mon, 13 Mar 2023 05:42:14 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:14 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 8459A5B6921; Mon, 13 Mar 2023 05:41:10 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Elad Nachman Subject: [PATCH v4 4/8] dt-bindings: PCI: dwc: Add dma-ranges, region mask Date: Mon, 13 Mar 2023 14:40:12 +0200 Message-ID: <20230313124016.17102-5-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: eCJZqwhSSm_hjhuKhOV91Q5XDz7EC0Vg X-Proofpoint-ORIG-GUID: eCJZqwhSSm_hjhuKhOV91Q5XDz7EC0Vg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Elad Nachman Add properties to support configurable DMA mask bits and region mask bits: 1. configurable dma-ranges is needed for Marvell AC5/AC5X SOCs which have their physical DDR memory start at address 0x2_0000_0000. 2. Configurable region mask bits is needed for the Marvell Armada 7020/7040/8040 SOCs when the DT file places the PCIe window above the 4GB region. The Synopsis Designware PCIe IP in these SOCs is too old to specify the highest memory location supported by the PCIe, but practically supports such locations. Allow these locations to be specified in the DT file. Signed-off-by: Elad Nachman --- v4: 1) Fix commit message and its formatting 2) Replace num-dmamask with dma-ranges .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 5 +++++ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index d87e13496834..3cb9af1aefeb 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -261,6 +261,11 @@ properties: dma-coherent: true + num-regionmask: + description: | + number of region limit mask bits to use, if different than default 32 + maximum: 64 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 1a83f0f65f19..ed7ae2a14804 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -197,6 +197,12 @@ properties: - contains: const: msi + dma-ranges: + description: + Defines the DMA mask for devices which due to non-standard HW address + assignment have their RAM starting address above the lower 32-bit region. + Since this is a mask, only the size attribute of the dma-ranges is used. + additionalProperties: true required: From patchwork Mon Mar 13 12:40:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172436 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82594C6FD1C for ; Mon, 13 Mar 2023 12:43:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230259AbjCMMnQ (ORCPT ); Mon, 13 Mar 2023 08:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230104AbjCMMm6 (ORCPT ); Mon, 13 Mar 2023 08:42:58 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E738965044; Mon, 13 Mar 2023 05:42:24 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6OxcO020021; Mon, 13 Mar 2023 05:42:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=QTMWXURCDJiR7mSr9wa/ZQQCka4cqYJIXxmGkMAjPKk=; b=kZiAJWRLUv7G48l4ZJvqZ6H74E5Befu1MXGgUImvfaaHqNHs5N3BayUlZ2Cf43vJhUFG xOt0A5RdrMSu1Cw8z5ktmLooE3RxN6nhvA/OUM/E5cExbQTuQGH1kQCgH2jkMJdbRofM yv3YpBWZEmMiU56GZxpw4ePN5ZWu8QZm/plzZjQlPJ2cDCbWoqyll6kGPQNG6x4pfLNB w6ywGDrm792W1T252CyX9APORp9tpOxq9HNDBKyQJ/1+VROMwEsx2+y+6aunBz6W/3TB 8Oc3YKmEx68xbIlQMOMKs6q/PdhWCL7XW6FICc4ywWJvJgMfgNWs6YmK4P9ApGZdh3Pz 7g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p8t1t5gex-19 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 05:42:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:20 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 53E565B693D; Mon, 13 Mar 2023 05:41:15 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Elad Nachman Subject: [PATCH v4 5/8] PCI: armada8k: support AC5 INTx PCIe interrupts Date: Mon, 13 Mar 2023 14:40:13 +0200 Message-ID: <20230313124016.17102-6-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: JCyOKQzn5cf_Ucap8mVfSpT9mLIwwHHi X-Proofpoint-ORIG-GUID: JCyOKQzn5cf_Ucap8mVfSpT9mLIwwHHi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Elad Nachman Support message emulation of INTx PCIe interrupts for Marvell AC5/X. These message emulations require writing an additional status register with acknowledge bits. Signed-off-by: Elad Nachman --- v4: Split the part not handling INTx interrupts to a separate patch drivers/pci/controller/dwc/pcie-armada8k.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 02481ecadd25..2b94e32853ad 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -61,6 +61,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) +#define PCIE_GLOBAL_INT_CAUSE2_REG (PCIE_VENDOR_REGS_OFFSET + 0x24) #define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) #define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_B_ASSERT_MASK BIT(10) @@ -267,8 +268,14 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); - if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) - dw_handle_msi_irq(&pci->pp); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) { + if (PCIE_MSI_MASK_AC5 & val) + dw_handle_msi_irq(&pci->pp); + + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG); + /* Now clear the second interrupt cause. */ + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG, val); + } return IRQ_HANDLED; } From patchwork Mon Mar 13 12:40:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172437 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42938C7618D for ; Mon, 13 Mar 2023 12:43:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbjCMMnQ (ORCPT ); Mon, 13 Mar 2023 08:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230140AbjCMMm6 (ORCPT ); Mon, 13 Mar 2023 08:42:58 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11DF267824; Mon, 13 Mar 2023 05:42:25 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6OxcP020021; Mon, 13 Mar 2023 05:42:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=7DKfIo9JLAYpRKRTLSaaANvz0M1ibKDER5y1y9Rke+A=; b=kSLrJR17BZ/AdYbZrQCJVWrdkXS5u3hbqm+RLcXs3NXP3mmmWSSeQ2v7SKbBdedLtWLr Vo4qLU3kByYxhEFV2ILU3k4TkUu8FMwme9FrgHldbJboGyyVS12cV+Tszu00TS92rofb jMAommBcTKIzo/n9InELHXz6j0V5eSYRw+q9TeJZqPptUdeP0DYGR60CZE44viHOMcj0 wxsFLw8ELmZPk6oUdMRk1XF1Mw3XDUewRZvJPXu7H8KDEvqhlcfuX0mIXZfVR0od5sCg gAdZTH8HFMvt6d7vE9derhgcpXhKc7oz3Nw+wyJAAWIduCIu6EtWFYT9fXAo88C2xkok Aw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p8t1t5gex-20 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 05:42:17 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:22 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 2C5325B6921; Mon, 13 Mar 2023 05:41:18 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Elad Nachman Subject: [PATCH v4 6/8] PCI: armada8k: support reg regions according to DT. Date: Mon, 13 Mar 2023 14:40:14 +0200 Message-ID: <20230313124016.17102-7-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: R8-l_f3q1QTZAIqYGGMZ9XTliljdjdj1 X-Proofpoint-ORIG-GUID: R8-l_f3q1QTZAIqYGGMZ9XTliljdjdj1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Elad Nachman Support atu/vendor registers regions start according to DT rather than using inflexible offset arithmetics. Signed-off-by: Elad Nachman --- v4: Split from previous patch in series drivers/pci/controller/dwc/pcie-armada8k.c | 30 ++++++++++++++-------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 2b94e32853ad..145434c7a9fb 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -46,7 +46,7 @@ struct armada8k_pcie_of_data { const struct dw_pcie_ops *pcie_ops; }; -#define PCIE_VENDOR_REGS_OFFSET 0x8000 /* in ac5 is 0x10000 */ +#define PCIE_VENDOR_REGS_OFFSET 0x8000 /* in ac5 is in another region */ #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) @@ -314,24 +314,29 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, return 0; } -static u32 ac5_xlate_dbi_reg(u32 reg) +static void __iomem *ac5_xlate_dbi_reg(struct dw_pcie *pci, + void __iomem *base, + u32 reg) { /* Handle AC5 ATU access */ if ((reg & ~0xfffff) == PCIE_ATU_ACCESS_MASK_AC5) { reg &= 0xfffff; - /* ATU registers offset is 0xC00 + 0x200 * n, + /* ATU registers offset is 0xC000 + 0x200 * n, * from RFU registers. */ - reg = 0xc000 | (0x200 * (reg >> 9)) | (reg & 0xff); + reg = (0x200 * (reg >> 9)) | (reg & 0xff); + return pci->atu_base + reg; } else if ((reg & 0xfffff000) == PCIE_VENDOR_REGS_OFFSET) { /* PCIe RFU registers in A8K are at offset 0x8000 from base * (0xf2600000) while in AC5 offset is 0x10000 from base - * (0x800a0000) therefore need the addition of 0x8000. + * (0x800a0000) therefore need to be reduced by 0x8000 + * and rebased from dbi2 base, which is set to the PCIe rfu + * base in the AC5 dts: */ - reg += PCIE_VENDOR_REGS_OFFSET; + reg -= PCIE_VENDOR_REGS_OFFSET; + return pci->dbi_base2 + reg; } - - return reg; + return base + reg; } static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -339,14 +344,14 @@ static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, { u32 val; - dw_pcie_read(base + ac5_xlate_dbi_reg(reg), size, &val); + dw_pcie_read(ac5_xlate_dbi_reg(pci, base, reg), size, &val); return val; } static void ac5_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) { - dw_pcie_write(base + ac5_xlate_dbi_reg(reg), size, val); + dw_pcie_write(ac5_xlate_dbi_reg(pci, base, reg), size, val); } static const struct dw_pcie_ops armada8k_dw_pcie_ops = { @@ -425,7 +430,6 @@ static int armada8k_pcie_probe(struct platform_device *pdev) ret = PTR_ERR(pci->dbi_base); goto fail_clkreg; } - ret = armada8k_pcie_setup_phys(pcie); if (ret) goto fail_clkreg; @@ -436,6 +440,10 @@ static int armada8k_pcie_probe(struct platform_device *pdev) if (ret) goto disable_phy; + /* backwards compatibility with older dts files: */ + if (!pci->dbi_base2) + pci->dbi_base2 = pci->dbi_base; + return 0; disable_phy: From patchwork Mon Mar 13 12:40:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172424 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C622C6FD1C for ; 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Mon, 13 Mar 2023 05:41:48 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:26 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 39AA65B6921; Mon, 13 Mar 2023 05:41:23 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Elad Nachman Subject: [PATCH v4 7/8] PCI: dwc: Introduce configurable DMA mask Date: Mon, 13 Mar 2023 14:40:15 +0200 Message-ID: <20230313124016.17102-8-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: dHocvyUF3pegmSJR2gewwdMD3dcDt488 X-Proofpoint-ORIG-GUID: dHocvyUF3pegmSJR2gewwdMD3dcDt488 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Elad Nachman Some devices, such as AC5 and AC5X have their physical DDR memory start at address 0x2_0000_0000. In order to have the DMA coherent allocation succeed later, a different DMA mask is required, as defined in the DT file for such SOCs, using dma-ranges. If not defined, fallback to 32-bit as previously done in the code. Signed-off-by: Elad Nachman --- v4: 1) Fix commit message formatting. 2) Fix removal / addition of blank lines. .../pci/controller/dwc/pcie-designware-host.c | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9952057c8819..74393e59e7a7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -325,10 +325,14 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; + struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); u64 *msi_vaddr; int ret; u32 ctrl, num_ctrls; + u32 num_dma_maskbits = 32; + struct of_pci_range range; + struct of_pci_range_parser parser; for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; @@ -367,18 +371,36 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) } /* + * Some devices, such as AC5 and AC5X have their physical DDR memory + * start at address 0x2_0000_0000 . In order to have the DMA + * coherent allocation succeed later, a different DMA mask is + * required, as defined in the DT file for such SOCs using dma-ranges. + * If not defined, fallback to 32-bit as described below: + * * Even though the iMSI-RX Module supports 64-bit addresses some * peripheral PCIe devices may lack 64-bit message support. In * order not to miss MSI TLPs from those devices the MSI target * address has to be within the lowest 4GB. * - * Note until there is a better alternative found the reservation is + * Note until there is a better alternative found, the reservation is * done by allocating from the artificially limited DMA-coherent * memory. */ - ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + ret = of_pci_dma_range_parser_init(&parser, np); + if (!ret) { + if (of_pci_range_parser_one(&parser, &range)) { + if (range.size > BIT_MASK(32) ) { + num_dma_maskbits = fls64(range.size); + dev_info(dev, "Overriding DMA mask to %u bits...\n", num_dma_maskbits); + } + } + } + + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(num_dma_maskbits)); if (ret) - dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + dev_warn(dev, + "Failed to set DMA mask to %u-bit. Devices with only 32-bit MSI support may not work properly\n", + num_dma_maskbits); msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, GFP_KERNEL); From patchwork Mon Mar 13 12:40:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13172438 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F168CC61DA4 for ; Mon, 13 Mar 2023 12:43:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230316AbjCMMnS (ORCPT ); Mon, 13 Mar 2023 08:43:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbjCMMm7 (ORCPT ); Mon, 13 Mar 2023 08:42:59 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB446A1EC; Mon, 13 Mar 2023 05:42:27 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6OxcQ020021; Mon, 13 Mar 2023 05:42:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=+Twwfo+d1JCCV20Ow3YeKxKYdEAuXIvfbVrrAMuP3yA=; b=guNHMHlyOa/7znmSrleiZRsrgbsvOWq0cOkeJh0umWESO1IqHPan62SO5JZ2XmM97+OR 0x6v22rD/fNfDOMMmNu8eY4MEoVkv5QMJ48R5mtas/wLyJEK00ICbSKkk4SfNkGwwObE t+Jr4NCBKO74/1TmbvT6YJ549huXcJwVSoirSQEMW/uD6Koav30EsrjJNKaPRryRrtcV IjMIqETRoTzOKFrMmMwrKxf92OkN46wWc9Y07z2lqcisxdYJfp6YeOA53ZqFRUvKvw12 S6EWaBxG1yt1/XXhrFcEiVP7LGAxUE0yjtu4J8nfCWGazwDpLsoyglXKuZlMOiHK6ojl pA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p8t1t5gjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 05:42:19 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 05:41:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 13 Mar 2023 05:41:30 -0700 Received: from jupiter073.il.marvell.com (unknown [10.5.116.85]) by maili.marvell.com (Postfix) with ESMTP id 07CCF5B6921; Mon, 13 Mar 2023 05:41:26 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , CC: Elad Nachman Subject: [PATCH v4 8/8] PCI: dwc: Introduce region limit from DT Date: Mon, 13 Mar 2023 14:40:16 +0200 Message-ID: <20230313124016.17102-9-enachman@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230313124016.17102-1-enachman@marvell.com> References: <20230313124016.17102-1-enachman@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 9Xb2KkvInWYrasdOqz5A3CBQUIxGT5aI X-Proofpoint-ORIG-GUID: 9Xb2KkvInWYrasdOqz5A3CBQUIxGT5aI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_05,2023-03-13_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Elad Nachman Allow dts override of region limit for SOCs with older Synopsis Designware PCIe IP but with greater than 32-bit address range support, such as the Armada 7020/7040/8040 family of SOCs by Marvell, when the DT file places the PCIe window above the 4GB region. The Synopsis Designware PCIe IP in these SOCs is too old to specify the highest memory location supported by the PCIe, but practically supports such locations. Allow these locations to be specified in the DT file. DT property is called num-regionmask , and can range between 33 and 64. Signed-off-by: Elad Nachman --- v4: 1) Fix blank lines removal / addition 2) Remove usage of variable with same name as dt binding property drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 53a16b8b6ac2..9773c110c733 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -735,8 +735,10 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) void dw_pcie_iatu_detect(struct dw_pcie *pci) { int max_region, ob, ib; - u32 val, min, dir; + u32 val, min, dir, ret; u64 max; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); if (val == 0xFFFFFFFF) { @@ -781,7 +783,13 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); } else { - max = 0; + /* Allow dts override of region limit for older IP with above 32-bit support: */ + ret = of_property_read_u32(np, "num-regionmask", &val); + if (!ret && val > 32) { + max = GENMASK(val - 33, 0); + dev_info(pci->dev, "Overriding region limit to %u bits\n", val); + } else + max = 0; } pci->num_ob_windows = ob;