From patchwork Wed Mar 15 11:07:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE58DC61DA4 for ; Wed, 15 Mar 2023 11:20:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231895AbjCOLUl (ORCPT ); Wed, 15 Mar 2023 07:20:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231792AbjCOLUR (ORCPT ); Wed, 15 Mar 2023 07:20:17 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C716379B31 for ; Wed, 15 Mar 2023 04:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678879089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RepI+IfyFptg6gJlYsDZJr2PdqAcoibwPIbHUAcBm+g=; b=D3DBvsZbk5gvxXazEXqazAKCN1E8TYmXGGotVHHJJiw0gzwwdG5IWlM9dfZxnAznwUW7NR fshVr1O86Bc9FZ9Tfj3Y5A07dGK9D+VJAr8TPMOefWM+UeyPEzzpIVrB2Ve7/TZVIc6i0R NAHPpGlz5qaw1zP1dJJO2xWvDZqFo38= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-465-C6BFShxuPDGi8KaWyKruIQ-1; Wed, 15 Mar 2023 07:07:36 -0400 X-MC-Unique: C6BFShxuPDGi8KaWyKruIQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 34954382C96D; Wed, 15 Mar 2023 11:07:36 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id 409D82027042; Wed, 15 Mar 2023 11:07:34 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 1/6] arm: pmu: pmu-chain-promotion: Improve debug messages Date: Wed, 15 Mar 2023 12:07:20 +0100 Message-Id: <20230315110725.1215523-2-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The pmu-chain-promotion test is composed of several subtests. In case of failures, the current logs are really dificult to analyze since they look very similar and sometimes duplicated for each subtest. Add prefixes for each subtest and introduce a macro that prints the registers we are mostly interested in, namerly the 2 first counters and the overflow counter. Signed-off-by: Eric Auger Reviewed-by: Alexandru Elisei --- arm/pmu.c | 63 ++++++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index f6e95012..dad7d4b4 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -715,6 +715,11 @@ static void test_chained_sw_incr(bool unused) report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0), read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); } +#define PRINT_REGS(__s) \ + report_info("%s #1=0x%lx #0=0x%lx overflow=0x%lx", __s, \ + read_regn_el0(pmevcntr, 1), \ + read_regn_el0(pmevcntr, 0), \ + read_sysreg(pmovsclr_el0)) static void test_chain_promotion(bool unused) { @@ -725,6 +730,7 @@ static void test_chain_promotion(bool unused) return; /* Only enable CHAIN counter */ + report_prefix_push("subtest1"); pmu_reset(); write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); @@ -732,83 +738,81 @@ static void test_chain_promotion(bool unused) isb(); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + PRINT_REGS("post"); report(!read_regn_el0(pmevcntr, 0), "chain counter not counting if even counter is disabled"); + report_prefix_pop(); /* Only enable even counter */ + report_prefix_push("subtest2"); pmu_reset(); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); write_sysreg_s(0x1, PMCNTENSET_EL0); isb(); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + PRINT_REGS("post"); report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), "odd counter did not increment on overflow if disabled"); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); - report_info("CHAIN counter #1 has value 0x%lx", - read_regn_el0(pmevcntr, 1)); - report_info("overflow counter 0x%lx", read_sysreg(pmovsclr_el0)); + report_prefix_pop(); /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ + report_prefix_push("subtest3"); pmu_reset(); write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); isb(); + PRINT_REGS("init"); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + PRINT_REGS("After 1st loop"); /* disable the CHAIN event */ write_sysreg_s(0x2, PMCNTENCLR_EL0); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + PRINT_REGS("After 2d loop"); report(read_sysreg(pmovsclr_el0) == 0x1, "should have triggered an overflow on #0"); report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 shouldn't have incremented"); + report_prefix_pop(); /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ + report_prefix_push("subtest4"); pmu_reset(); write_sysreg_s(0x1, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); isb(); - report_info("counter #0 = 0x%lx, counter #1 = 0x%lx overflow=0x%lx", - read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), - read_sysreg(pmovsclr_el0)); + PRINT_REGS("init"); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + PRINT_REGS("After 1st loop"); /* enable the CHAIN event */ write_sysreg_s(0x3, PMCNTENSET_EL0); isb(); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + + PRINT_REGS("After 2d loop"); report((read_regn_el0(pmevcntr, 1) == 1) && (read_sysreg(pmovsclr_el0) == 0x1), "CHAIN counter enabled: CHAIN counter was incremented and overflow"); - - report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", - read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + report_prefix_pop(); /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ + report_prefix_push("subtest5"); pmu_reset(); write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); isb(); + PRINT_REGS("init"); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + PRINT_REGS("After 1st loop"); /* 0 becomes CHAINED */ write_sysreg_s(0x0, PMCNTENSET_EL0); @@ -817,37 +821,34 @@ static void test_chain_promotion(bool unused) write_regn_el0(pmevcntr, 1, 0x0); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("MEM_ACCESS counter #0 has value 0x%lx", - read_regn_el0(pmevcntr, 0)); + PRINT_REGS("After 2d loop"); report((read_regn_el0(pmevcntr, 1) == 1) && (read_sysreg(pmovsclr_el0) == 0x1), "32b->64b: CHAIN counter incremented and overflow"); - - report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", - read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + report_prefix_pop(); /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ + report_prefix_push("subtest6"); pmu_reset(); write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); write_sysreg_s(0x3, PMCNTENSET_EL0); + PRINT_REGS("init"); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); - report_info("counter #0=0x%lx, counter #1=0x%lx", - read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); + PRINT_REGS("After 1st loop"); write_sysreg_s(0x0, PMCNTENSET_EL0); write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); write_sysreg_s(0x3, PMCNTENSET_EL0); mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + PRINT_REGS("After 2d loop"); report(read_sysreg(pmovsclr_el0) == 1, "overflow is expected on counter 0"); - report_info("counter #0=0x%lx, counter #1=0x%lx overflow=0x%lx", - read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), - read_sysreg(pmovsclr_el0)); + report_prefix_pop(); } static bool expect_interrupts(uint32_t bitmap) From patchwork Wed Mar 15 11:07:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3E89C7618A for ; Wed, 15 Mar 2023 11:20:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232086AbjCOLUo (ORCPT ); Wed, 15 Mar 2023 07:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231855AbjCOLUT (ORCPT ); Wed, 15 Mar 2023 07:20:19 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6C408536A for ; Wed, 15 Mar 2023 04:18:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678879089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LUg/lA5dPqAuc9OguXJG4Q0LnI5RxBl9sSCbOrZlfsk=; b=RaGgaYXTQiypJFllf0gLmUpiggLIf1k+Wc9Zu6kVTXqhm0C3gxhj1kdLVDw+wEns4bIyOZ oTqf0tV7UU2UcHoJ6+Ngphq/9MKR4eyPE8wo1NFRSgCurKzf0QmgBH4q/lo1HM+ccSNImp 1BzPSSEbKL+yGN/oqQF6uGYn3X0Lk5s= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-594-OiJABwaJMy2BixKYmqf4mg-1; Wed, 15 Mar 2023 07:07:39 -0400 X-MC-Unique: OiJABwaJMy2BixKYmqf4mg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 90B0F185A792; Wed, 15 Mar 2023 11:07:38 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id 84B44202701F; Wed, 15 Mar 2023 11:07:36 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 2/6] arm: pmu: pmu-chain-promotion: Introduce defines for count and margin values Date: Wed, 15 Mar 2023 12:07:21 +0100 Message-Id: <20230315110725.1215523-3-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The pmu-chain-promotion test is composed of separate subtests. Some of them apply some settings on a first MEM_ACCESS loop iterations, change the settings and run another MEM_ACCESS loop. The PRE_OVERFLOW2 MEM_ACCESS counter init value is defined so that the first loop does not overflow and the second loop overflows. At the moment the MEM_ACCESS count number is hardcoded to 20 and PRE_OVERFLOW2 is set to UINT32_MAX - 20 - 15 where 15 acts as a margin. Introduce defines for the count number and the margin so that it becomes easier to change them. Signed-off-by: Eric Auger Reviewed-by: Alexandru Elisei --- arm/pmu.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index dad7d4b4..b88366a8 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -55,11 +55,18 @@ #define EXT_COMMON_EVENTS_LOW 0x4000 #define EXT_COMMON_EVENTS_HIGH 0x403F -#define ALL_SET_32 0x00000000FFFFFFFFULL +#define ALL_SET_32 0x00000000FFFFFFFFULL #define ALL_CLEAR 0x0000000000000000ULL #define PRE_OVERFLOW_32 0x00000000FFFFFFF0ULL -#define PRE_OVERFLOW2_32 0x00000000FFFFFFDCULL #define PRE_OVERFLOW_64 0xFFFFFFFFFFFFFFF0ULL +#define COUNT 20 +#define MARGIN 15 +/* + * PRE_OVERFLOW2 is set so that 1st COUNT iterations do not + * produce 32b overflow and 2d COUNT iterations do. To accommodate + * for some observed variability we take into account a given @MARGIN + */ +#define PRE_OVERFLOW2_32 (ALL_SET_32 - COUNT - MARGIN) #define PRE_OVERFLOW(__overflow_at_64bits) \ (__overflow_at_64bits ? PRE_OVERFLOW_64 : PRE_OVERFLOW_32) @@ -737,7 +744,7 @@ static void test_chain_promotion(bool unused) write_sysreg_s(0x2, PMCNTENSET_EL0); isb(); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("post"); report(!read_regn_el0(pmevcntr, 0), "chain counter not counting if even counter is disabled"); @@ -750,13 +757,13 @@ static void test_chain_promotion(bool unused) write_sysreg_s(0x1, PMCNTENSET_EL0); isb(); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("post"); report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), "odd counter did not increment on overflow if disabled"); report_prefix_pop(); - /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ + /* 1st COUNT with CHAIN enabled, next COUNT with CHAIN disabled */ report_prefix_push("subtest3"); pmu_reset(); write_sysreg_s(0x3, PMCNTENSET_EL0); @@ -764,12 +771,12 @@ static void test_chain_promotion(bool unused) isb(); PRINT_REGS("init"); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); /* disable the CHAIN event */ write_sysreg_s(0x2, PMCNTENCLR_EL0); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); report(read_sysreg(pmovsclr_el0) == 0x1, "should have triggered an overflow on #0"); @@ -777,7 +784,7 @@ static void test_chain_promotion(bool unused) "CHAIN counter #1 shouldn't have incremented"); report_prefix_pop(); - /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ + /* 1st COUNT with CHAIN disabled, next COUNT with CHAIN enabled */ report_prefix_push("subtest4"); pmu_reset(); @@ -786,13 +793,13 @@ static void test_chain_promotion(bool unused) isb(); PRINT_REGS("init"); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); /* enable the CHAIN event */ write_sysreg_s(0x3, PMCNTENSET_EL0); isb(); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); @@ -811,7 +818,7 @@ static void test_chain_promotion(bool unused) isb(); PRINT_REGS("init"); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); /* 0 becomes CHAINED */ @@ -820,7 +827,7 @@ static void test_chain_promotion(bool unused) write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 1, 0x0); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); report((read_regn_el0(pmevcntr, 1) == 1) && @@ -837,14 +844,14 @@ static void test_chain_promotion(bool unused) write_sysreg_s(0x3, PMCNTENSET_EL0); PRINT_REGS("init"); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); write_sysreg_s(0x0, PMCNTENSET_EL0); write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); write_sysreg_s(0x3, PMCNTENSET_EL0); - mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); report(read_sysreg(pmovsclr_el0) == 1, "overflow is expected on counter 0"); From patchwork Wed Mar 15 11:07:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D07C9C61DA4 for ; Wed, 15 Mar 2023 11:20:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231781AbjCOLUg (ORCPT ); Wed, 15 Mar 2023 07:20:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231769AbjCOLUQ (ORCPT ); Wed, 15 Mar 2023 07:20:16 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8471B76F41 for ; Wed, 15 Mar 2023 04:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678879089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dKufXWfDgT0CA64z31FmWiaMc4lke7nLK+zVzTewluo=; b=NfDH9aPDFjt50HxJrH/m15+JtnUP8Vj8YH3zkof+aAdaJgstk+XkWHlEMMfcX4wnlLhIlt BNeed5bMHWwSxfr35eAOmYUB9Ly55ulmfvVGKhzf3WRlNz+hQGEFOrB8Fp+XbHuWimHYUu uTudTUrT/7LbBOnKurpQk6zfrmWZrF4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-124-wDi_qgVLOLa2kntmHkztqA-1; Wed, 15 Mar 2023 07:07:41 -0400 X-MC-Unique: wDi_qgVLOLa2kntmHkztqA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id D156A185A78B; Wed, 15 Mar 2023 11:07:40 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id D66272027040; Wed, 15 Mar 2023 11:07:38 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 3/6] arm: pmu: Add extra DSB barriers in the mem_access loop Date: Wed, 15 Mar 2023 12:07:22 +0100 Message-Id: <20230315110725.1215523-4-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The mem access loop currently features ISB barriers only. However the mem_access loop counts the number of accesses to memory. ISB do not garantee the PE cannot reorder memory access. Let's add a DSB ISH before the write to PMCR_EL0 that enables the PMU and after the last iteration, before disabling the PMU. Signed-off-by: Eric Auger Suggested-by: Alexandru Elisei --- This was discussed in https://lore.kernel.org/all/YzxmHpV2rpfaUdWi@monolith.localdoman/ --- arm/pmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index b88366a8..dde399e2 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -301,6 +301,7 @@ static void mem_access_loop(void *addr, long loop, uint32_t pmcr) { uint64_t pmcr64 = pmcr; asm volatile( + " dsb ish\n" " msr pmcr_el0, %[pmcr]\n" " isb\n" " mov x10, %[loop]\n" @@ -308,6 +309,7 @@ asm volatile( " ldr x9, [%[addr]]\n" " cmp x10, #0x0\n" " b.gt 1b\n" + " dsb ish\n" " msr pmcr_el0, xzr\n" " isb\n" : From patchwork Wed Mar 15 11:07:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0FA8C6FD1D for ; Wed, 15 Mar 2023 11:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232096AbjCOLMd (ORCPT ); Wed, 15 Mar 2023 07:12:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232093AbjCOLMG (ORCPT ); Wed, 15 Mar 2023 07:12:06 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96C508C81F for ; Wed, 15 Mar 2023 04:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678878467; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=W9JfBxT/tFVlJGKUlXgy73iHpcMp3LqRtX3+KfMtIMo=; b=HMeSWSj4GmpbrAy/QG/29UCxdmPmYX7zAGlfu1ddUl6sGygu/zPwFaHNvTTqLadVn3ptwJ nMcoG69L2D+bYcVN0A4880iKS3ZaSyUSTHlaSBP5WgGS7ikSpAYcwlRB+8kzNOiOX1KlEB NTt/AfWz4J8DtRpf69JmLC1nzUaSgqI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-515-wRurrxHSMIOjhDTIHdKwkQ-1; Wed, 15 Mar 2023 07:07:44 -0400 X-MC-Unique: wRurrxHSMIOjhDTIHdKwkQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 326D78028B3; Wed, 15 Mar 2023 11:07:43 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id 25386202701F; Wed, 15 Mar 2023 11:07:41 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 4/6] arm: pmu: Fix chain counter enable/disable sequences Date: Wed, 15 Mar 2023 12:07:23 +0100 Message-Id: <20230315110725.1215523-5-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In some ARM ARM ddi0487 revisions it is said that disabling/enabling a pair of counters that are paired by a CHAIN event should follow a given sequence: Disable the low counter first, isb, disable the high counter Enable the high counter first, isb, enable low counter This was the case in Fc. However this is not written anymore in Ia revision. Introduce 2 helpers to execute those sequences and replace the existing PMCNTENCLR/ENSET calls. Also fix 2 write_sysreg_s(0x0, PMCNTENSET_EL0) in subtest 5 & 6 and replace them by PMCNTENCLR writes since writing 0 in PMCNTENSET_EL0 has no effect. Signed-off-by: Eric Auger --- arm/pmu.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index dde399e2..af679667 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -730,6 +730,22 @@ static void test_chained_sw_incr(bool unused) read_regn_el0(pmevcntr, 0), \ read_sysreg(pmovsclr_el0)) +static void enable_chain_counter(int even) +{ + write_sysreg_s(BIT(even), PMCNTENSET_EL0); /* Enable the high counter first */ + isb(); + write_sysreg_s(BIT(even + 1), PMCNTENSET_EL0); /* Enable the low counter */ + isb(); +} + +static void disable_chain_counter(int even) +{ + write_sysreg_s(BIT(even + 1), PMCNTENCLR_EL0); /* Disable the low counter first*/ + isb(); + write_sysreg_s(BIT(even), PMCNTENCLR_EL0); /* Disable the high counter */ + isb(); +} + static void test_chain_promotion(bool unused) { uint32_t events[] = {MEM_ACCESS, CHAIN}; @@ -768,16 +784,17 @@ static void test_chain_promotion(bool unused) /* 1st COUNT with CHAIN enabled, next COUNT with CHAIN disabled */ report_prefix_push("subtest3"); pmu_reset(); - write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); - isb(); + enable_chain_counter(0); PRINT_REGS("init"); mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); /* disable the CHAIN event */ - write_sysreg_s(0x2, PMCNTENCLR_EL0); + disable_chain_counter(0); + write_sysreg_s(0x1, PMCNTENSET_EL0); /* Enable the low counter */ + isb(); mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); report(read_sysreg(pmovsclr_el0) == 0x1, @@ -798,9 +815,11 @@ static void test_chain_promotion(bool unused) mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); - /* enable the CHAIN event */ - write_sysreg_s(0x3, PMCNTENSET_EL0); + /* Disable the even counter and enable the chain counter */ + write_sysreg_s(0x1, PMCNTENCLR_EL0); /* Disable the low counter first */ isb(); + enable_chain_counter(0); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); @@ -824,10 +843,10 @@ static void test_chain_promotion(bool unused) PRINT_REGS("After 1st loop"); /* 0 becomes CHAINED */ - write_sysreg_s(0x0, PMCNTENSET_EL0); + write_sysreg_s(0x3, PMCNTENCLR_EL0); write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); - write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 1, 0x0); + enable_chain_counter(0); mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 2d loop"); @@ -843,13 +862,13 @@ static void test_chain_promotion(bool unused) write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); - write_sysreg_s(0x3, PMCNTENSET_EL0); + enable_chain_counter(0); PRINT_REGS("init"); mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); PRINT_REGS("After 1st loop"); - write_sysreg_s(0x0, PMCNTENSET_EL0); + disable_chain_counter(0); write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); write_sysreg_s(0x3, PMCNTENSET_EL0); From patchwork Wed Mar 15 11:07:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC2AC61DA4 for ; Wed, 15 Mar 2023 11:18:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232038AbjCOLSI (ORCPT ); Wed, 15 Mar 2023 07:18:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231933AbjCOLRi (ORCPT ); Wed, 15 Mar 2023 07:17:38 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33A681515D for ; Wed, 15 Mar 2023 04:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678878861; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kuHE2AeRI9e/mGOy+BIcsuR8/WqXmEdwe7t+2hC5Uig=; b=DOuD8WajrtdhyTW582LPvJ+63uCsztc/nXSW8AJ7jcojP0UwTKi2XS8BtIkVmv42G1DpRt oACdN/a9rPYywKC88mWavdqZ0KXLUHQfL3lIX98cPuOTjn6A8W2mooGo0HItF60Hnizimw hB3WgFIZpjGP0Ud19lPdukGXWwx1zQs= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-672-17xLadpmMaa72CvrG-fNwg-1; Wed, 15 Mar 2023 07:07:46 -0400 X-MC-Unique: 17xLadpmMaa72CvrG-fNwg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 72C86382C967; Wed, 15 Mar 2023 11:07:45 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id 79680202701E; Wed, 15 Mar 2023 11:07:43 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 5/6] arm: pmu: Add pmu-memaccess-reliability test Date: Wed, 15 Mar 2023 12:07:24 +0100 Message-Id: <20230315110725.1215523-6-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a new basic test that runs MEM_ACCESS loop over 100 iterations and make sure the number of measured MEM_ACCESS never overflows the margin. Some other pmu tests rely on this pattern and if the MEM_ACCESS measurement is not reliable, it is better to report it beforehand and not confuse the user any further. Without the subsequent patch, this typically fails on ThunderXv2 with the following logs: INFO: pmu: pmu-memaccess-reliability: 32-bit overflows: overflow=1 min=21 max=41 COUNT=20 MARGIN=15 FAIL: pmu: pmu-memaccess-reliability: 32-bit overflows: memaccess is reliable Signed-off-by: Eric Auger --- arm/pmu.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++++++ 2 files changed, 58 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index af679667..c3d2a428 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -56,6 +56,7 @@ #define EXT_COMMON_EVENTS_HIGH 0x403F #define ALL_SET_32 0x00000000FFFFFFFFULL +#define ALL_SET_64 0xFFFFFFFFFFFFFFFFULL #define ALL_CLEAR 0x0000000000000000ULL #define PRE_OVERFLOW_32 0x00000000FFFFFFF0ULL #define PRE_OVERFLOW_64 0xFFFFFFFFFFFFFFF0ULL @@ -67,6 +68,10 @@ * for some observed variability we take into account a given @MARGIN */ #define PRE_OVERFLOW2_32 (ALL_SET_32 - COUNT - MARGIN) +#define PRE_OVERFLOW2_64 (ALL_SET_64 - COUNT - MARGIN) + +#define PRE_OVERFLOW2(__overflow_at_64bits) \ + (__overflow_at_64bits ? PRE_OVERFLOW2_64 : PRE_OVERFLOW2_32) #define PRE_OVERFLOW(__overflow_at_64bits) \ (__overflow_at_64bits ? PRE_OVERFLOW_64 : PRE_OVERFLOW_32) @@ -746,6 +751,50 @@ static void disable_chain_counter(int even) isb(); } +static void test_memaccess_reliability(bool overflow_at_64bits) +{ + uint32_t events[] = {MEM_ACCESS}; + void *addr = malloc(PAGE_SIZE); + uint64_t count, max = 0, min = pmevcntr_mask(); + uint64_t pre_overflow2 = PRE_OVERFLOW2(overflow_at_64bits); + uint64_t pmcr_lp = overflow_at_64bits ? PMU_PMCR_LP : 0; + bool overflow = false; + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events)) || + !check_overflow_prerequisites(overflow_at_64bits)) + return; + + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + for (int i = 0; i < 100; i++) { + pmu_reset(); + write_regn_el0(pmevcntr, 0, pre_overflow2); + write_sysreg_s(0x1, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); + count = read_regn_el0(pmevcntr, 0); + if (count < pre_overflow2) { + count += COUNT + MARGIN; + if (count > max) + max = count; + if (count < min) + min = count; + overflow = true; + report_info("iter=%d count=%ld min=%ld max=%ld overflow!!!", + i, count, min, max); + continue; + } + count -= pre_overflow2; + if (count > max) + max = count; + if (count < min) + min = count; + } + report_info("overflow=%d min=%ld max=%ld COUNT=%d MARGIN=%d", + overflow, min, max, COUNT, MARGIN); + report(!overflow, "memaccess is reliable"); +} + static void test_chain_promotion(bool unused) { uint32_t events[] = {MEM_ACCESS, CHAIN}; @@ -1203,6 +1252,9 @@ int main(int argc, char *argv[]) } else if (strcmp(argv[1], "pmu-basic-event-count") == 0) { run_event_test(argv[1], test_basic_event_count, false); run_event_test(argv[1], test_basic_event_count, true); + } else if (strcmp(argv[1], "pmu-memaccess-reliability") == 0) { + run_event_test(argv[1], test_memaccess_reliability, false); + run_event_test(argv[1], test_memaccess_reliability, true); } else if (strcmp(argv[1], "pmu-mem-access") == 0) { run_event_test(argv[1], test_mem_access, false); run_event_test(argv[1], test_mem_access, true); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 5e67b558..301261aa 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -90,6 +90,12 @@ groups = pmu arch = arm64 extra_params = -append 'pmu-mem-access' +[pmu-memaccess-reliability] +file = pmu.flat +groups = pmu +arch = arm64 +extra_params = -append 'pmu-memaccess-reliability' + [pmu-sw-incr] file = pmu.flat groups = pmu From patchwork Wed Mar 15 11:07:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13175651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78F4BC6FD1D for ; Wed, 15 Mar 2023 11:20:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbjCOLUj (ORCPT ); Wed, 15 Mar 2023 07:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231785AbjCOLUR (ORCPT ); Wed, 15 Mar 2023 07:20:17 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4B0E7A915 for ; Wed, 15 Mar 2023 04:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678879089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pw5und1amevi6fGrmvoVmaGCPWmitHsfJCR1o0JTYMk=; b=Xgxw4hs6ar9MQV+l3f3I/XnIiaNjhmx5HJ6kmQ2BnSugZecA22oT1IaL2+ma2b0Kx5nUUW GUJUkPLjHXBl7mO2SxLvyOw8SwbqIMtKZAqnA+xoMX7kh5OKRPQQ7VKnpbL7gxtYe846Gt UzEP99T7KtkdqzVVQMaauIqtyXazydM= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-613-BLTLcpIFNVygVpIQ8I_qgg-1; Wed, 15 Mar 2023 07:07:48 -0400 X-MC-Unique: BLTLcpIFNVygVpIQ8I_qgg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C01A5382C970; Wed, 15 Mar 2023 11:07:47 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.193.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id BBA2B202701E; Wed, 15 Mar 2023 11:07:45 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, andrew.jones@linux.dev, maz@kernel.org, will@kernel.org, oliver.upton@linux.dev, ricarkol@google.com, reijiw@google.com, alexandru.elisei@arm.com Subject: [kvm-unit-tests PATCH 6/6] arm: pmu-chain-promotion: Increase the count and margin values Date: Wed, 15 Mar 2023 12:07:25 +0100 Message-Id: <20230315110725.1215523-7-eric.auger@redhat.com> In-Reply-To: <20230315110725.1215523-1-eric.auger@redhat.com> References: <20230315110725.1215523-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Let's increase the mem_access loop count by defining COUNT=250 (instead of 20) and define a more reasonable margin (100 instead of 15 previously) so that it gives better chance to accommodate for HW implementation variance. Those values were chosen arbitrarily higher. Those values fix the random failures on ThunderX2 machines. Signed-off-by: Eric Auger --- arm/pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index c3d2a428..d897d8d3 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -60,8 +60,8 @@ #define ALL_CLEAR 0x0000000000000000ULL #define PRE_OVERFLOW_32 0x00000000FFFFFFF0ULL #define PRE_OVERFLOW_64 0xFFFFFFFFFFFFFFF0ULL -#define COUNT 20 -#define MARGIN 15 +#define COUNT 250 +#define MARGIN 100 /* * PRE_OVERFLOW2 is set so that 1st COUNT iterations do not * produce 32b overflow and 2d COUNT iterations do. To accommodate