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No functional change intended. Reviewed-by: Janosch Frank Signed-off-by: Nina Schoetterl-Glausch --- s390x/spec_ex.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c index 42ecaed3..2adc5996 100644 --- a/s390x/spec_ex.c +++ b/s390x/spec_ex.c @@ -105,10 +105,7 @@ static int check_invalid_psw(void) /* For normal PSWs bit 12 has to be 0 to be a valid PSW*/ static int psw_bit_12_is_1(void) { - struct psw invalid = { - .mask = BIT(63 - 12), - .addr = 0x00000000deadbeee - }; + struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee); expect_invalid_psw(invalid); load_psw(invalid); @@ -118,10 +115,7 @@ static int psw_bit_12_is_1(void) /* A short PSW needs to have bit 12 set to be valid. */ static int short_psw_bit_12_is_0(void) { - struct psw invalid = { - .mask = BIT(63 - 12), - .addr = 0x00000000deadbeee - }; + struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee); struct short_psw short_invalid = { .mask = 0x0, .addr = 0xdeadbeee From patchwork Fri Mar 17 13:32:52 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 13:33:02 +0000 (GMT) From: Nina Schoetterl-Glausch To: Thomas Huth , Janosch Frank , Claudio Imbrenda Cc: Nina Schoetterl-Glausch , David Hildenbrand , kvm@vger.kernel.org, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH v4 2/3] s390x/spec_ex: Add test introducing odd address into PSW Date: Fri, 17 Mar 2023 14:32:52 +0100 Message-Id: <20230317133253.965010-3-nsg@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317133253.965010-1-nsg@linux.ibm.com> References: <20230317133253.965010-1-nsg@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 76zEg8lV3YGoMa8WsBhp5pstx67WpNxm X-Proofpoint-GUID: QpCNnFibCPwf5CJD_5bShnDvJO4IftZ4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-17_08,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 bulkscore=0 mlxscore=0 phishscore=0 clxscore=1015 suspectscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303170092 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Instructions on s390 must be halfword aligned. Introducing an odd instruction address into the PSW leads to a specification exception when attempting to execute the instruction at the odd address. Add a test for this. Acked-by: Janosch Frank Signed-off-by: Nina Schoetterl-Glausch --- s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c index 2adc5996..ab023347 100644 --- a/s390x/spec_ex.c +++ b/s390x/spec_ex.c @@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw) invalid_psw_expected = true; } +static void clear_invalid_psw(void) +{ + expected_psw = PSW(0, 0); + invalid_psw_expected = false; +} + static int check_invalid_psw(void) { /* Since the fixup sets this to false we check for false here. */ if (!invalid_psw_expected) { + /* + * Early exception recognition: pgm_int_id == 0. + * Late exception recognition: psw address has been + * incremented by pgm_int_id (unpredictable value) + */ if (expected_psw.mask == invalid_psw.mask && - expected_psw.addr == invalid_psw.addr) + expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id) return 0; report_fail("Wrong invalid PSW"); } else { @@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void) return check_invalid_psw(); } +extern char misaligned_code[]; +asm ( ".balign 2\n" +" . = . + 1\n" +"misaligned_code:\n" +" larl %r0,0\n" +" br %r1\n" +); + +static int psw_odd_address(void) +{ + struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code); + uint64_t executed_addr; + + expect_invalid_psw(odd); + fixup_psw.mask = extract_psw_mask(); + asm volatile ( "xgr %%r0,%%r0\n" + " larl %%r1,0f\n" + " stg %%r1,%[fixup_addr]\n" + " lpswe %[odd_psw]\n" + "0: lr %[executed_addr],%%r0\n" + : [fixup_addr] "=&T" (fixup_psw.addr), + [executed_addr] "=d" (executed_addr) + : [odd_psw] "Q" (odd) + : "cc", "%r0", "%r1" + ); + + if (!executed_addr) { + return check_invalid_psw(); + } else { + assert(executed_addr == odd.addr); + clear_invalid_psw(); + report_fail("did not execute unaligned instructions"); + return 1; + } +} + /* A short PSW needs to have bit 12 set to be valid. */ static int short_psw_bit_12_is_0(void) { @@ -170,6 +217,7 @@ struct spec_ex_trigger { static const struct spec_ex_trigger spec_ex_triggers[] = { { "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw }, { "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw }, + { "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw }, { "bad_alignment", &bad_alignment, true, NULL }, { "not_even", ¬_even, true, NULL }, { NULL, NULL, false, NULL }, From patchwork Fri Mar 17 13:32:53 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 13:33:06 +0000 (GMT) From: Nina Schoetterl-Glausch To: Thomas Huth , Janosch Frank , Claudio Imbrenda Cc: Nina Schoetterl-Glausch , David Hildenbrand , kvm@vger.kernel.org, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH v4 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address Date: Fri, 17 Mar 2023 14:32:53 +0100 Message-Id: <20230317133253.965010-4-nsg@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317133253.965010-1-nsg@linux.ibm.com> References: <20230317133253.965010-1-nsg@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: jYwWtLBGQs65KfG4wpScdJlrEjHlKex2 X-Proofpoint-GUID: bF6GB0fjH8jHlNnp2XTwdn3hHx8vFJMy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-17_08,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303170092 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The EXECUTE instruction executes the instruction at the given target address. This address must be halfword aligned, otherwise a specification exception occurs. Add a test for this. Reviewed-by: Janosch Frank Signed-off-by: Nina Schoetterl-Glausch --- s390x/spec_ex.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c index ab023347..b4b9095f 100644 --- a/s390x/spec_ex.c +++ b/s390x/spec_ex.c @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void) return 0; } +static int odd_ex_target(void) +{ + uint64_t pre_target_addr; + int to = 0, from = 0x0dd; + + asm volatile ( ".pushsection .text.ex_odd\n" + " .balign 2\n" + "pre_odd_ex_target:\n" + " . = . + 1\n" + " lr %[to],%[from]\n" + " .popsection\n" + + " larl %[pre_target_addr],pre_odd_ex_target\n" + " ex 0,1(%[pre_target_addr])\n" + : [pre_target_addr] "=&a" (pre_target_addr), + [to] "+d" (to) + : [from] "d" (from) + ); + + assert((pre_target_addr + 1) & 1); + report(to != from, "did not perform ex with odd target"); + return 0; +} + static int bad_alignment(void) { uint32_t words[5] __attribute__((aligned(16))); @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = { { "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw }, { "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw }, { "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw }, + { "odd_ex_target", &odd_ex_target, true, NULL }, { "bad_alignment", &bad_alignment, true, NULL }, { "not_even", ¬_even, true, NULL }, { NULL, NULL, false, NULL },