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[0] https://www.ti.com/lit/gpn/am625 Page 1. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index acc7f8ab6426..4193c2b3eed6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -148,7 +148,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; From patchwork Mon Mar 20 04:49:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 13180720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58C31C7618A for ; Mon, 20 Mar 2023 04:50:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=p7URjQWj0Qea/GG0VniHo1hoiPHYwWdPv1siMphqAiI=; b=Scfo0I2zCOFs8R X/O6w9HG9kzwEDGh+2uXr9Zk3+ZoY1K2Hr4TjCSSXhuiEnYHZ4DW2wRp53ps08kzKdVKuomj+QXZz Y4oa9eGCfH2Aed9ycIZxc6O67bFr/vF9MoFHbzzeCffuxwoAwvnN1ExtELQdVBTEoaGuZDUFCT9Jf 1GVEiGRU177lBgpeD4urwzE9We0JJSdyQVXGK+tf/9CCb4L4HFuqmmk9ur6Cq8hUR+7IBmzsS+8ae F9mDgWSyUUDNfVd3rBhj7ZBaxvYc2bC2ge5p0WFq8igyIeMq/xF9QMoUWUs39jQbm226WIVmeND/z eo1WdTgwsj/d43JPXP1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pe7T3-0085CL-2o; Mon, 20 Mar 2023 04:49:57 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pe7T0-0085BU-1Q for linux-arm-kernel@lists.infradead.org; Mon, 20 Mar 2023 04:49:56 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32K4ng78024966; Sun, 19 Mar 2023 23:49:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679287782; bh=akxJQA0mgVTQ5d2mpZskCWVUMJDkXK3PiSFjoqjCdTU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kYcc7/7Y8qbM6dtz2+sgOwXBlHN5FieXk+8JfBrTsI+6sF6axjzi5Zz3rbNYpf3E/ fYCyD2QvjlBxAmLXFRH/3P9H+i6NNCDZbX68B8tRq8/AFCai39cRH8BPs3CbhQT5OQ PmnR5cmYiBEwAz3J1O4O8T+Sr7tKXwLgzqqBxCEs= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32K4ngrD012013 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 19 Mar 2023 23:49:42 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 19 Mar 2023 23:49:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 19 Mar 2023 23:49:41 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32K4naj0022696; Sun, 19 Mar 2023 23:49:39 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski CC: , , Subject: [PATCH 2/2] arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB Date: Mon, 20 Mar 2023 10:19:35 +0530 Message-ID: <20230320044935.2512288-2-vigneshr@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230320044935.2512288-1-vigneshr@ti.com> References: <20230320044935.2512288-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230319_214954_538552_18426B57 X-CRM114-Status: GOOD ( 11.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index 9734549851c0..58f1c43edcf8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -97,7 +97,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; };