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Tue, 21 Mar 2023 02:07:06 -0500 From: Parth Gajjar To: , , CC: , , , , , , , Parth Gajjar Subject: [PATCH v2 1/2] dt-bindings: gpu: mali-utgard: Add xlnx,zynqmp-mali compatible Date: Tue, 21 Mar 2023 00:06:18 -0700 Message-ID: <20230321070619.29440-2-parth.gajjar@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321070619.29440-1-parth.gajjar@amd.com> References: <20230321070619.29440-1-parth.gajjar@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT066:EE_|MN0PR12MB6150:EE_ X-MS-Office365-Filtering-Correlation-Id: da4bb568-27b9-40cc-02b2-08db29dae64c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t2NH3hYo+TTBlFIEaMjUDujRRQtaeSzGHgHwuR4Fn2DhYGBMXfDQvLr8Tx7UZe1bwt6EoGBTmPXuAjInQyZJdkvur48RpgDDvp31lWPUWkbdnhydSuWTR8Zt1fWT3adTaLPh/tuT3vLZvRu9OMiJ2PqSs+YZYDlE/NFkleV5YXV5C2KqtPDE4cI5zyanoeZ8QkPJ1WaL+vAmlYbsqE1NmhAHjItPXC3g8GbFntjYeYdwNxkd1B7A9yNjMUB2mmze5FcHIKzzYb2XObiZuYSUMktAIpwJJjKnlOQGGgxVZBognRqEKzfkOFBRQ+F3Pd77kMcarT198H+jxn83RFSoaNUXof0KjvDAGwE8KmzVBlxniU+WS6T4DvrEAYZzsusrnlihzrDfFXjYJSiiKj40/AQFjqe+/MqsUCSb96P1idirQmvHc1xaELlN2wxwPZquzqT786L+gxRtwmhkiGRtpfpVq4FucIR2Fz8b9VpgUVWLdENRHqAyb2NCvJI2oLk+rXQmlUnIho1T6MmL3nHWgozYqdwhDJCDcGM2vHCudA+j9tW5m2qBATOMw5FjG3WDJfavIGEwvlDlWuZ1p6OH/+QyXtDOZKpwrT9Y0Lnes+91e2nQRq7nV6cFfZp3B/Ms1vxTUGNZgtWr52adqBmC5Kftn6XMaIKMrO8XRKVxkjjuRS+7AGr8jKCii3tnhocr0n4kf7KxsDXW34UHiEGQJeZn3yUxDOSr0k0kJEB0fEs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199018)(46966006)(36840700001)(40470700004)(40460700003)(40480700001)(5660300002)(4326008)(8676002)(70586007)(70206006)(110136005)(316002)(54906003)(2616005)(6666004)(8936002)(36860700001)(44832011)(26005)(1076003)(336012)(41300700001)(4744005)(186003)(426003)(47076005)(478600001)(82310400005)(86362001)(36756003)(2906002)(82740400003)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Xilinx zynqmp SoC contains Mali400, so add its specific compatible to bindings. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar Acked-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index 318122d95eb5..0fae1ef013be 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -33,6 +33,7 @@ properties: - rockchip,rk3228-mali - samsung,exynos4210-mali - stericsson,db8500-mali + - xlnx,zynqmp-mali - const: arm,mali-400 - items: - enum: From patchwork Tue Mar 21 07:06:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gajjar, Parth" X-Patchwork-Id: 13182328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A04FFC761A6 for ; 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Tue, 21 Mar 2023 02:07:15 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 21 Mar 2023 02:07:14 -0500 Received: from xsjssw-mmedia2.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 21 Mar 2023 02:07:13 -0500 From: Parth Gajjar To: , , CC: , , , , , , , Parth Gajjar Subject: [PATCH v2 2/2] arm64: zynqmp: Add mali-400 gpu node for zynqmp Date: Tue, 21 Mar 2023 00:06:19 -0700 Message-ID: <20230321070619.29440-3-parth.gajjar@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321070619.29440-1-parth.gajjar@amd.com> References: <20230321070619.29440-1-parth.gajjar@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT066:EE_|SN7PR12MB6792:EE_ X-MS-Office365-Filtering-Correlation-Id: 44a3cb08-c419-4ff7-ccee-08db29dae71d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 3 +++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 11 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 3e9979ab60bb..5e7e1bf5b811 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -95,6 +95,10 @@ &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; +&gpu { + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; +}; + &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 20e83ca47b5d..34412304d09f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -287,3 +287,7 @@ &gpio { "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index b05be2552826..f89ef2afcd9e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -108,6 +108,9 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; &i2c1 { status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05a2b79738af..6e0106bf1294 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -152,6 +152,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 6948fd40554b..c74bc3ff703b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -161,6 +161,10 @@ &gpio { "", "", "", ""; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; pinctrl-names = "default", "gpio"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5fd6b70a154a..13c43324f1d2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -216,6 +216,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index bd8f20f3223d..485585c491f4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -122,6 +122,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 96feaad30166..44ec9edd2452 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -127,6 +127,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 24a252317150..09773b7200f8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -227,6 +227,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d685d8fbc36a..e0305dcbb010 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -187,6 +187,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 153db59dc4b3..bb0d0be30aa0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -411,6 +411,18 @@ gic: interrupt-controller@f9010000 { interrupts = <1 9 0xf04>; }; + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; + reg = <0x0 0xfd4b0000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, + <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; + power-domains = <&zynqmp_firmware PD_GPU>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access.