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Fri, 24 Mar 2023 09:52:41 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id a5-20020aa780c5000000b0062b5a55835dsm1420289pfn.213.2023.03.24.09.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 09:52:40 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 1/3] memory: brcmstb_memc: Cache configuration register value Date: Fri, 24 Mar 2023 09:52:29 -0700 Message-Id: <20230324165231.3468069-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230324_095243_742418_EF437FE6 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The configuration register does not change once the DDR controller is configured, in preparation for providing more information about the DDR type/width in subsequent changes, store this value so we can retrieve it. Signed-off-by: Florian Fainelli --- drivers/memory/brcmstb_memc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 233a53f5bce1..67c75e21c95e 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -29,18 +29,15 @@ struct brcmstb_memc { struct device *dev; void __iomem *ddr_ctrl; unsigned int timeout_cycles; + u32 config_reg; u32 frequency; u32 srpd_offset; }; static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc) { - void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG; - u32 reg; - - reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK; - - return reg == CNTRLR_CONFIG_LPDDR4_SHIFT; + return (memc->config_reg & CNTRLR_CONFIG_MASK) == + CNTRLR_CONFIG_LPDDR4_SHIFT; } static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc, @@ -148,6 +145,9 @@ static int brcmstb_memc_probe(struct platform_device *pdev) of_property_read_u32(pdev->dev.of_node, "clock-frequency", &memc->frequency); + memc->config_reg = readl_relaxed(memc->ddr_ctrl + + REG_MEMC_CNTRLR_CONFIG); + ret = sysfs_create_group(&dev->kobj, &dev_attr_group); if (ret) return ret; From patchwork Fri Mar 24 16:52:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 13187001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76D9FC6FD1C for ; Fri, 24 Mar 2023 16:53:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 24 Mar 2023 09:52:43 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id a5-20020aa780c5000000b0062b5a55835dsm1420289pfn.213.2023.03.24.09.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 09:52:42 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 2/3] Documentation: sysfs: brcmstb-memc: Document new attributes Date: Fri, 24 Mar 2023 09:52:30 -0700 Message-Id: <20230324165231.3468069-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230324_095246_243966_2ABFB89E X-CRM114-Status: GOOD ( 11.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the DDR rank, size, total size, width and type attributes. Signed-off-by: Florian Fainelli --- .../ABI/testing/sysfs-platform-brcmstb-memc | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc b/Documentation/ABI/testing/sysfs-platform-brcmstb-memc index 2f2b750ac2fd..bc969c02b85f 100644 --- a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc +++ b/Documentation/ABI/testing/sysfs-platform-brcmstb-memc @@ -1,3 +1,42 @@ +What: /sys/bus/platform/devices/*/ddr_rank +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + Displays whether the device is single or dual rank. + +What: /sys/bus/platform/devices/*/ddr_size +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies the size of each DRAM device in the first + (or only) rank + +What: /sys/bus/platform/devices/*/ddr_total_width +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies the total data width of all DRAM devices + (in each rank) + +What: /sys/bus/platform/devices/*/ddr_type +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies DRAM technology type. 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Fri, 24 Mar 2023 09:52:44 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 3/3] memory: brcmstb_memc: Add new DDR attributes Date: Fri, 24 Mar 2023 09:52:31 -0700 Message-Id: <20230324165231.3468069-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230324_095247_868309_567CCD12 X-CRM114-Status: GOOD ( 14.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Provide information about the DDR size, type, width, total width, dual/single rank. This is useful for reporting purposes and inventory of the system(s). Signed-off-by: Florian Fainelli --- drivers/memory/brcmstb_memc.c | 80 ++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 67c75e21c95e..032567dfd6e2 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -13,7 +13,14 @@ #define REG_MEMC_CNTRLR_CONFIG 0x00 #define CNTRLR_CONFIG_LPDDR4_SHIFT 5 -#define CNTRLR_CONFIG_MASK 0xf +#define CNTRLR_CONFIG_MASK GENMASK(3, 0) +#define CNTRLR_CONFIG_SIZE_SHIFT 4 +#define CNTRLR_CONFIG_SIZE_MASK GENMASK(7, 4) +#define CNTRLR_CONFIG_WIDTH_SHIFT 8 +#define CNTRLR_CONFIG_WIDTH_MASK GENMASK(9, 8) +#define CNTRLR_CONFIG_TOT_WIDTH_SHIFT 10 +#define CNTRLR_CONFIG_TOT_WIDTH_MASK GENMASK(11, 10) +#define CNTRLR_CONFIG_RANK_SHIFT 16 #define REG_MEMC_SRPD_CFG_21 0x20 #define REG_MEMC_SRPD_CFG_20 0x34 #define REG_MEMC_SRPD_CFG_1x 0x3c @@ -63,6 +70,67 @@ static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc, return 0; } +static ssize_t ddr_rank_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", + memc->config_reg & CNTRLR_CONFIG_RANK_SHIFT ? + "dual" : "single"); +} + +static ssize_t ddr_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_SIZE_MASK) >> + CNTRLR_CONFIG_SIZE_SHIFT; + + return sprintf(buf, "%dMb\n", 256 << val); +} + +static ssize_t ddr_total_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_TOT_WIDTH_MASK) >> + CNTRLR_CONFIG_TOT_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + +static ssize_t ddr_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + const char *ddr_type_to_str[] = { + "DDR2", + "DDR3", + "DDR4", + "GDDR5M", + "GDDR5", + "LPDDR4", + }; + u32 val = memc->config_reg & CNTRLR_CONFIG_MASK; + const char *type = "unknown"; + + if (val < ARRAY_SIZE(ddr_type_to_str)) + type = ddr_type_to_str[val]; + + return sprintf(buf, "%s\n", type); +} + +static ssize_t ddr_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_WIDTH_MASK) >> + CNTRLR_CONFIG_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + static ssize_t frequency_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -105,10 +173,20 @@ static ssize_t srpd_store(struct device *dev, struct device_attribute *attr, return count; } +static DEVICE_ATTR_RO(ddr_rank); +static DEVICE_ATTR_RO(ddr_size); +static DEVICE_ATTR_RO(ddr_total_width); +static DEVICE_ATTR_RO(ddr_type); +static DEVICE_ATTR_RO(ddr_width); static DEVICE_ATTR_RO(frequency); static DEVICE_ATTR_RW(srpd); static struct attribute *dev_attrs[] = { + &dev_attr_ddr_rank.attr, + &dev_attr_ddr_size.attr, + &dev_attr_ddr_total_width.attr, + &dev_attr_ddr_type.attr, + &dev_attr_ddr_width.attr, &dev_attr_frequency.attr, &dev_attr_srpd.attr, NULL,