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Sat, 25 Mar 2023 18:19:55 -0700 (PDT) Date: Sun, 26 Mar 2023 01:19:48 +0000 In-Reply-To: <20230326011950.405749-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230326011950.405749-1-jingzhangos@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230326011950.405749-2-jingzhangos@google.com> Subject: [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230325_181957_684655_38BA6EEB X-CRM114-Status: GOOD ( 11.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since number of context-aware breakpoints must be no more than number of supported breakpoints according to Arm ARM, return an error if userspace tries to set CTX_CMPS field to such value. Signed-off-by: Jing Zhang --- arch/arm64/kvm/id_regs.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c index 726b810b6e06..64691273980b 100644 --- a/arch/arm64/kvm/id_regs.c +++ b/arch/arm64/kvm/id_regs.c @@ -362,10 +362,15 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { - u8 pmuver, host_pmuver; + u8 pmuver, host_pmuver, brps, ctx_cmps; bool valid_pmu; int ret; + brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), val); + ctx_cmps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), val); + if (ctx_cmps > brps) + return -EINVAL; + host_pmuver = kvm_arm_pmu_get_pmuver_limit(); /* @@ -623,6 +628,10 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = { .ftr_bits = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_BRPs_SHIFT, ID_AA64DFR0_EL1_BRPs_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, ID_AA64DFR0_EL1_CTX_CMPs_WIDTH, 0), ARM64_FTR_END, }, .init = init_id_aa64dfr0_el1, }, From patchwork Sun Mar 26 01:19:49 2023 Content-Type: text/plain; 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Sat, 25 Mar 2023 18:19:57 -0700 (PDT) Date: Sun, 26 Mar 2023 01:19:49 +0000 In-Reply-To: <20230326011950.405749-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230326011950.405749-1-jingzhangos@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230326011950.405749-3-jingzhangos@google.com> Subject: [PATCH v1 2/3] KVM: arm64: Enable writable for remaining fields for ID_AA64DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230325_181958_446627_89B0A92A X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable writable from userspace for all remaining fields in ID_AA64DFR0_EL1, which don't need special handlings for dependency. Signed-off-by: Jing Zhang --- arch/arm64/kvm/id_regs.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c index 64691273980b..e64152aa448b 100644 --- a/arch/arm64/kvm/id_regs.c +++ b/arch/arm64/kvm/id_regs.c @@ -626,12 +626,32 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, .ftr_bits = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_DebugVer_SHIFT, ID_AA64DFR0_EL1_DebugVer_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_TraceVer_SHIFT, ID_AA64DFR0_EL1_TraceVer_WIDTH, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_WIDTH, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, ID_AA64DFR0_EL1_BRPs_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_WRPs_SHIFT, ID_AA64DFR0_EL1_WRPs_WIDTH, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, ID_AA64DFR0_EL1_CTX_CMPs_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_PMSVer_SHIFT, ID_AA64DFR0_EL1_PMSVer_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_DoubleLock_SHIFT, ID_AA64DFR0_EL1_DoubleLock_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_TraceFilt_SHIFT, ID_AA64DFR0_EL1_TraceFilt_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_TraceBuffer_SHIFT, ID_AA64DFR0_EL1_TraceBuffer_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_MTPMU_SHIFT, ID_AA64DFR0_EL1_MTPMU_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_BRBE_SHIFT, ID_AA64DFR0_EL1_BRBE_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_AA64DFR0_EL1_HPMN0_SHIFT, ID_AA64DFR0_EL1_HPMN0_WIDTH, 0), ARM64_FTR_END, }, .init = init_id_aa64dfr0_el1, }, From patchwork Sun Mar 26 01:19:50 2023 Content-Type: text/plain; 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Sat, 25 Mar 2023 18:19:59 -0700 (PDT) Date: Sun, 26 Mar 2023 01:19:50 +0000 In-Reply-To: <20230326011950.405749-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230326011950.405749-1-jingzhangos@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230326011950.405749-4-jingzhangos@google.com> Subject: [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230325_182000_736972_AAE20DCF X-CRM114-Status: UNSURE ( 8.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All valid fields in ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/id_regs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c index e64152aa448b..7dc2fb8121f3 100644 --- a/arch/arm64/kvm/id_regs.c +++ b/arch/arm64/kvm/id_regs.c @@ -565,8 +565,22 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, }, .ftr_bits = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopDbg_SHIFT, ID_DFR0_EL1_CopDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopSDbg_SHIFT, ID_DFR0_EL1_CopSDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MMapDbg_SHIFT, ID_DFR0_EL1_MMapDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopTrc_SHIFT, ID_DFR0_EL1_CopTrc_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MMapTrc_SHIFT, ID_DFR0_EL1_MMapTrc_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MProfDbg_SHIFT, ID_DFR0_EL1_MProfDbg_WIDTH, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_PerfMon_SHIFT, ID_DFR0_EL1_PerfMon_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_TraceFilt_SHIFT, ID_DFR0_EL1_TraceFilt_WIDTH, 0), ARM64_FTR_END, }, .init = init_id_dfr0_el1, },