From patchwork Mon Mar 27 11:59:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13189100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C589C76195 for ; Mon, 27 Mar 2023 12:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Xau3itL6rNsOm8o1GRE2Qk2arvJ2Aj884qrnCvzj/1Y=; b=zFLX2Od+iwJTQP 978fTI6uNMmdwLtaQc4JSn+bbM8P3INLpmNzmM+kKiXYDT53GHePKVYVfbW/oygRnqKhIwBp+VcUI r3Xql4GS7CilfPNp4RbeGF8yfW52untmBBQ60Pojbo7tfoXV6Z6FGogBjZfliKOluVkoedTaUfiMS j/zvr1eOPi4z84wrDkwYUw0J6q2D1zhDFZNZTLjqMdqEcO056/CTd0Hzdef4TVjEkOUWL/oq4TmDZ RWvdj/bizVZcQTPiKzIKyweM2X8QcdzdOVcD+RMTv/+V0POcod/rM+NLePedx8iIr5xUSuD0AdtuS hIj4FZCrhTay05GNhdZQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWd-00AoYJ-0m; Mon, 27 Mar 2023 12:00:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWT-00AoUW-1E for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 12:00:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 40A00C14; Mon, 27 Mar 2023 05:01:08 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6FFF83F663; Mon, 27 Mar 2023 05:00:21 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Sudeep Holla , Oliver Upton , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] cacheinfo: Check sib_leaf in cache_leaves_are_shared() Date: Mon, 27 Mar 2023 13:59:49 +0200 Message-Id: <20230327115953.788244-2-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230327115953.788244-1-pierre.gondois@arm.com> References: <20230327115953.788244-1-pierre.gondois@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_050025_471839_DA6079B4 X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If 'this_leaf' is a L2 cache (or higher) and 'sib_leaf' is a L1 cache, the caches are detected as shared. Indeed, cache_leaves_are_shared() only checks the cache level of 'this_leaf' when 'sib_leaf''s cache level should also be checked. Also update the comment: the function is called when populating 'shared_cpu_map'. Signed-off-by: Pierre Gondois --- drivers/base/cacheinfo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index f6573c335f4c..4ca117574af1 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -38,11 +38,10 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, { /* * For non DT/ACPI systems, assume unique level 1 caches, - * system-wide shared caches for all other levels. This will be used - * only if arch specific code has not populated shared_cpu_map + * system-wide shared caches for all other levels. */ if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) - return !(this_leaf->level == 1); + return (this_leaf->level != 1) || (sib_leaf->level != 1); if ((sib_leaf->attributes & CACHE_ID) && (this_leaf->attributes & CACHE_ID)) From patchwork Mon Mar 27 11:59:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13189101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 303C3C7619A for ; Mon, 27 Mar 2023 12:01:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=23Mp0IzRGXCd70WiZBG8Pcwavjb0o7TFJZ6DI4wr52M=; b=kwDMfvdmblJPUk 7JF4oATncKYP7FR2vcjYCy//tn9VkfFBgDu0NwFUL9sS67MngzKbKqAgkGKrbWIfsMSCItbWJeylt oG4T7a5S7YbHY+zS8gCI0/hbxOLUIY5ddx6cST3+k85jSSQvOhf3Lo8AhyuUb6k4L6oFbjIMOlduV ktujqO+By99p6k5PQ6uGoAqhV3mxQ5XTAMKGfO7pL7Or12ttqUaSSSeSQWoGtkBtOiJuaN/BPd2Id /7Koujul5kHpgv5NDc9cJ+necvCV5rXBmrEPQ+MK5OtMp+8f6uQr2mWfHg1YpQ1IeHcCM44JDpE8X nCQT4jC/Ap016nuok8qA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWe-00AoYi-0k; Mon, 27 Mar 2023 12:00:36 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWZ-00AoXK-1V for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 12:00:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 559A1FEC; Mon, 27 Mar 2023 05:01:13 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 72C6C3F663; Mon, 27 Mar 2023 05:00:26 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Sudeep Holla , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] cacheinfo: Check cache properties are present in DT Date: Mon, 27 Mar 2023 13:59:50 +0200 Message-Id: <20230327115953.788244-3-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230327115953.788244-1-pierre.gondois@arm.com> References: <20230327115953.788244-1-pierre.gondois@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_050031_553605_60B29157 X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If a Device Tree (DT) is used, the presence of cache properties is assumed. Not finding any is not considered. For arm64 platforms, cache information can be fetched from the clidr_el1 register. Checking whether cache information is available in the DT allows to switch to using clidr_el1. init_of_cache_level() \-of_count_cache_leaves() will assume there a 2 cache leaves (L1 data/instruction caches), which can be different from clidr_el1 information. cache_setup_of_node() tries to read cache properties in the DT. If there are none, this is considered a success. Knowing no information was available would allow to switch to using clidr_el1. Signed-off-by: Pierre Gondois Reported-by: Alexandre Ghiti --- drivers/base/cacheinfo.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 4ca117574af1..5b0edf2d5da8 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -78,6 +78,9 @@ bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y) } #ifdef CONFIG_OF + +static bool of_check_cache_nodes(struct device_node *np); + /* OF properties to query for a given cache type */ struct cache_type_info { const char *size_prop; @@ -205,6 +208,11 @@ static int cache_setup_of_node(unsigned int cpu) return -ENOENT; } + if (!of_check_cache_nodes(np)) { + of_node_put(np); + return -ENOENT; + } + prev = np; while (index < cache_leaves(cpu)) { @@ -229,6 +237,25 @@ static int cache_setup_of_node(unsigned int cpu) return 0; } +static bool of_check_cache_nodes(struct device_node *np) +{ + struct device_node *next; + + if (of_property_read_bool(np, "cache-size") || + of_property_read_bool(np, "i-cache-size") || + of_property_read_bool(np, "d-cache-size") || + of_property_read_bool(np, "cache-unified")) + return true; + + next = of_find_next_cache_node(np); + if (next) { + of_node_put(next); + return true; + } + + return false; +} + static int of_count_cache_leaves(struct device_node *np) { unsigned int leaves = 0; @@ -260,6 +287,9 @@ int init_of_cache_level(unsigned int cpu) struct device_node *prev = NULL; unsigned int levels = 0, leaves, level; + if (!of_check_cache_nodes(np)) + goto err_out; + leaves = of_count_cache_leaves(np); if (leaves > 0) levels = 1; From patchwork Mon Mar 27 11:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13189102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D5C4C76195 for ; Mon, 27 Mar 2023 12:01:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7VpsMWOpg99rIQ1eKMgYC8yNQ5el3pldBtCIVghWmrk=; b=vn4IWPFCM1i5lF rn/9aLBmVCU6vjww76Cr96MqNANE0lWYx00gvs1gIahvtsNcTqoQI1RvTSHb21QSST9cEqL4gUffW A43mKAJpf/Da2LO9ONtyd8+vy/OTjII4jwVLeB2WHpAizQxvEq3vczMFcz7eu3vEp2t3DJQ7jdzWK EgnhN9rH/V7lw1kI2cTJhEOo8ztRR0wXS8BTjcmylWki4vyh+NE5j9AQA6dmd0xcdzkr5Ymn16JIF /toAIJVFd0ZDJorPc36Di9ZILQf/C/qaIkoTHCVG4jBFsnMQj2GvzGKFq6FeXAs92p7CfASS57ks0 /C6EoH+wpdHsBQvN4OFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWt-00AoeX-2V; Mon, 27 Mar 2023 12:00:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pglWh-00AoZo-1E for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 12:00:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E520B1042; Mon, 27 Mar 2023 05:01:18 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8BAAF3F663; Mon, 27 Mar 2023 05:00:31 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Sudeep Holla , Palmer Dabbelt , Oliver Upton , Akihiko Odaki , Gavin Shan , Conor Dooley , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] cacheinfo: Add use_arch[|_cache]_info field/function Date: Mon, 27 Mar 2023 13:59:51 +0200 Message-Id: <20230327115953.788244-4-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230327115953.788244-1-pierre.gondois@arm.com> References: <20230327115953.788244-1-pierre.gondois@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_050039_511707_2DFC48BF X-CRM114-Status: GOOD ( 16.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The cache information can be extracted from either a Device Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). The clidr_el1 register is used only if DT/ACPI information is not available. It does not states how caches are shared among CPUs. Add a use_arch_cache_info field/function to identify when the DT/ACPI doesn't provide cache information. Use this information to assume L1 caches are privates and L2 and higher are shared among all CPUs. Signed-off-by: Pierre Gondois --- arch/arm64/kernel/cacheinfo.c | 5 +++++ drivers/base/cacheinfo.c | 20 ++++++++++++++++++-- include/linux/cacheinfo.h | 2 ++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index c307f69e9b55..b6306cda0fa7 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -96,3 +96,8 @@ int populate_cache_leaves(unsigned int cpu) } return 0; } + +bool use_arch_cache_info(unsigned int cpu) +{ + return true; +} diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 5b0edf2d5da8..c6266ccc2df5 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -40,8 +40,9 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, * For non DT/ACPI systems, assume unique level 1 caches, * system-wide shared caches for all other levels. */ - if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) - return (this_leaf->level != 1) || (sib_leaf->level != 1); + if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) || + this_leaf->use_arch_info) + return (this_leaf->level != 1) && (sib_leaf->level != 1); if ((sib_leaf->attributes & CACHE_ID) && (this_leaf->attributes & CACHE_ID)) @@ -330,6 +331,11 @@ int __weak cache_setup_acpi(unsigned int cpu) return -ENOTSUPP; } +bool __weak use_arch_cache_info(unsigned int cpu) +{ + return false; +} + unsigned int coherency_max_size; static int cache_setup_properties(unsigned int cpu) @@ -349,6 +355,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); struct cacheinfo *this_leaf, *sib_leaf; unsigned int index, sib_index; + bool use_arch_info = false; int ret = 0; if (this_cpu_ci->cpu_map_populated) @@ -361,6 +368,12 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) */ if (!last_level_cache_is_valid(cpu)) { ret = cache_setup_properties(cpu); + // Possibility to rely on arch specific information. + if (ret && use_arch_cache_info(cpu)) { + use_arch_info = true; + ret = 0; + } + if (ret) return ret; } @@ -370,6 +383,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) this_leaf = per_cpu_cacheinfo_idx(cpu, index); + if (use_arch_info) + this_leaf->use_arch_info = true; + cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); for_each_online_cpu(i) { struct cpu_cacheinfo *sib_cpu_ci = get_cpu_cacheinfo(i); diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 908e19d17f49..bcbb8bd5759a 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -66,6 +66,7 @@ struct cacheinfo { #define CACHE_ALLOCATE_POLICY_MASK \ (CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE) #define CACHE_ID BIT(4) + bool use_arch_info; void *fw_token; bool disable_sysfs; void *priv; @@ -82,6 +83,7 @@ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); int init_of_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); +bool use_arch_cache_info(unsigned int cpu); int cache_setup_acpi(unsigned int cpu); bool last_level_cache_is_valid(unsigned int cpu); bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y);