From patchwork Wed Mar 29 08:47:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F8DFC77B60 for ; Wed, 29 Mar 2023 08:49:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231251AbjC2Is7 (ORCPT ); Wed, 29 Mar 2023 04:48:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231246AbjC2Ish (ORCPT ); Wed, 29 Mar 2023 04:48:37 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24850270B; Wed, 29 Mar 2023 01:48:30 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T5EcU3010496; Wed, 29 Mar 2023 08:47:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=TzK5i/ajuvHn0kJ11FDgKqTnpNjR94m2w+KYenxBxS4=; b=nYhOBIXqcAAiyKfNX+UZRqiOnw58qrJ1DpipILhREgwpBezBwCuDKCqNTbxEPLoZWPiO 51yhr3r50SH4pFFSDPlXT8XYguUJf0BR+QKELqQDFIdNvCLpJmNLjjztXXliiMhampdO XxOvJkerYsF1tIG7vaLtiZDpY9R6Qoxz0mWhLphQdUql+w9OhPAg51ho1pMSZgymhJ0u naQwJXcxb7bQA+/4aoQhjy1UnrViHycTw3FzS2Ne1ds9SqdKKaeWipQXTIbVoxK/8ma7 YhBiz8I2//U13675jxIf4zLrSSKwXQapflK0iiOkUssaFGMG5l7U4CDUI96DiejZfDV3 +w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmbs88skc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lvUr031340 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:57 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:56 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 1/8] coresight-tpdm: Add CMB dataset support Date: Wed, 29 Mar 2023 01:47:37 -0700 Message-ID: <20230329084744.5705-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TnV_6cR8QRKoe7Li3qhZoMCUuh4BB-Xb X-Proofpoint-GUID: TnV_6cR8QRKoe7Li3qhZoMCUuh4BB-Xb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit can be enabled for data collection by writing 1 to the first bit of CMB_CR register. This change is to add enable/disable function for CMB dataset by writing CMB_CR register. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 30 ++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 9 ++++++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 3240bc4a8b30..d92432329c9c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -149,6 +149,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); + val |= TPDM_CMB_CR_ENA; + + /* Set the enable bit of CMB control register to 1 */ + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +} + /* TPDM enable operations */ /* The TPDM or Monitor serves as data collection component for various * dataset types. It covers Basic Counts(BC), Tenure Counts(TC), @@ -160,9 +171,11 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - /* Check if DSB datasets is present for TPDM. */ + /* Enable dataset packets */ if (drvdata->datasets & TPDM_PIDR0_DS_DSB) tpdm_enable_dsb(drvdata); + if (drvdata->datasets & TPDM_PIDR0_DS_CMB) + tpdm_enable_cmb(drvdata); CS_LOCK(drvdata->base); } @@ -196,14 +209,27 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); + val &= ~TPDM_CMB_CR_ENA; + + /* Set the enable bit of CMB control register to 0 */ + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +} + /* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - /* Check if DSB datasets is present for TPDM. */ + /* Disable dataset packet */ if (drvdata->datasets & TPDM_PIDR0_DS_DSB) tpdm_disable_dsb(drvdata); + if (drvdata->datasets & TPDM_PIDR0_DS_CMB) + tpdm_disable_cmb(drvdata); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 355a499635c2..4c065a4b8a75 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -9,6 +9,13 @@ /* The max number of the datasets that TPDM supports */ #define TPDM_DATASETS 7 +/* CMB Subunit Registers*/ +/*CMB subunit global control register*/ +#define TPDM_CMB_CR (0xA00) + +/* Enable bit for CMB subunit */ +#define TPDM_CMB_CR_ENA BIT(0) + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) @@ -65,10 +72,12 @@ * * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0 */ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) +#define TPDM_PIDR0_DS_CMB BIT(2) #define TPDM_DSB_MAX_LINES 256 /* MAX number of EDCR registers */ From patchwork Wed Mar 29 08:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64261C761A6 for ; Wed, 29 Mar 2023 08:48:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230392AbjC2IsZ (ORCPT ); Wed, 29 Mar 2023 04:48:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231234AbjC2IsX (ORCPT ); Wed, 29 Mar 2023 04:48:23 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28D21172B; Wed, 29 Mar 2023 01:48:22 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T1Co8p012346; Wed, 29 Mar 2023 08:47:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=bx8oVsuQ3IjguArMCDxtBpJ1u3h2J0XhbOIDrGFFIQU=; b=fiaM97aAFvcgiZsY/hjbIgLEGh1v6Xcjl8CjGrW+FUemyTXJKruJiqT8RGEcltQLobMq OLVo9AH4GhiK5TdicTL02JrcJZWIo74woJoQiXvYmJJtO1igAAonH8on9dl6OUjKi4yI 3boCJ1v3pysUUG6dS32kh+9yU3ghe0dks2pkdHxIDxHq+XisFxQUz6aYkSG/zByCvwcW st7X4MpXr3PBErvo/6WKhoWmc7WRlA+DzMkgWkvZis6Kx7iyS4SSOeXjYnLRcPVVNyoO +lJtPkvM8aIQY6RInSNSMxaPJPWBcJrjsAKa6QvYOpx+2qK4JHPQOksw4pUnDd52riDc dg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmawsgw0b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lvpN017485 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:57 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:56 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 2/8] coresight-tpdm: Add support to configure CMB collection mode Date: Wed, 29 Mar 2023 01:47:38 -0700 Message-ID: <20230329084744.5705-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: otC5jpbn-7XqgVTanm08PsNgyiNfu3zF X-Proofpoint-ORIG-GUID: otC5jpbn-7XqgVTanm08PsNgyiNfu3zF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 mlxlogscore=867 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org TPDM CMB subunits support two forms of CMB data set element creation: continuous and trace-on-change collection mode. Continuous change creates CMB data set elements on every CMBCLK edge. Trace-on-change creates CMB data set elements only when a new data set element differs in value from the previous element in a CMB data set. Set CMB_CR.MODE to 0 for continuous CMB collection mode. Set CMB_CR.MODE to 1 for trace-on-change CMB collection mode Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 8 ++ drivers/hwtracing/coresight/coresight-tpdm.c | 77 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 12 +++ 3 files changed, 96 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 6bdba7d375c9..89051018dd70 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -155,3 +155,11 @@ Description: Accepts the following two values. value 1: Index number of MSR register value 2: The value need to be written + +What: /sys/bus/coresight/devices//cmb_mode +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write CMB data collection mode. Only value 0 and 1 can be written to this node. + Set to 0 is for continuous CMB collection mode. Set to 1 is for trace-on-change CMB + collection mode. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d92432329c9c..68244abfc8b9 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -34,6 +34,21 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_cmb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata) { + if (drvdata->datasets & TPDM_PIDR0_DS_CMB) + return attr->mode; + } + + return 0; +} + + static int tpdm_init_datasets(struct tpdm_drvdata *drvdata) { if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { @@ -50,6 +65,15 @@ static int tpdm_init_datasets(struct tpdm_drvdata *drvdata) &drvdata->dsb->msr_num); } + if (drvdata->datasets & TPDM_PIDR0_DS_CMB) { + if (!drvdata->cmb) { + drvdata->cmb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->cmb), GFP_KERNEL); + if (!drvdata->cmb) + return -ENOMEM; + } + } + return 0; } @@ -154,9 +178,18 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) u32 val; val = readl_relaxed(drvdata->base + TPDM_CMB_CR); - val |= TPDM_CMB_CR_ENA; + /* + * Set to 0 for continuous CMB collection mode, + * 1 for trace-on-change CMB collection mode. + */ + if (drvdata->cmb->trace_mode) + val |= TPDM_CMB_CR_MODE; + else + val &= ~TPDM_CMB_CR_MODE; /* Set the enable bit of CMB control register to 1 */ + val |= TPDM_CMB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); } @@ -819,6 +852,37 @@ static ssize_t dsb_msr_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_msr); +static ssize_t cmb_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%x\n", + drvdata->cmb->trace_mode); + +} + +static ssize_t cmb_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long trace_mode; + int ret; + + ret = kstrtoul(buf, 16, &trace_mode); + if (ret || (trace_mode & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->trace_mode = trace_mode; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_mode); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -835,14 +899,25 @@ static struct attribute *tpdm_dsb_attrs[] = { NULL, }; +static struct attribute *tpdm_cmb_attrs[] = { + &dev_attr_cmb_mode.attr, + NULL, +}; + static struct attribute_group tpdm_dsb_attr_grp = { .attrs = tpdm_dsb_attrs, .is_visible = tpdm_dsb_is_visible, }; +static struct attribute_group tpdm_cmb_attr_grp = { + .attrs = tpdm_cmb_attrs, + .is_visible = tpdm_cmb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp, + &tpdm_cmb_attr_grp, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4c065a4b8a75..d716963bee10 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -15,6 +15,8 @@ /* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) +/* Trace collection mode for CMB subunit*/ +#define TPDM_CMB_CR_MODE BIT(1) /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) @@ -117,6 +119,14 @@ struct dsb_dataset { u32 *msr; }; +/* + * struct cmb_dataset + * @trace_mode: Dataset collection mode + */ +struct cmb_dataset { + u32 trace_mode; +}; + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -125,6 +135,7 @@ struct dsb_dataset { * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. + * @cmb: cmb dataset struct data. */ struct tpdm_drvdata { @@ -135,6 +146,7 @@ struct tpdm_drvdata { bool enable; unsigned long datasets; struct dsb_dataset *dsb; + struct cmb_dataset *cmb; }; #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ From patchwork Wed Mar 29 08:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 744D8C74A5B for ; Wed, 29 Mar 2023 08:48:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231255AbjC2Is2 (ORCPT ); Wed, 29 Mar 2023 04:48:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231240AbjC2IsY (ORCPT ); Wed, 29 Mar 2023 04:48:24 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CE7719AA; Wed, 29 Mar 2023 01:48:22 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T4G9Tk032383; Wed, 29 Mar 2023 08:47:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=T0RIXA94jq1FwQF0oeAsD0q59AYGX1JGeAtA947i83I=; b=nR4KBV5kD2HcQMMOd90HUR9zKShQHwADSdoW5hKo29Dts8v8Qrw/PRFbAwH5JeQEQGPg pHznXa6POsio8njFbIPEXEolVqXHssNcvA38Cq4YkqUG7KaOdbi8BnXK0Cj/dnyGp6xY t6kHRYJtxl+ALQyW+a/cd7tyhD4m1R1+0DHUUnxxTG9VqD48jaEMCnQjhnIsJo6D/5zd 04Cm8JNkVP1RppZ5YPfzgLag6FY//sVCoCY8+ZVtHA0YwMSuFtx1W6ozPxg2H6SZIYDX NDx1sdyOUtlrF9ND4eRE1Hp6jEsrvfwBl6IT5GgyBA6B+/u5tr2b1G2kSbpqy4IkksZa 9g== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmb8h0v93-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lvg6031501 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:57 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:57 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 3/8] coresight-tpdm: Add pattern registers support for CMB data set Date: Wed, 29 Mar 2023 01:47:39 -0700 Message-ID: <20230329084744.5705-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: asVZ83vdQpQAOIhT53QyukegyAd3Em1A X-Proofpoint-GUID: asVZ83vdQpQAOIhT53QyukegyAd3Em1A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Timestamps are requested if the monitor’s CMB data set unit input data matches the value in the Monitor CMB timestamp pattern and mask registers (M_CMB_TPR and M_CMB_TPMR) when CMB timestamp enabled via the timestamp insertion enable register bit(CMB_TIER.PATT_TSENAB). The pattern match trigger output is achieved via setting values into the CMB trigger pattern and mask registers (CMB_XPR and CMB_XPMR). After configuring a pattern through these registers, the TPDM subunit will assert an output trigger every time it receives new input data that matches the configured pattern value. Values in a given bit number of the mask register correspond to the same bit number in the corresponding pattern register. Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 25 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 169 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 19 ++ 3 files changed, 213 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 89051018dd70..4cc22ad5c485 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -163,3 +163,28 @@ Contact: Jinlong Mao Description: (RW) Read or write CMB data collection mode. Only value 0 and 1 can be written to this node. Set to 0 is for continuous CMB collection mode. Set to 1 is for trace-on-change CMB collection mode. + +What: /sys/bus/coresight/devices//cmb_patt_mask +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write CMB timestamp pattern mask. + +What: /sys/bus/coresight/devices//cmb_patt_val +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write CMB interface timestamp request pattern match control. + +What: /sys/bus/coresight/devices//cmb_trig_patt_mask +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write the value of CMB subunit trigger pattern mask. + +What: /sys/bus/coresight/devices//cmb_trig_patt_val +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write the value of CMB subunit trigger pattern match. + diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 68244abfc8b9..05341fa7a6b7 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -176,6 +176,19 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) { u32 val; + int i; + + /* Configure pattern registers*/ + for (i = 0; i < TPDM_CMB_MAX_PATT; i++) { + writel_relaxed(drvdata->cmb->patt_val[i], + drvdata->base + TPDM_CMB_TPR(i)); + writel_relaxed(drvdata->cmb->patt_mask[i], + drvdata->base + TPDM_CMB_TPMR(i)); + writel_relaxed(drvdata->cmb->trig_patt_val[i], + drvdata->base + TPDM_CMB_XPR(i)); + writel_relaxed(drvdata->cmb->trig_patt_mask[i], + drvdata->base + TPDM_CMB_XPMR(i)); + } val = readl_relaxed(drvdata->base + TPDM_CMB_CR); /* @@ -883,6 +896,158 @@ static ssize_t cmb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_mode); +static ssize_t cmb_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_CMB_MAX_PATT; i++) { + size += sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->cmb->patt_val[i]); + } + spin_unlock(&drvdata->spinlock); + return size; +} + +static ssize_t cmb_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_CMB_MAX_PATT) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->patt_val[index] = val; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(cmb_patt_val); + +static ssize_t cmb_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_CMB_MAX_PATT; i++) { + size += sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->cmb->patt_mask[i]); + } + spin_unlock(&drvdata->spinlock); + return size; + +} + +static ssize_t cmb_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_CMB_MAX_PATT) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->patt_mask[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_patt_mask); + +static ssize_t cmb_trig_patt_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_CMB_MAX_PATT; i++) { + size += sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->cmb->trig_patt_val[i]); + } + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t cmb_trig_patt_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_CMB_MAX_PATT) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->trig_patt_val[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_trig_patt_val); + +static ssize_t cmb_trig_patt_mask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t size = 0; + int i; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < TPDM_CMB_MAX_PATT; i++) { + size += sysfs_emit_at(buf, size, + "Index: 0x%x Value: 0x%x\n", i, + drvdata->cmb->trig_patt_mask[i]); + } + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t cmb_trig_patt_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long index, val; + + if (sscanf(buf, "%lx %lx", &index, &val) != 2) + return -EINVAL; + if (index >= TPDM_CMB_MAX_PATT) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->trig_patt_mask[index] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_trig_patt_mask); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -901,6 +1066,10 @@ static struct attribute *tpdm_dsb_attrs[] = { static struct attribute *tpdm_cmb_attrs[] = { &dev_attr_cmb_mode.attr, + &dev_attr_cmb_patt_val.attr, + &dev_attr_cmb_patt_mask.attr, + &dev_attr_cmb_trig_patt_val.attr, + &dev_attr_cmb_trig_patt_mask.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index d716963bee10..616b6df41e00 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,12 +12,23 @@ /* CMB Subunit Registers*/ /*CMB subunit global control register*/ #define TPDM_CMB_CR (0xA00) +/*CMB subunit timestamp pattern registers*/ +#define TPDM_CMB_TPR(n) (0xA08 + (n * 4)) +/*CMB subunit timestamp pattern mask registers*/ +#define TPDM_CMB_TPMR(n) (0xA10 + (n * 4)) +/*CMB subunit trigger pattern registers*/ +#define TPDM_CMB_XPR(n) (0xA18 + (n * 4)) +/*CMB subunit trigger pattern mask registers*/ +#define TPDM_CMB_XPMR(n) (0xA20 + (n * 4)) /* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) /* Trace collection mode for CMB subunit*/ #define TPDM_CMB_CR_MODE BIT(1) +/*Patten register number*/ +#define TPDM_CMB_MAX_PATT 2 + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) @@ -122,9 +133,17 @@ struct dsb_dataset { /* * struct cmb_dataset * @trace_mode: Dataset collection mode + * @patt_val: Save value for pattern + * @patt_mask: Save value for pattern mask + * @trig_patt_val: Save value for trigger pattern + * @trig_patt_mask: Save value for trigger pattern mask */ struct cmb_dataset { u32 trace_mode; + u32 patt_val[TPDM_CMB_MAX_PATT]; + u32 patt_mask[TPDM_CMB_MAX_PATT]; + u32 trig_patt_val[TPDM_CMB_MAX_PATT]; + u32 trig_patt_mask[TPDM_CMB_MAX_PATT]; }; /** From patchwork Wed Mar 29 08:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6018CC761A6 for ; Wed, 29 Mar 2023 08:48:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbjC2IsW (ORCPT ); Wed, 29 Mar 2023 04:48:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229656AbjC2IsV (ORCPT ); Wed, 29 Mar 2023 04:48:21 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68206172B; Wed, 29 Mar 2023 01:48:20 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T3Bmu5007034; Wed, 29 Mar 2023 08:47:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=45d4yhT9YEm0+LQwNA6raFnJAcjyP2ebzoinOzaHzc4=; b=lW9IeU3YQcNQJ+Dgpvrc57HoWvSbc5ZaVIXOCEoW1qh1Q5icA57wwet2QG7SmuaACd0A UPNfbL7c0HPjtLlshFBlwlbr1YZG0GSMTy3jHOVlyu93/aaPuKwAY1bxNZudNj5MzZMV t4A/QTM2Hq7dEkfelKLiNCMBzjBl/joCRngHrOM3D9wacLjIao5bKYChpuOAY78OLKDi Bqq/Jxz5e8jnWKyCXFtOW/hIEFUNOtNVrD5dc3QvlRFs9dHSC6HER7gVfSaZgJxubQa5 BL3gVQktZVXf6M8lwwhPutZlU8OAgjdrQNDgy/PBpScC0dZCq2Dz33ibWGYblzD0cYGZ xw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmd6ugmbm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lwej017497 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:57 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 4/8] coresight-tpdm: Add timestamp control register support for the CMB Date: Wed, 29 Mar 2023 01:47:40 -0700 Message-ID: <20230329084744.5705-5-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2f0jtgMG8KpiX207l28c-mQULJQYpxET X-Proofpoint-ORIG-GUID: 2f0jtgMG8KpiX207l28c-mQULJQYpxET X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 phishscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org CMB_TIER register is CMB subunit timestamp insertion enable register. Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB CTI timestamp request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp for all packets. Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 24 ++++ drivers/hwtracing/coresight/coresight-tpdm.c | 114 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++ 3 files changed, 152 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 4cc22ad5c485..aa357f463d03 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -188,3 +188,27 @@ KernelVersion 6.3 Contact: Jinlong Mao Description: (RW) Read or write the value of CMB subunit trigger pattern match. +What: /sys/bus/coresight/devices//cmb_patt_ts +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write status of timestamp upon CMB interface pattern match. + Only value 0 and 1 can be written to this node. Set this node to 1 to + request a timestamp following a CMB interface pattern match. + +What: /sys/bus/coresight/devices//cmb_trig_ts +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write the status of timestamp upon CMB cross trigger interface. + Only value 0 and 1 can be written to this node. Set this node to 1 to + request a timestamp following a CMB CTI timestamp request. + +What: /sys/bus/coresight/devices//cmb_ts_all +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write the status of timestamp upon all interface. + Only value 0 and 1 can be written to this node. Set this node to 1 to requeset + timestamp to all trace packet. + diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 05341fa7a6b7..88bb740cddd6 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -190,6 +190,22 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) drvdata->base + TPDM_CMB_XPMR(i)); } + /* Configure timestamp control register. */ + val = readl_relaxed(drvdata->base + TPDM_CMB_TIER); + if (drvdata->cmb->patt_ts) + val = val | TPDM_CMB_TIER_PATT_TSENAB; + else + val = val & ~TPDM_CMB_TIER_PATT_TSENAB; + if (drvdata->cmb->trig_ts) + val = val | TPDM_CMB_TIER_XTRIG_TSENAB; + else + val = val & ~TPDM_CMB_TIER_XTRIG_TSENAB; + if (drvdata->cmb->ts_all) + val = val | TPDM_CMB_TIER_TS_ALL; + else + val = val & ~TPDM_CMB_TIER_TS_ALL; + writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); /* * Set to 0 for continuous CMB collection mode, @@ -1048,6 +1064,101 @@ static ssize_t cmb_trig_patt_mask_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_trig_patt_mask); +static ssize_t cmb_patt_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + + return scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)drvdata->cmb->patt_ts); +} + +static ssize_t cmb_patt_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 16, &val) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->cmb->patt_ts = true; + else + drvdata->cmb->patt_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_patt_ts); + +static ssize_t cmb_ts_all_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + + return scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)drvdata->cmb->ts_all); +} + +static ssize_t cmb_ts_all_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 16, &val) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->cmb->ts_all = true; + else + drvdata->cmb->ts_all = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_ts_all); + +static ssize_t cmb_trig_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)drvdata->cmb->trig_ts); +} + +static ssize_t cmb_trig_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 16, &val) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->cmb->trig_ts = true; + else + drvdata->cmb->trig_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_trig_ts); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -1070,6 +1181,9 @@ static struct attribute *tpdm_cmb_attrs[] = { &dev_attr_cmb_patt_mask.attr, &dev_attr_cmb_trig_patt_val.attr, &dev_attr_cmb_trig_patt_mask.attr, + &dev_attr_cmb_patt_ts.attr, + &dev_attr_cmb_ts_all.attr, + &dev_attr_cmb_trig_ts.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 616b6df41e00..88ade2f2ef6c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* CMB Subunit Registers*/ /*CMB subunit global control register*/ #define TPDM_CMB_CR (0xA00) +/*CMB subunit timestamp insertion enable register*/ +#define TPDM_CMB_TIER (0xA04) /*CMB subunit timestamp pattern registers*/ #define TPDM_CMB_TPR(n) (0xA08 + (n * 4)) /*CMB subunit timestamp pattern mask registers*/ @@ -25,6 +27,12 @@ #define TPDM_CMB_CR_ENA BIT(0) /* Trace collection mode for CMB subunit*/ #define TPDM_CMB_CR_MODE BIT(1) +/* Timestamp control for pattern match */ +#define TPDM_CMB_TIER_PATT_TSENAB BIT(0) +/* CMB CTI timestamp request */ +#define TPDM_CMB_TIER_XTRIG_TSENAB BIT(1) +/* For timestamp fo all trace*/ +#define TPDM_CMB_TIER_TS_ALL BIT(2) /*Patten register number*/ #define TPDM_CMB_MAX_PATT 2 @@ -137,6 +145,9 @@ struct dsb_dataset { * @patt_mask: Save value for pattern mask * @trig_patt_val: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @patt_ts: Indicates if pattern match for timestamp is enabled. + * @trig_ts: Indicates if CTI trigger for timestamp is enabled. + * @ts_all: Indicates if timestamp is enabled for all packets. */ struct cmb_dataset { u32 trace_mode; @@ -144,6 +155,9 @@ struct cmb_dataset { u32 patt_mask[TPDM_CMB_MAX_PATT]; u32 trig_patt_val[TPDM_CMB_MAX_PATT]; u32 trig_patt_mask[TPDM_CMB_MAX_PATT]; + bool patt_ts; + bool trig_ts; + bool ts_all; }; /** From patchwork Wed Mar 29 08:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE3D2C6FD18 for ; Wed, 29 Mar 2023 08:48:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231258AbjC2Isz (ORCPT ); Wed, 29 Mar 2023 04:48:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231285AbjC2Isi (ORCPT ); Wed, 29 Mar 2023 04:48:38 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E02640E8; Wed, 29 Mar 2023 01:48:30 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T7OvXW002401; Wed, 29 Mar 2023 08:48:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=FT8jIE6CqAkWKSPy/13QapZZX7btBX1ZdzJlOq5x9C4=; b=NRmFTIMxbOKgnNMBWKlGJj0RO9Ff57cPMLJRMIG1mu2MWVj5KHinvzHA4NyWGyya/1wA 0jg2tPMsZJt97z9FtRe4a3+p2AXoJqmvBMI26f4c3cDWATH1vqP8g4F2SG72EUBxEBdJ jQuEpHA4fnofR8XIDLGV3CqLZMOqvsiejYGkKwwVRrHkVipL2vt8EXGq6q/A2cco0Um8 KodNQ3k23wC9RCgBGedBTAVosVyTzTfcL2yTSXzH+sO+v2FQJ+Sv/S4l7gB28HsJt9yA kALhujRCVVxREpoKHVaWvM36aArozFjSSM5pkoZ7yD4lgOhnSSkRcL23mIfUYvGKbIbf rQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pkv45k929-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lwJa031753 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:57 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 5/8] coresight-tpdm: Add msr register support for CMB Date: Wed, 29 Mar 2023 01:47:41 -0700 Message-ID: <20230329084744.5705-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5tWVQbd9LbMdwNEIrnME1Nqj7ty9YYci X-Proofpoint-ORIG-GUID: 5tWVQbd9LbMdwNEIrnME1Nqj7ty9YYci X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the nodes for CMB subunit MSR(mux select register) support. CMB MSRs(mux select registers) is to separate mux,arbitration, ,interleaving,data packing control from stream filtering control. Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ drivers/hwtracing/coresight/coresight-tpdm.c | 59 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 6 ++ 3 files changed, 71 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index aa357f463d03..403c45fcdcfe 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -212,3 +212,9 @@ Description: (RW) Read or write the status of timestamp upon all interface. Only value 0 and 1 can be written to this node. Set this node to 1 to requeset timestamp to all trace packet. +What: /sys/bus/coresight/devices//cmb_msr +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao +Description: (RW) Read or write the value of CMB msr. + diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 88bb740cddd6..91b9ec80bf23 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -72,6 +72,14 @@ static int tpdm_init_datasets(struct tpdm_drvdata *drvdata) if (!drvdata->cmb) return -ENOMEM; } + + /* Get cmb msr number*/ + of_property_read_u32(drvdata->dev->of_node, "qcom,cmb-msr-num", + &drvdata->cmb->msr_num); + drvdata->cmb->msr = devm_kzalloc(drvdata->dev, + (drvdata->cmb->msr_num * sizeof(u32)), GFP_KERNEL); + if (!drvdata->cmb->msr) + return -ENOMEM; } return 0; @@ -206,6 +214,12 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) val = val & ~TPDM_CMB_TIER_TS_ALL; writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); + /* Configure MSR registers */ + if (drvdata->cmb->msr_num != 0) + for (i = 0; i < drvdata->cmb->msr_num; i++) + writel_relaxed(drvdata->cmb->msr[i], + drvdata->base + TPDM_CMB_MSR(i)); + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); /* * Set to 0 for continuous CMB collection mode, @@ -1159,6 +1173,50 @@ static ssize_t cmb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_trig_ts); +static ssize_t cmb_msr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned int i; + ssize_t size = 0; + + if (drvdata->cmb->msr_num == 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + for (i = 0; i < drvdata->cmb->msr_num; i++) { + size += sysfs_emit_at(buf, size, + "%u 0x%x\n", i, drvdata->cmb->msr[i]); + } + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t cmb_msr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned int num, val; + int nval; + + if (drvdata->cmb->msr_num == 0) + return -EINVAL; + + nval = sscanf(buf, "%u %x", &num, &val); + if ((nval != 2) || (num >= (drvdata->cmb->msr_num - 1))) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->msr[num] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_msr); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -1184,6 +1242,7 @@ static struct attribute *tpdm_cmb_attrs[] = { &dev_attr_cmb_patt_ts.attr, &dev_attr_cmb_ts_all.attr, &dev_attr_cmb_trig_ts.attr, + &dev_attr_cmb_msr.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 88ade2f2ef6c..d783fc94252b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -22,6 +22,8 @@ #define TPDM_CMB_XPR(n) (0xA18 + (n * 4)) /*CMB subunit trigger pattern mask registers*/ #define TPDM_CMB_XPMR(n) (0xA20 + (n * 4)) +/* CMB MSR register */ +#define TPDM_CMB_MSR(n) (0xA80 + (n * 4)) /* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) @@ -145,6 +147,8 @@ struct dsb_dataset { * @patt_mask: Save value for pattern mask * @trig_patt_val: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @msr_num: The number of msr register + * @msr: Save value for msr registers * @patt_ts: Indicates if pattern match for timestamp is enabled. * @trig_ts: Indicates if CTI trigger for timestamp is enabled. * @ts_all: Indicates if timestamp is enabled for all packets. @@ -155,6 +159,8 @@ struct cmb_dataset { u32 patt_mask[TPDM_CMB_MAX_PATT]; u32 trig_patt_val[TPDM_CMB_MAX_PATT]; u32 trig_patt_mask[TPDM_CMB_MAX_PATT]; + u32 msr_num; + u32 *msr; bool patt_ts; bool trig_ts; bool ts_all; From patchwork Wed Mar 29 08:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E0DEC77B6F for ; Wed, 29 Mar 2023 08:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjC2IsY (ORCPT ); Wed, 29 Mar 2023 04:48:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231194AbjC2IsW (ORCPT ); Wed, 29 Mar 2023 04:48:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 985C31721; Wed, 29 Mar 2023 01:48:21 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T8XJud030690; Wed, 29 Mar 2023 08:47:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=k9Zd+poeSAflCAm6BhMQn4MEZzgfoY/iIo3aPnSnmIs=; b=pVCB/fpBxCXIqJqhxmmZDwyeCUIE8UDx+VJSQ5512bpoyHMxxnRUDrKbHwJrwSUSVVfx uhzS7WQUiO+Ezlxpn7hSnONyuvrS/6roJCovs5jEubmh9rOaLa8EQz/zBFeXkf7SqhVM rXkQ1EP2+NFrZ0De2DIYbmJxG/tnQ15qwGBbsXP19Wb5larpXVVfeCW0DHyVngpG/f0f ikk8Abapg5GxX+O1VenxCpAE+XdASqsYp8HETmHyVSyu1HgE3JxZOrSBG/uxpvCANCrw Fm9cUs7WwLvoXgUYN3746fYe/C6dndKxdZadbUXFLIk31aUr2x+6pV0V4CfqKc8sh6HI 6A== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmawsgw0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lwTo009168 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 6/8] dt-bindings: arm: Add support for TPDM CMB MSR register Date: Wed, 29 Mar 2023 01:47:42 -0700 Message-ID: <20230329084744.5705-7-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y-wAyoBk0j0UeFbxH7lhCOezIDlnpzmA X-Proofpoint-ORIG-GUID: y-wAyoBk0j0UeFbxH7lhCOezIDlnpzmA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 mlxlogscore=970 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) for TPDM. It specifies the number of CMB MSR registers supported by the TDPM. Signed-off-by: Mao Jinlong Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 691c7ba365aa..283dfb39d46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -62,6 +62,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msr-num: + description: + Specifies the number of CMB MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 128 + clocks: maxItems: 1 @@ -97,6 +106,7 @@ examples: qcom,dsb-element-size = <32>; qcom,dsb_msr_num = <16>; + qcom,cmb-msr-num = <6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From patchwork Wed Mar 29 08:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4663DC77B6C for ; Wed, 29 Mar 2023 08:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231230AbjC2IsX (ORCPT ); Wed, 29 Mar 2023 04:48:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230489AbjC2IsV (ORCPT ); Wed, 29 Mar 2023 04:48:21 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51E9A1721; Wed, 29 Mar 2023 01:48:20 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T6Bnqx030838; Wed, 29 Mar 2023 08:48:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Hizfx70K2+XOLPTpvFYRBuhNI+gaFxVSY3aWlzR3sd0=; b=kCRIwlwsDOjMe4lnB+iIKZ+FNdl4xaRUSrzarvC8mVpoODUTrMWK+I/HFBmI2IzWxMnP zC0uC5BzuvRdccKa4pWcgQAIIBeAg2ZmvdYmm9kqx2VxwhF3tFXb3WbhISmJI9ZLoeOI 6uzJhXnyKJTKDEuL584WuoMv07r/jaWoseLEnqC9GrVyHgDEW2sbwlU5dK8LZ0SEk/sO WZA9JYBssGsa/2bJNqcZmTXJNVPIf82MtzC6WFJKxpXdlKlGslPvJ7E+/cvCPtTFshsP yqNWdsuFwpuZDoDpMGpGNuLoakbKyuqjiaXFUF3A0I2aCfm+jsBFIL4qT2kAI54vQNcI ow== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pm6k81d3x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lxLf031756 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 7/8] coresight-tpda: Add support to configure CMB element size Date: Wed, 29 Mar 2023 01:47:43 -0700 Message-ID: <20230329084744.5705-8-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TsQUo688sPHWPk05tQhkPEbxFpcM8DZ_ X-Proofpoint-GUID: TsQUo688sPHWPk05tQhkPEbxFpcM8DZ_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=911 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Read the CMB element size from the device tree. Set the register bit that controls the CMB element size of the corresponding port. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpda.c | 33 +++++++++++++++++--- drivers/hwtracing/coresight/coresight-tpda.h | 4 +++ 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index a620a51e861a..c2ce62e769ea 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -42,11 +42,12 @@ static int tpda_set_element_size(struct tpda_drvdata *drvdata, continue; } if (in_csdev && strstr(dev_name(&in_csdev->dev), "tpdm")) { - if (!of_property_read_u32(in_csdev->dev.parent->of_node, - "qcom,dsb-elemenet-size", &drvdata->dsb_esize[nr_inport])) - break; - dev_err(drvdata->dev, "Fail to get data set element size\n"); - return -EINVAL; + of_property_read_u32(in_csdev->dev.parent->of_node, + "qcom,dsb-elemenet-size", &drvdata->dsb_esize[nr_inport]); + of_property_read_u8(in_csdev->dev.parent->of_node, + "qcom,cmb-elemenet-size", &drvdata->cmb_esize[nr_inport]); + + break; } tpda_set_element_size(drvdata, in_csdev, 0); } @@ -82,6 +83,28 @@ static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) else dev_err(drvdata->dev, "DSB data size input from port[%d] is invalid\n", port); + + /* + * Configure aggregator port n CMB data set element size + * Set the bit to 0 if the size is 8 + * Set the bit to 1 if the size is 32 + * Set the bit to 1 if the size is 64 + */ + if (drvdata->cmb_esize[port] == 8) + val &= ~TPDA_Pn_CR_CMBSIZE; + else if (drvdata->cmb_esize[port] == 32) + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); + else if (drvdata->cmb_esize[port] == 32) + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2); + else { + /* + * CMB element size is not configured. + * Fall back to 32-bit. + */ + WARN_ON_ONCE(1); + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); + } + /* Enable the port */ val |= TPDA_Pn_CR_ENA; writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 9ec5870b5f7c..d5290d21457d 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -12,6 +12,8 @@ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) +/* Aggregator port CMB data set element size bit */ +#define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) #define TPDA_MAX_INPORTS 32 @@ -26,6 +28,7 @@ * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @dsb_esize: DSB element size + * @cmb_esize: CMB element size. Must be 8, 32 or 64. */ struct tpda_drvdata { void __iomem *base; @@ -34,6 +37,7 @@ struct tpda_drvdata { spinlock_t spinlock; u8 atid; u32 dsb_esize[TPDA_MAX_INPORTS]; + u8 cmb_esize[TPDA_MAX_INPORTS]; }; #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ From patchwork Wed Mar 29 08:47:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13192115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88193C77B6C for ; Wed, 29 Mar 2023 08:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231319AbjC2ItB (ORCPT ); Wed, 29 Mar 2023 04:49:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230371AbjC2Ish (ORCPT ); Wed, 29 Mar 2023 04:48:37 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E5843C3B; Wed, 29 Mar 2023 01:48:29 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32SNpbU7008579; Wed, 29 Mar 2023 08:48:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=OFlfjRYANz+Cqp4MQubmPGGlSaQQl2KTHyWywJDQfNU=; b=McijSEUeV0lrgmWH7bXMe7go7pauLFxxbnmHYFKuJOeSkjcOMqyUxIzGiBhuZdr8yHdz s0IGrkVGQTGE2+R4Zhu3ZO1v2cfv56BsdxFeQv/NzxqskIccf5eT4iFleEvN6c7TfVnJ ZNI2PBIcSjU/erB6Hluvmc5wenVEpCESqYH+dJtNgsa6WgqKzvXi/lvdBGFuBsYOwhEO PqzLf7pwgFWVxrKaS6EQNhkZJ7NnWPJbuUql3YI8Q/d1ijAgbCvG7Chhot6gLSQn1GJS tkkY8d3M4pU2x/D6IVJ7CaCp/YKGAFxFGPUTnrvvQRQjZCpTnDBdO5wExvBYc64CRuG+ 2Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pky0xavuh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:48:00 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lxwR023421 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 8/8] dt-bindings: arm: Add support for TPDM CMB element size Date: Wed, 29 Mar 2023 01:47:44 -0700 Message-ID: <20230329084744.5705-9-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GLsgeYYQQ4AB4XtBOcZqp0R4KauqzKhs X-Proofpoint-ORIG-GUID: GLsgeYYQQ4AB4XtBOcZqp0R4KauqzKhs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=831 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add property "qcom,cmb-elem-size" to support CMB element for TPDM. The associated aggregator will read this size before it is enabled. CMB element size currently only supports 8-bit, 32-bit and 64-bit. Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-tpdm.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 283dfb39d46f..c5169de81e58 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -53,6 +53,14 @@ properties: minimum: 32 maximum: 64 + qcom,cmb-element-size: + description: + Specifies the CMB (Continuous multi-bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently supports 8-bit, 32-bit, 64-bit. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 32, 64] + qcom,dsb_msr_num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -95,6 +103,12 @@ required: - clocks - clock-names +anyOf: + - required: + - qcom,dsb_msr_num + - required: + - qcom,cmb-msr-num + additionalProperties: false examples: @@ -105,6 +119,8 @@ examples: reg = <0x0684c000 0x1000>; qcom,dsb-element-size = <32>; + qcom,cmb-element-size = <32>; + qcom,dsb_msr_num = <16>; qcom,cmb-msr-num = <6>;