From patchwork Wed Mar 29 15:39:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Marussi X-Patchwork-Id: 13192711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB163C74A5B for ; Wed, 29 Mar 2023 15:40:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OFfhajmU7hWgTaCxhQ5J3n4ja+7cUj8cdBeghUOOydk=; b=zAj+ahhR2mbZJg jqinnCEXeOSWIOCsw+npfDc7KgIZu7Y933Gd396z7Dmrrc3hKFdQdxFhK73BTYT9UFeytpB9Nmx3f jZqD0xquGbomCJ9CHfISv09fmVKXtM2akKQu7YmpleAzJc4FYrvCSEEVi6gmjX7vNZVlmq+31X9mx fcGlK1VZZl1l7uDmtp5rG6hUkGXBffL1iZI+0YV69boE4LRL56ufds9743x37ebFSKdLtgEoHF7ew My3/P6UzYirMo1YmxZlGNztVW0Kcs6vwhj1BSQHsh7uVd6teuQHUd463zEEG24cybCttyzwBfo29L vaSjODkGym5eRd8N+g2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXuB-000pMD-17; Wed, 29 Mar 2023 15:40:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXty-000pJB-2L for linux-arm-kernel@lists.infradead.org; Wed, 29 Mar 2023 15:39:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C699C2F4; Wed, 29 Mar 2023 08:40:36 -0700 (PDT) Received: from e120937-lin.. (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDE033F663; Wed, 29 Mar 2023 08:39:50 -0700 (PDT) From: Cristian Marussi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, vincent.guittot@linaro.org, souvik.chakravarty@arm.com, nicola.mazzucato@arm.com, Tushar.Khandelwal@arm.com, viresh.kumar@linaro.org, jassisinghbrar@gmail.com, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: mailbox : arm,mhuv2: Allow for more RX interrupts Date: Wed, 29 Mar 2023 16:39:35 +0100 Message-Id: <20230329153936.394911-2-cristian.marussi@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230329153936.394911-1-cristian.marussi@arm.com> References: <20230329153936.394911-1-cristian.marussi@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_083954_830015_2AD5CF25 X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ARM MHUv2 Receiver block can indeed support more interrupts, up to the maximum number of available channels, but anyway no more than the maximum number of supported interrupt for an AMBA device. Signed-off-by: Cristian Marussi --- Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org .../devicetree/bindings/mailbox/arm,mhuv2.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml index a4f1fe63659a..5a57f4e2a623 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml @@ -69,10 +69,15 @@ properties: interrupts: description: | - The MHUv2 controller always implements an interrupt in the "receiver" - mode, while the interrupt in the "sender" mode was not available in the - version MHUv2.0, but the later versions do have it. - maxItems: 1 + The MHUv2 controller always implements at least an interrupt in the + "receiver" mode, while the interrupt in the "sender" mode was not + available in the version MHUv2.0, but the later versions do have it. + In "receiver" mode, beside a single combined interrupt, there could be + multiple interrupts, up to the number of implemented channels but anyway + no more than the maximum number of interrupts potentially supported by + AMBA. + minItems: 1 + maxItems: 9 clocks: maxItems: 1 From patchwork Wed Mar 29 15:39:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Marussi X-Patchwork-Id: 13192710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20A50C74A5B for ; Wed, 29 Mar 2023 15:40:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vs+/lTzxaGaUgOPjsQDmOpFfTQ0VJC8cjVs/XfJWpI8=; b=jJO2D+H9YpF0qK UQ1v2DIrPqxTDWb6oiDCQsVtiaaAKizCh8HJzVB2L1Il6dPPO8U9k0Mn6b1xJr83vOkkaX1gpiKJV 7HaAqKsD8DtIzDPT4WLv37XKeKeyn6OR+PlgacoRt9Ho19VVEA9thethp+uKUyqWUEgNPpNLeDw+V x9MZScTArdqdb2CLWoh+Z9GNoWMeGDl54rxhWYpRipoedn8oHG1Mylfp1PbHto6OyOFqxn++ELa8T PTiExljRz/rJXVc5ItPhJzGYD7x/lmrF+Wyb8rAcilgXYvovbwQFKwgitznLzUJihumjz/MLqNH3T NndvdILwMeClfwEFMQaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXuC-000pMo-1S; Wed, 29 Mar 2023 15:40:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXtz-000pJt-2s for linux-arm-kernel@lists.infradead.org; Wed, 29 Mar 2023 15:39:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7023E1570; Wed, 29 Mar 2023 08:40:38 -0700 (PDT) Received: from e120937-lin.. (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC0D03F663; Wed, 29 Mar 2023 08:39:52 -0700 (PDT) From: Cristian Marussi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, vincent.guittot@linaro.org, souvik.chakravarty@arm.com, nicola.mazzucato@arm.com, Tushar.Khandelwal@arm.com, viresh.kumar@linaro.org, jassisinghbrar@gmail.com Subject: [PATCH 2/2] mailbox: arm_mhuv2: Add support for multiple rx interrupt Date: Wed, 29 Mar 2023 16:39:36 +0100 Message-Id: <20230329153936.394911-3-cristian.marussi@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230329153936.394911-1-cristian.marussi@arm.com> References: <20230329153936.394911-1-cristian.marussi@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_083955_981018_1E14BC10 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ARM MHUv2 can be configured to receive multiple interrupt related to the receiver block, up to the maximum number of available channels, and not necessarily grouped into a single combined interrupt. Allow to register more interrupt for the RX block up to the maximum number of interrupts supported by an AMBA device. Signed-off-by: Cristian Marussi --- drivers/mailbox/arm_mhuv2.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c index c6d4957c4da8..89060bee1fb0 100644 --- a/drivers/mailbox/arm_mhuv2.c +++ b/drivers/mailbox/arm_mhuv2.c @@ -163,7 +163,6 @@ enum mhuv2_frame { * @send: Base address of the register mapping region. * @recv: Base address of the register mapping region. * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME. - * @irq: Interrupt. * @windows: Channel windows implemented by the platform. * @minor: Minor version of the controller. * @length: Length of the protocols array in bytes. @@ -178,7 +177,6 @@ struct mhuv2 { struct mhu2_recv_frame_reg __iomem *recv; }; enum mhuv2_frame frame; - unsigned int irq; unsigned int windows; unsigned int minor; unsigned int length; @@ -991,7 +989,6 @@ static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu, } else { mhu->mbox.txdone_irq = true; mhu->mbox.txdone_poll = false; - mhu->irq = adev->irq[0]; writel_relaxed_bitfield(1, &mhu->send->int_en, struct int_en_t, chcomb); @@ -1029,18 +1026,23 @@ static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu, mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, struct mhu_cfg_t, num_ch); mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, struct aidr_t, arch_minor_rev); - mhu->irq = adev->irq[0]; - if (!mhu->irq) { - dev_err(dev, "Missing receiver IRQ\n"); - return -EINVAL; - } + for (i = 0; i < min_t(unsigned int, mhu->windows, AMBA_NR_IRQS); i++) { + if (!adev->irq[i]) { + /* At least one receiver IRQ is needed */ + if (i == 0) { + dev_err(dev, "Missing receiver IRQ\n"); + return -EINVAL; + } + continue; + } - ret = devm_request_threaded_irq(dev, mhu->irq, NULL, - mhuv2_receiver_interrupt, IRQF_ONESHOT, - "mhuv2-rx", mhu); - if (ret) { - dev_err(dev, "Failed to request rx IRQ\n"); - return ret; + ret = devm_request_threaded_irq(dev, adev->irq[i], NULL, + mhuv2_receiver_interrupt, IRQF_ONESHOT, + "mhuv2-rx", mhu); + if (ret) { + dev_err(dev, "Failed to request rx IRQ\n"); + return ret; + } } /* Mask all the channel windows */