From patchwork Wed Mar 29 23:18:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13193298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97E98C761A6 for ; Wed, 29 Mar 2023 23:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230139AbjC2XTh (ORCPT ); Wed, 29 Mar 2023 19:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230419AbjC2XTc (ORCPT ); Wed, 29 Mar 2023 19:19:32 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66D5A55A8 for ; Wed, 29 Mar 2023 16:19:31 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32TL1aRR029711; Wed, 29 Mar 2023 23:19:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=EPS8WVCNA4Hq2My0AKL1dW1ePYQOxGns1QFO2kAGooU=; b=mYAvBSHBQI/ZP5DgjQ0GNEmKKSsHFAdesLUGxG7P1zfOWKTmLUJQt4orVjofsuoWbd2J DIFx/sDLd8b1jsseVvr8nRrAVoRyUl+gLzRZWp4Y8zAgnl19YOxJAZFxqeSP5jG8lnmn z3VP9+tRBE+Crohkk1+BNKQwKve2ietJgdGMpliIU/vK2LWgWNEJ7LFZppWT+o02JsuS 8H0+sIjaBv75U7kBxvWDc+uW1UYx4anJ0Ko9trLCHTjcwMwGBFoB5ttO/IWg+vEFNMVI 6a21IpFLExaeIlGZnJpsg/0JEzLRz9WX58rSmduTiqZnrIUgOo3PAz/BsoTA+TdAwDI8 Rg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmgpm2c5n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 23:19:25 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32TNJOhl001691 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 23:19:24 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 29 Mar 2023 16:19:23 -0700 From: Jessica Zhang Date: Wed, 29 Mar 2023 16:18:46 -0700 Subject: [PATCH RFC 1/5] drm/display/dsc: Add flatness and initial scale value calculations MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v1-1-f3e479f59b6d@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680131963; l=1136; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=SmUlHFX48mj90cfuauXTJhBCrZPlPdKdTIQ5CrqNEnM=; b=WVhQT4/v4oGBVZjjdTmUcWoniU+tN/8nznzTS5hRi2BElh6elqLXQgBwDZtter1pC8VUedQug ZlAf2nIpdfOAIdNL0FIICf7L7TNoUNHudP5+hkUDhwuX3HRX6PLgByr X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: b6e1NcaQONXW9piBgZBal-W0jf1XVnJS X-Proofpoint-ORIG-GUID: b6e1NcaQONXW9piBgZBal-W0jf1XVnJS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_14,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290174 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add helpers to calculate det_thresh_flatness and initial_scale_value as these calculations are defined within the DSC spec. Signed-off-by: Jessica Zhang --- include/drm/display/drm_dsc_helper.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 4448c482b092..63175650a45e 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -17,6 +17,16 @@ enum drm_dsc_params_kind { DRM_DSC_1_2_420, }; +static inline int drm_dsc_calculate_initial_scale_value(struct drm_dsc_config *dsc) +{ + return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset); +} + +static inline int drm_dsc_calculate_det_thresh_flatness(struct drm_dsc_config *dsc) +{ + return 2 << (dsc->bits_per_component - 8); +} + void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, From patchwork Wed Mar 29 23:18:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13193301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FEB0C74A5B for ; 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Wed, 29 Mar 2023 16:19:24 -0700 From: Jessica Zhang Date: Wed, 29 Mar 2023 16:18:47 -0700 Subject: [PATCH RFC 2/5] drm/msm: Add MSM-specific DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v1-2-f3e479f59b6d@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680131963; l=4509; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=F7DeXx14VaJNxs0fW4oVoxv7B5m8Awn++2HoKAaMagA=; b=1xxeNYDEYrvFd4ADKbDA91VsrkIw0ApkUG59spQt28qP1tV3ogeaLMI09FPzegzo2MYGWOkNu nCUZtR3hN/NCFwwnQLkLuWsW7S5rLS4BefS48PRlVGzZRcUZHaftbNK X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _keyx5imFAkjea-UAoWoLx6kFk1j2hMD X-Proofpoint-ORIG-GUID: _keyx5imFAkjea-UAoWoLx6kFk1j2hMD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_14,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=614 adultscore=0 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290174 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/msm_dsc_helper.c | 74 +++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/msm_dsc_helper.h | 28 ++++++++++++ 3 files changed, 103 insertions(+) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7274c41228ed..897a5b1c88f6 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -90,6 +90,7 @@ msm-y += \ disp/mdp_kms.o \ disp/msm_disp_snapshot.o \ disp/msm_disp_snapshot_util.o \ + disp/msm_dsc_helper.o \ msm_atomic.o \ msm_atomic_tracepoints.o \ msm_debugfs.o \ diff --git a/drivers/gpu/drm/msm/disp/msm_dsc_helper.c b/drivers/gpu/drm/msm/disp/msm_dsc_helper.c new file mode 100644 index 000000000000..ec15c0d829e8 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/msm_dsc_helper.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#include +#include +#include + +#include "msm_drv.h" +#include "msm_dsc_helper.h" + +static int get_comp_ratio(struct drm_dsc_config *dsc, u32 src_bpp) +{ + return mult_frac(100, src_bpp, DSC_BPP(*dsc)); +} + +static s64 get_bytes_per_soft_slice(struct drm_dsc_config *dsc, int intf_width, int comp_ratio) +{ + s64 comp_ratio_fp, num_bits_fp; + s64 numerator_fp, denominator_fp; + + comp_ratio_fp = drm_fixp_from_fraction(comp_ratio, 100); + num_bits_fp = drm_fixp_from_fraction(8, 1); + + numerator_fp = drm_fixp_from_fraction(dsc->slice_width * dsc->bits_per_component * 3, 1); + denominator_fp = drm_fixp_mul(comp_ratio_fp, num_bits_fp); + + return drm_fixp_div(numerator_fp, denominator_fp); +} + +u32 msm_dsc_get_eol_byte_num(struct drm_dsc_config *dsc, int intf_width, u32 src_bpp) +{ + u32 bytes_per_ss, extra_eol_bytes, bytes_per_intf; + s64 bytes_per_ss_fp; + int slice_per_intf = msm_dsc_get_slice_per_intf(dsc, intf_width); + int comp_ratio = get_comp_ratio(dsc, src_bpp); + + bytes_per_ss_fp = get_bytes_per_soft_slice(dsc, intf_width, comp_ratio); + bytes_per_ss = drm_fixp2int_ceil(bytes_per_ss_fp); + + bytes_per_intf = bytes_per_ss * slice_per_intf; + extra_eol_bytes = bytes_per_intf % 3; + if (extra_eol_bytes != 0) + extra_eol_bytes = 3 - extra_eol_bytes; + + return extra_eol_bytes; +} + +u32 msm_dsc_get_dce_bytes_per_line(struct drm_dsc_config *dsc, int intf_width) +{ + u32 bpp; + u32 dce_bytes_per_line; + + bpp = DSC_BPP(*dsc); + dce_bytes_per_line = DIV_ROUND_UP(dsc->bits_per_pixel * intf_width, 8); + + return dce_bytes_per_line; +} + +int msm_dsc_get_pclk_per_line(struct drm_dsc_config *dsc, int intf_width, u32 src_bpp) +{ + s64 data_width; + int comp_ratio = get_comp_ratio(dsc, src_bpp); + + if (!dsc->slice_width || (intf_width < dsc->slice_width)) + return -EINVAL; + + data_width = get_bytes_per_soft_slice(dsc, intf_width, comp_ratio); + data_width = drm_fixp_mul(dsc->slice_count, data_width); + data_width = drm_fixp_from_fraction(data_width, 3); + + return drm_fixp2int_ceil(data_width); +} diff --git a/drivers/gpu/drm/msm/disp/msm_dsc_helper.h b/drivers/gpu/drm/msm/disp/msm_dsc_helper.h new file mode 100644 index 000000000000..308069b2b5a4 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/msm_dsc_helper.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#ifndef MSM_DSC_HELPER_H_ +#define MSM_DSC_HELPER_H_ + +#include +#include + +/* + * Helper methods for MSM specific DSC calculations that are common between timing engine, + * DSI, and DP. + */ + +#define MSM_DSC_SLICE_PER_PKT 1 +#define DSC_BPP(config) ((config).bits_per_pixel >> 4) + +static inline int msm_dsc_get_slice_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(intf_width, dsc->slice_width); +} + +u32 msm_dsc_get_eol_byte_num(struct drm_dsc_config *dsc, int intf_width, u32 src_bpp); +u32 msm_dsc_get_dce_bytes_per_line(struct drm_dsc_config *dsc, int intf_width); +int msm_dsc_get_pclk_per_line(struct drm_dsc_config *dsc, int intf_width, u32 src_bpp); +#endif /* MSM_DSC_HELPER_H_ */ From patchwork Wed Mar 29 23:18:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13193300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BF6CC6FD18 for ; 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Wed, 29 Mar 2023 16:19:24 -0700 From: Jessica Zhang Date: Wed, 29 Mar 2023 16:18:48 -0700 Subject: [PATCH RFC 3/5] drm/msm/dpu: Use DRM DSC helper for det_thresh_flatness MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v1-3-f3e479f59b6d@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680131963; l=1014; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=PeUoqn42vHHdMQ4PdFlqVoAL//N1PJ2g2Ngm2c7IwqU=; b=4ikp2F0tuBHGBDCCE4WpMa/QewYQxs4HSFMd4LfWNHNYAhpvs/C7StH5A3DOrXQARiG7VbW5l kvQLtSFmqEPDpwIKiCO2+ohY2KASmILRw/FugXWkGT9kKAVUWXg6Fbp X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZoHVAIBHemoL8ciigkc2jTpS3nbB-zpF X-Proofpoint-ORIG-GUID: ZoHVAIBHemoL8ciigkc2jTpS3nbB-zpF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_14,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=613 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290174 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 619926da1441..648c530b5d05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -3,6 +3,8 @@ * Copyright (c) 2020-2022, Linaro Limited */ +#include + #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" @@ -102,7 +104,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, data |= dsc->final_offset; DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); - det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8); + det_thresh_flatness = drm_dsc_calculate_det_thresh_flatness(dsc); data = det_thresh_flatness << 10; data |= dsc->flatness_max_qp << 5; data |= dsc->flatness_min_qp; From patchwork Wed Mar 29 23:18:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13193297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7F03C74A5B for ; Wed, 29 Mar 2023 23:19:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229650AbjC2XTg (ORCPT ); Wed, 29 Mar 2023 19:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjC2XTc (ORCPT ); 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Wed, 29 Mar 2023 23:19:25 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32TNJPTV027023 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 23:19:25 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 29 Mar 2023 16:19:24 -0700 From: Jessica Zhang Date: Wed, 29 Mar 2023 16:18:49 -0700 Subject: [PATCH RFC 4/5] drm/msm/dpu: Fix slice_last_group_size calculation MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v1-4-f3e479f59b6d@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; 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Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 648c530b5d05..1a1a0f6523f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -56,7 +56,11 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, if (is_cmd_mode) initial_lines += 1; - slice_last_group_size = 3 - (dsc->slice_width % 3); + slice_last_group_size = dsc->slice_width % 3; + + if (slice_last_group_size == 0) + slice_last_group_size = 3; + data = (initial_lines << 20); data |= ((slice_last_group_size - 1) << 18); /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ From patchwork Wed Mar 29 23:18:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13193299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE88EC77B62 for ; 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Wed, 29 Mar 2023 16:19:24 -0700 From: Jessica Zhang Date: Wed, 29 Mar 2023 16:18:50 -0700 Subject: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v1-5-f3e479f59b6d@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v1-0-f3e479f59b6d@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680131963; l=2616; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=xG8XY4p+9sFuZ8VS88BsiwokXrujL45jZTipBXd/wvk=; b=yGo90Rh1uJuG9Kx42aciP2HeHa7QELQufwSogDlIuBpZRPEUR96UNeFoqIgekbvkfktbpv+QB z96j45GCIBUA0ty4D60dp9yRMeTCFUle5crSsvozq9xFk2ZZs7Kcyof X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1NEiBEXsOL0vyW1QztdmwpQtOyfrXS5A X-Proofpoint-GUID: 1NEiBEXsOL0vyW1QztdmwpQtOyfrXS5A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_14,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=981 clxscore=1015 priorityscore=1501 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290174 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use MSM and DRM DSC helper methods. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 74d38f90398a..7419fe58a941 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -31,6 +31,7 @@ #include "msm_kms.h" #include "msm_gem.h" #include "phy/dsi_phy.h" +#include "disp/msm_dsc_helper.h" #define DSI_RESET_TOGGLE_DELAY_MS 20 @@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod { struct drm_dsc_config *dsc = msm_host->dsc; u32 reg, reg_ctrl, reg_ctrl2; - u32 slice_per_intf, total_bytes_per_intf; + u32 slice_per_intf; u32 pkt_per_line; u32 eol_byte_num; /* first calculate dsc parameters and then program * compress mode registers */ - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); + slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay); /* * If slice_count is greater than slice_per_intf @@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod if (dsc->slice_count > slice_per_intf) dsc->slice_count = 1; - total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay, + dsi_get_bpp(msm_host->format)); - eol_byte_num = total_bytes_per_intf % 3; - pkt_per_line = slice_per_intf / dsc->slice_count; + pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT; if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); @@ -911,6 +912,11 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DBG(""); + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) + /* Default widebus_en to false for now. */ + hdisplay = msm_dsc_get_pclk_per_line(msm_host->dsc, mode->hdisplay, + dsi_get_bpp(msm_host->format)); + /* * For bonded DSI mode, the current DRM mode has * the complete width of the panel. Since, the complete @@ -1759,7 +1765,7 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return ret; } - dsc->initial_scale_value = 32; + dsc->initial_scale_value = drm_dsc_calculate_initial_scale_value(dsc); dsc->line_buf_depth = dsc->bits_per_component + 1; return drm_dsc_compute_rc_parameters(dsc);