From patchwork Thu Mar 30 11:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13194061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FDBEC77B71 for ; Thu, 30 Mar 2023 11:45:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231774AbjC3LpM (ORCPT ); Thu, 30 Mar 2023 07:45:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231963AbjC3Lov (ORCPT ); Thu, 30 Mar 2023 07:44:51 -0400 Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2017A83C8; Thu, 30 Mar 2023 04:44:24 -0700 (PDT) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32UBb8lj027643; Thu, 30 Mar 2023 11:43:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=4JDk3ncKZXU86FTMRQRNJwRzhvtHRmjgsixB4IkaKEg=; b=J2qt50Ejf4y/XBJf0B24OG7yLdfbiXISFlcK8uzfMn27gn4LaLwHOUUUv8+Phh2J/zjQ 9n/2KVZfBiDt/r/cUv160It6map74Y0ZMN/kbuMt2aFOSvjLDdc9sk0na/kJZocJT8ZB Oa/0AVy0WKP4Y6/nJietMRWyBLEUt1HvbHt4aD7fQ2jsR7e5I/6CoBCOQ6J7A8v48L4T 4hFJnOWKt+ofM88muLfQ84MuBiMWqsP9AzXAKvtbNB/OJ3lHG6XbpoYw2KceI4LKuMKJ JmGHH1bs44hZ8d/iOBwIlnrG5mOBM0KEWtb84zaUz0CLR0WgC0SLaQYlNVItlFtBGdZV aQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3pmp335vtx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 11:43:46 +0000 Received: from m0098420.ppops.net (m0098420.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32UBhj0U025966; Thu, 30 Mar 2023 11:43:45 GMT Received: from ppma01fra.de.ibm.com (46.49.7a9f.ip4.static.sl-reverse.com [159.122.73.70]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3pmp335vtg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 11:43:45 +0000 Received: from pps.filterd (ppma01fra.de.ibm.com [127.0.0.1]) by ppma01fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 32U3IgrT011237; Thu, 30 Mar 2023 11:43:43 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma01fra.de.ibm.com (PPS) with ESMTPS id 3phrk6mt8u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 11:43:43 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 32UBheBL25821544 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 30 Mar 2023 11:43:40 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2EBB20040; Thu, 30 Mar 2023 11:43:39 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4B01920043; Thu, 30 Mar 2023 11:43:39 +0000 (GMT) Received: from linux6.. (unknown [9.114.12.104]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 11:43:39 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, imbrenda@linux.ibm.com, nrb@linux.ibm.com, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH 1/5] lib: s390x: Add ap library Date: Thu, 30 Mar 2023 11:42:40 +0000 Message-Id: <20230330114244.35559-2-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330114244.35559-1-frankja@linux.ibm.com> References: <20230330114244.35559-1-frankja@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: e9bGNx0CCYFo3ip1Mxx1NbQaJPa9XhyN X-Proofpoint-ORIG-GUID: MUFAudQSslP7b_C1sKSyZ5MXfK72C5wa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_07,2023-03-30_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300095 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add functions and definitions needed to test the Adjunct Processor (AP) crypto interface. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/s390x/ap.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 lib/s390x/ap.c create mode 100644 lib/s390x/ap.h diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c new file mode 100644 index 00000000..374fa210 --- /dev/null +++ b/lib/s390x/ap.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP crypto functions + * + * Some parts taken from the Linux AP driver. + * + * Copyright IBM Corp. 2023 + * Author: Janosch Frank + * Tony Krowiak + * Martin Schwidefsky + * Harald Freudenberger + */ + +#include +#include +#include +#include + +int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct pqap_r2 *r2) +{ + struct pqap_r0 r0 = {}; + int cc; + + /* + * Test AP Queue + * + * Writes AP configuration information to the memory pointed + * at by GR2. + * + * Inputs: 0 + * Outputs: 1 (APQSW), 2 (tapq data) + * Synchronous + */ + r0.ap = ap; + r0.qn = qn; + r0.fc = PQAP_TEST_APQ; + asm volatile( + " lgr 0,%[r0]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " stg 1, %[apqsw]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [apqsw] "=&T" (*apqsw), [r2] "+&d" (r2), [cc] "=&d" (cc) + : [r0] "d" (r0) + : "memory"); + + return cc; +} + +int ap_pqap_qci(struct ap_config_info *info) +{ + struct pqap_r0 r0 = { .fc = PQAP_QUERY_AP_CONF_INFO }; + unsigned long r1 = 0; + int cc; + + /* + * Query AP Configuration Information + * + * Writes AP configuration information to the memory pointed + * at by GR2. + * + * Inputs: 0,2 + * Outputs: memory at r2 address + * Synchronous + */ + asm volatile( + " lgr 0,%[r0]\n" + " lgr 2,%[info]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " ipm %[cc]\n" + " srl %[cc],28\n" + : [r1] "+&d" (r1), [cc] "=&d" (cc) + : [r0] "d" (r0), [info] "d" (info) + : "cc", "memory", "0", "2"); + + return cc; +} + +bool ap_check(void) +{ + struct ap_queue_status r1 = {}; + struct pqap_r2 r2 = {}; + + /* Base AP support has no STFLE or SCLP feature bit */ + expect_pgm_int(); + ap_pqap_tapq(0, 0, &r1, &r2); + + if (clear_pgm_int() == PGM_INT_CODE_OPERATION) + return false; + + return true; +} diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h new file mode 100644 index 00000000..79fe6eb0 --- /dev/null +++ b/lib/s390x/ap.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP definitions + * + * Copyright IBM Corp. 2023 + * Author: Janosch Frank + * Tony Krowiak + * Martin Schwidefsky + * Harald Freudenberger + */ + +#ifndef _S390X_AP_H_ +#define _S390X_AP_H_ + +enum PQAP_FC { + PQAP_TEST_APQ, + PQAP_RESET_APQ, + PQAP_ZEROIZE_APQ, + PQAP_QUEUE_INT_CONTRL, + PQAP_QUERY_AP_CONF_INFO, + PQAP_QUERY_AP_COMP_TYPE, + PQAP_BEST_AP, +}; + +struct ap_queue_status { + uint32_t pad0; /* Ignored padding for zArch */ + uint32_t empty : 1; + uint32_t replies_waiting: 1; + uint32_t full : 1; + uint32_t pad1 : 4; + uint32_t irq_enabled : 1; + uint32_t rc : 8; + uint32_t pad2 : 16; +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct ap_queue_status) == sizeof(uint64_t), "APQSW size"); + +struct ap_config_info { + uint8_t apsc : 1; /* S bit */ + uint8_t apxa : 1; /* N bit */ + uint8_t qact : 1; /* C bit */ + uint8_t rc8a : 1; /* R bit */ + uint8_t l : 1; /* L bit */ + uint8_t lext : 3; /* Lext bits */ + uint8_t reserved2[3]; + uint8_t Na; /* max # of APs - 1 */ + uint8_t Nd; /* max # of Domains - 1 */ + uint8_t reserved6[10]; + uint32_t apm[8]; /* AP ID mask */ + uint32_t aqm[8]; /* AP (usage) queue mask */ + uint32_t adm[8]; /* AP (control) domain mask */ + uint8_t _reserved4[16]; +} __attribute__((aligned(8))) __attribute__ ((__packed__)); +_Static_assert(sizeof(struct ap_config_info) == 128, "PQAP QCI size"); + +struct pqap_r0 { + uint32_t pad0; + uint8_t fc; + uint8_t t : 1; /* Test facilities (TAPQ)*/ + uint8_t pad1 : 7; + uint8_t ap; + uint8_t qn; +} __attribute__((packed)) __attribute__((aligned(8))); + +struct pqap_r2 { + uint8_t s : 1; /* Special Command facility */ + uint8_t m : 1; /* AP4KM */ + uint8_t c : 1; /* AP4KC */ + uint8_t cop : 1; /* AP is in coprocessor mode */ + uint8_t acc : 1; /* AP is in accelerator mode */ + uint8_t xcp : 1; /* AP is in XCP-mode */ + uint8_t n : 1; /* AP extended addressing facility */ + uint8_t pad_0 : 1; + uint8_t pad_1[3]; + uint8_t at; + uint8_t nd; + uint8_t pad_6; + uint8_t pad_7 : 4; + uint8_t qd : 4; +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); + +bool ap_check(void); +int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct pqap_r2 *r2); +int ap_pqap_qci(struct ap_config_info *info); +#endif From patchwork Thu Mar 30 11:42:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13194064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F10EC6FD1D for ; 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(unknown [9.114.12.104]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 11:43:40 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, imbrenda@linux.ibm.com, nrb@linux.ibm.com, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH 2/5] s390x: Add guest 2 AP test Date: Thu, 30 Mar 2023 11:42:41 +0000 Message-Id: <20230330114244.35559-3-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330114244.35559-1-frankja@linux.ibm.com> References: <20230330114244.35559-1-frankja@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: B09ED7n7aMi6rWKAQmwd7J-EdZWAzofx X-Proofpoint-ORIG-GUID: sxadj7C6HcqdSXdOiKuniGYGgwX-aSBt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_06,2023-03-30_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 adultscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300095 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a test that checks the exceptions for the PQAP, NQAP and DQAP adjunct processor (AP) crypto instructions. Since triggering the exceptions doesn't require actual AP hardware, this test can run without complicated setup. Signed-off-by: Janosch Frank --- s390x/Makefile | 2 + s390x/ap.c | 308 ++++++++++++++++++++++++++++++++++++++++++++ s390x/unittests.cfg | 4 + 3 files changed, 314 insertions(+) create mode 100644 s390x/ap.c diff --git a/s390x/Makefile b/s390x/Makefile index e8559a4e..f74241d5 100644 --- a/s390x/Makefile +++ b/s390x/Makefile @@ -39,6 +39,7 @@ tests += $(TEST_DIR)/panic-loop-extint.elf tests += $(TEST_DIR)/panic-loop-pgm.elf tests += $(TEST_DIR)/migration-sck.elf tests += $(TEST_DIR)/exittime.elf +tests += $(TEST_DIR)/ap.elf pv-tests += $(TEST_DIR)/pv-diags.elf pv-tests += $(TEST_DIR)/pv-icptcode.elf @@ -102,6 +103,7 @@ cflatobjs += lib/s390x/malloc_io.o cflatobjs += lib/s390x/uv.o cflatobjs += lib/s390x/sie.o cflatobjs += lib/s390x/fault.o +cflatobjs += lib/s390x/ap.o OBJDIRS += lib/s390x diff --git a/s390x/ap.c b/s390x/ap.c new file mode 100644 index 00000000..82ddb6d2 --- /dev/null +++ b/s390x/ap.c @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP instruction G2 tests + * + * Copyright (c) 2023 IBM Corp + * + * Authors: + * Janosch Frank + */ + +#include +#include +#include +#include +#include +#include +#include + +/* For PQAP PGM checks where we need full control over the input */ +static void pqap(unsigned long grs[3]) +{ + asm volatile( + " lgr 0,%[r0]\n" + " lgr 1,%[r1]\n" + " lgr 2,%[r2]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + :: [r0] "d" (grs[0]), [r1] "d" (grs[1]), [r2] "d" (grs[2]) + : "cc", "memory", "0", "1", "2"); +} + +static void test_pgms_pqap(void) +{ + unsigned long grs[3] = {}; + struct pqap_r0 *r0 = (struct pqap_r0 *)grs; + uint8_t *data = alloc_page(); + uint16_t pgm; + int fails = 0; + int i; + + report_prefix_push("pqap"); + + /* Wrong FC code */ + report_prefix_push("invalid fc"); + r0->fc = 42; + expect_pgm_int(); + pqap(grs); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + memset(grs, 0, sizeof(grs)); + report_prefix_pop(); + + report_prefix_push("invalid gr0 bits"); + for (i = 42; i < 6; i++) { + expect_pgm_int(); + grs[0] = BIT(63 - i); + pqap(grs); + pgm = clear_pgm_int(); + + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", i); + fails++; + } + } + report(!fails, "All bits tested"); + memset(grs, 0, sizeof(grs)); + fails = 0; + report_prefix_pop(); + + report_prefix_push("alignment"); + report_prefix_push("fc=4"); + r0->fc = PQAP_QUERY_AP_CONF_INFO; + grs[2] = (unsigned long)data; + for (i = 1; i < 8; i++) { + expect_pgm_int(); + grs[2]++; + pqap(grs); + pgm = clear_pgm_int(); + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", i); + fails++; + } + } + report(!fails, "All bits tested"); + report_prefix_pop(); + report_prefix_push("fc=6"); + r0->fc = PQAP_BEST_AP; + grs[2] = (unsigned long)data; + for (i = 1; i < 8; i++) { + expect_pgm_int(); + grs[2]++; + pqap(grs); + pgm = clear_pgm_int(); + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", i); + fails++; + } + } + report(!fails, "All bits tested"); + report_prefix_pop(); + report_prefix_pop(); + + free_page(data); + report_prefix_pop(); +} + +static void test_pgms_nqap(void) +{ + uint8_t gr0_zeroes_bits[] = { + 32, 34, 35, 40 + }; + uint64_t gr0; + bool fail; + int i; + + report_prefix_push("nqap"); + + /* Registers 0 and 1 are always used, the others are even/odd pairs */ + report_prefix_push("spec"); + report_prefix_push("r1"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ad0000,3,6\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("r2"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ad0000,2,7\n" + : : : "cc", "memory", "0", "1", "3", "4"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len==0"); + expect_pgm_int(); + asm volatile ( + "xgr 0,0\n" + "xgr 5,5\n" + ".insn rre,0xb2ad0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len>12288"); + expect_pgm_int(); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 12289\n" + ".insn rre,0xb2ad0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("gr0_zero_bits"); + fail = false; + for (i = 0; i < 4; i++) { + expect_pgm_int(); + gr0 = BIT_ULL(63 - gr0_zeroes_bits[i]); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 128\n" + "lg 0, 0(%[val])\n" + ".insn rre,0xb2ad0000,2,4\n" + : : [val] "a" (&gr0) + : "cc", "memory", "0", "1", "2", "3", "4", "5"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_fail("setting gr0 bit %d did not result in a spec exception", + gr0_zeroes_bits[i]); + fail = true; + } + } + report(!fail, "set bit specification pgms"); + report_prefix_pop(); + + report_prefix_pop(); + report_prefix_pop(); +} + +static void test_pgms_dqap(void) +{ + uint8_t gr0_zeroes_bits[] = { + 33, 34, 35, 40, 41 + }; + uint64_t gr0; + bool fail; + int i; + + report_prefix_push("dqap"); + + /* Registers 0 and 1 are always used, the others are even/odd pairs */ + report_prefix_push("spec"); + report_prefix_push("r1"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ae0000,3,6\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("r2"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ae0000,2,7\n" + : : : "cc", "memory", "0", "1", "3", "4"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len==0"); + expect_pgm_int(); + asm volatile ( + "xgr 0,0\n" + "xgr 5,5\n" + ".insn rre,0xb2ae0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len>12288"); + expect_pgm_int(); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 12289\n" + ".insn rre,0xb2ae0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("gr0_zero_bits"); + fail = false; + for (i = 0; i < 5; i++) { + expect_pgm_int(); + gr0 = BIT_ULL(63 - gr0_zeroes_bits[i]); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 128\n" + "lg 0, 0(%[val])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [val] "a" (&gr0) + : "cc", "memory", "0", "1", "2", "3", "4", "5"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_info("setting gr0 bit %d did not result in a spec exception", + gr0_zeroes_bits[i]); + fail = true; + } + } + report(!fail, "set bit specification pgms"); + report_prefix_pop(); + + report_prefix_pop(); + report_prefix_pop(); +} + +static void test_priv(void) +{ + struct ap_config_info info = {}; + + report_prefix_push("privileged"); + + report_prefix_push("pqap"); + expect_pgm_int(); + enter_pstate(); + ap_pqap_qci(&info); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + /* + * Enqueue and dequeue take too many registers so a simple + * inline assembly makes more sense than using the library + * functions. + */ + report_prefix_push("nqap"); + expect_pgm_int(); + enter_pstate(); + asm volatile ( + ".insn rre,0xb2ad0000,0,2\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + report_prefix_push("dqap"); + expect_pgm_int(); + enter_pstate(); + asm volatile ( + ".insn rre,0xb2ae0000,0,2\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + report_prefix_pop(); +} + +int main(void) +{ + report_prefix_push("ap"); + if (!ap_check()) { + report_skip("AP instructions not available"); + goto done; + } + + test_priv(); + test_pgms_pqap(); + test_pgms_nqap(); + test_pgms_dqap(); + +done: + report_prefix_pop(); + return report_summary(); +} diff --git a/s390x/unittests.cfg b/s390x/unittests.cfg index d97eb5e9..9b7c65c8 100644 --- a/s390x/unittests.cfg +++ b/s390x/unittests.cfg @@ -215,3 +215,7 @@ file = migration-skey.elf smp = 2 groups = migration extra_params = -append '--parallel' + +[ap] +file = ap.elf + From patchwork Thu Mar 30 11:42:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13194060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12105C77B6D for ; Thu, 30 Mar 2023 11:45:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231719AbjC3LpK (ORCPT ); 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(unknown [9.114.12.104]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 11:43:40 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, imbrenda@linux.ibm.com, nrb@linux.ibm.com, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH 3/5] lib: s390x: ap: Add ap_setup Date: Thu, 30 Mar 2023 11:42:42 +0000 Message-Id: <20230330114244.35559-4-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330114244.35559-1-frankja@linux.ibm.com> References: <20230330114244.35559-1-frankja@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: QytCP7Yc3urW1ldyhx2XZZexcBfMSk6Z X-Proofpoint-GUID: Zx_-YMuKWiaho-HaFavPdbtXVFaMT9Rv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_07,2023-03-30_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 impostorscore=0 mlxlogscore=899 bulkscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300095 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For the next tests we need a valid queue which means we need to grab the qci info and search the first set bit in the ap and aq masks. Let's move from the ap_check function to a proper setup function that also returns the first usable APQN. Later we can extend the setup to build a list of all available APQNs but right now one APQN is plenty. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++- lib/s390x/ap.h | 5 ++++- s390x/ap.c | 7 ++++++- 3 files changed, 63 insertions(+), 3 deletions(-) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index 374fa210..8d7f2992 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -13,9 +13,12 @@ #include #include +#include #include #include +static struct ap_config_info qci; + int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2) { @@ -77,7 +80,44 @@ int ap_pqap_qci(struct ap_config_info *info) return cc; } -bool ap_check(void) +static int ap_get_apqn(uint8_t *ap, uint8_t *qn) +{ + unsigned long *ptr; + uint8_t bit; + int i; + + ap_pqap_qci(&qci); + *ap = 0; + *qn = 0; + + ptr = (unsigned long *)qci.apm; + for (i = 0; i < 4; i++) { + bit = fls(*ptr); + if (bit) { + *ap = i * 64 + 64 - bit; + break; + } + } + ptr = (unsigned long *)qci.aqm; + for (i = 0; i < 4; i++) { + bit = fls(*ptr); + if (bit) { + *qn = i * 64 + 64 - bit; + break; + } + } + + if (!*ap || !*qn) + return -1; + + /* fls returns 1 + bit number, so we need to remove 1 here */ + *ap -= 1; + *qn -= 1; + + return 0; +} + +static bool ap_check(void) { struct ap_queue_status r1 = {}; struct pqap_r2 r2 = {}; @@ -91,3 +131,15 @@ bool ap_check(void) return true; } + +int ap_setup(uint8_t *ap, uint8_t *qn) +{ + if (!ap_check()) + return AP_SETUP_NOINSTR; + + /* Instructions available but no APQNs */ + if (ap_get_apqn(ap, qn)) + return AP_SETUP_NOAPQN; + + return 0; +} diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index 79fe6eb0..59595eba 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -79,7 +79,10 @@ struct pqap_r2 { } __attribute__((packed)) __attribute__((aligned(8))); _Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); -bool ap_check(void); +#define AP_SETUP_NOINSTR -1 +#define AP_SETUP_NOAPQN 1 + +int ap_setup(uint8_t *ap, uint8_t *qn); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); int ap_pqap_qci(struct ap_config_info *info); diff --git a/s390x/ap.c b/s390x/ap.c index 82ddb6d2..20b4e76e 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -16,6 +16,9 @@ #include #include +static uint8_t apn; +static uint8_t qn; + /* For PQAP PGM checks where we need full control over the input */ static void pqap(unsigned long grs[3]) { @@ -291,8 +294,10 @@ static void test_priv(void) int main(void) { + int setup_rc = ap_setup(&apn, &qn); + report_prefix_push("ap"); - if (!ap_check()) { + if (setup_rc == AP_SETUP_NOINSTR) { report_skip("AP instructions not available"); goto done; } From patchwork Thu Mar 30 11:42:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13194063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ECCDC77B6E for ; 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(unknown [9.114.12.104]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 11:43:41 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, imbrenda@linux.ibm.com, nrb@linux.ibm.com, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH 4/5] s390x: ap: Add pqap aqic tests Date: Thu, 30 Mar 2023 11:42:43 +0000 Message-Id: <20230330114244.35559-5-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330114244.35559-1-frankja@linux.ibm.com> References: <20230330114244.35559-1-frankja@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: BKCE0FjLvtp0jE1QsPShbbowBgEZZAx8 X-Proofpoint-ORIG-GUID: jo3Dv3SrtUCqhVz1Sz7wzRevSsDMu3VT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_07,2023-03-30_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300095 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Let's check if we can enable/disable interrupts and if all errors are reported if we specify bad addresses for the notification indication byte. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 33 +++++++++++++++++++++++++++++ lib/s390x/ap.h | 11 ++++++++++ s390x/ap.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index 8d7f2992..aaf5b4b9 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -51,6 +51,39 @@ int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, return cc; } +int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct ap_qirq_ctrl aqic, unsigned long addr) +{ + struct pqap_r0 r0 = {}; + int cc; + + /* + * AP-Queue Interruption Control + * + * Enables/disables interrupts for a APQN + * + * Inputs: 0,1,2 + * Outputs: 1 (APQSW) + * Synchronous + */ + r0.ap = ap; + r0.qn = qn; + r0.fc = PQAP_QUEUE_INT_CONTRL; + asm volatile( + " lgr 0,%[r0]\n" + " lgr 1,%[aqic]\n" + " lgr 2,%[addr]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " stg 1, %[apqsw]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [apqsw] "=T" (*apqsw), [cc] "=&d" (cc) + : [r0] "d" (r0), [aqic] "d" (aqic), [addr] "d" (addr) + : "cc", "memory", "0", "2"); + + return cc; +} + int ap_pqap_qci(struct ap_config_info *info) { struct pqap_r0 r0 = { .fc = PQAP_QUERY_AP_CONF_INFO }; diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index 59595eba..3f9e2eb6 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -79,6 +79,15 @@ struct pqap_r2 { } __attribute__((packed)) __attribute__((aligned(8))); _Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); +struct ap_qirq_ctrl { + uint64_t res0 : 16; + uint64_t ir : 1; /* ir flag: enable (1) or disable (0) irq */ + uint64_t res1 : 44; + uint64_t isc : 3; /* irq sub class */ +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct ap_qirq_ctrl) == sizeof(uint64_t), + "struct ap_qirq_ctrl size"); + #define AP_SETUP_NOINSTR -1 #define AP_SETUP_NOAPQN 1 @@ -86,4 +95,6 @@ int ap_setup(uint8_t *ap, uint8_t *qn); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); int ap_pqap_qci(struct ap_config_info *info); +int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct ap_qirq_ctrl aqic, unsigned long addr); #endif diff --git a/s390x/ap.c b/s390x/ap.c index 20b4e76e..31dcfe29 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -292,6 +292,55 @@ static void test_priv(void) report_prefix_pop(); } +static void test_pqap_aqic(void) +{ + struct ap_queue_status apqsw = {}; + static uint8_t not_ind_byte; + struct ap_qirq_ctrl aqic = {}; + struct pqap_r2 r2 = {}; + + int cc; + + report_prefix_push("pqap"); + report_prefix_push("aqic"); + + ap_pqap_tapq(apn, qn, &apqsw, &r2); + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, 0); + report(cc == 3 && apqsw.rc == 6, "invalid addr 0"); + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, -1); + report(cc == 3 && apqsw.rc == 6, "invalid addr -1"); + + aqic.ir = 0; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + report(cc == 3 && apqsw.rc == 7, "disable"); + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable"); + + do { + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + report(cc == 3 && apqsw.rc == 7, "enable while enabled"); + + aqic.ir = 0; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + assert(cc == 0 && apqsw.rc == 0); + + do { + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 1); + + report_prefix_pop(); + report_prefix_pop(); +} + int main(void) { int setup_rc = ap_setup(&apn, &qn); @@ -307,6 +356,13 @@ int main(void) test_pgms_nqap(); test_pgms_dqap(); + /* The next tests need queues */ + if (setup_rc == AP_SETUP_NOAPQN) { + report_skip("No APQN available"); + goto done; + } + test_pqap_aqic(); + done: report_prefix_pop(); return report_summary(); From patchwork Thu Mar 30 11:42:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13194062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DD22C761A6 for ; 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(unknown [9.114.12.104]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Mar 2023 11:43:42 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, imbrenda@linux.ibm.com, nrb@linux.ibm.com, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH 5/5] s390x: ap: Add reset tests Date: Thu, 30 Mar 2023 11:42:44 +0000 Message-Id: <20230330114244.35559-6-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330114244.35559-1-frankja@linux.ibm.com> References: <20230330114244.35559-1-frankja@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: I5_mCWp2ugOhj3MfLEsjAmeStljk8UlL X-Proofpoint-ORIG-GUID: NMlbosLje0nwTcJhqEQCdYs6Dk_ja9xm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_07,2023-03-30_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300095 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Test if the IRQ enablement is turned off on a reset or zeroize PQAP. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/s390x/ap.h | 4 +++ s390x/ap.c | 52 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index aaf5b4b9..d969b2a5 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -113,6 +113,74 @@ int ap_pqap_qci(struct ap_config_info *info) return cc; } +static int pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *r1, + bool zeroize) +{ + struct pqap_r0 r0 = {}; + int cc; + + /* + * Reset/zeroize AP Queue + * + * Resets/zeroizes a queue and disables IRQs + * + * Inputs: 0 + * Outputs: 1 + * Asynchronous + */ + r0.ap = ap; + r0.qn = qn; + r0.fc = zeroize ? PQAP_ZEROIZE_APQ : PQAP_RESET_APQ; + asm volatile( + " lgr 0,%[r0]\n" + " lgr 1,%[r1]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " ipm %[cc]\n" + " srl %[cc],28\n" + : [r1] "+&d" (r1), [cc] "=&d" (cc) + : [r0] "d" (r0) + : "memory"); + + return cc; +} + +static int pqap_reset_wait(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + bool zeroize) +{ + struct pqap_r2 r2 = {}; + int cc; + + cc = pqap_reset(ap, qn, apqsw, zeroize); + /* On a cc == 3 / error we don't need to wait */ + if (cc) + return cc; + + /* + * TAPQ returns AP_RC_RESET_IN_PROGRESS if a reset is being + * processed + */ + do { + cc = ap_pqap_tapq(ap, qn, apqsw, &r2); + /* Give it some time to process before the retry */ + mdelay(20); + } while (apqsw->rc == AP_RC_RESET_IN_PROGRESS); + + if (apqsw->rc) + printf("Wait for reset failed on ap %d queue %d with tapq rc %d.", + ap, qn, apqsw->rc); + return cc; +} + +int ap_pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw) +{ + return pqap_reset_wait(ap, qn, apqsw, false); +} + +int ap_pqap_reset_zeroize(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw) +{ + return pqap_reset_wait(ap, qn, apqsw, true); +} + static int ap_get_apqn(uint8_t *ap, uint8_t *qn) { unsigned long *ptr; diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index 3f9e2eb6..f9343b5f 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -12,6 +12,8 @@ #ifndef _S390X_AP_H_ #define _S390X_AP_H_ +#define AP_RC_RESET_IN_PROGRESS 0x02 + enum PQAP_FC { PQAP_TEST_APQ, PQAP_RESET_APQ, @@ -94,6 +96,8 @@ _Static_assert(sizeof(struct ap_qirq_ctrl) == sizeof(uint64_t), int ap_setup(uint8_t *ap, uint8_t *qn); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); +int ap_pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); +int ap_pqap_reset_zeroize(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); int ap_pqap_qci(struct ap_config_info *info); int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct ap_qirq_ctrl aqic, unsigned long addr); diff --git a/s390x/ap.c b/s390x/ap.c index 31dcfe29..47b4f832 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -341,6 +341,57 @@ static void test_pqap_aqic(void) report_prefix_pop(); } +static void test_pqap_resets(void) +{ + struct ap_queue_status apqsw = {}; + static uint8_t not_ind_byte; + struct ap_qirq_ctrl aqic = {}; + struct pqap_r2 r2 = {}; + + int cc; + + report_prefix_push("pqap"); + report_prefix_push("rapq"); + + /* Enable IRQs which the resets will disable */ + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable"); + + do { + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + report(apqsw.irq_enabled == 1, "IRQs enabled"); + + ap_pqap_reset(apn, qn, &apqsw); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + assert(!cc); + report(apqsw.irq_enabled == 0, "IRQs have been disabled"); + + report_prefix_pop(); + + report_prefix_push("zapq"); + + /* Enable IRQs which the resets will disable */ + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)¬_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable"); + + do { + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + report(apqsw.irq_enabled == 1, "IRQs enabled"); + + ap_pqap_reset_zeroize(apn, qn, &apqsw); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + assert(!cc); + report(apqsw.irq_enabled == 0, "IRQs have been disabled"); + + report_prefix_pop(); + + report_prefix_pop(); +} + int main(void) { int setup_rc = ap_setup(&apn, &qn); @@ -362,6 +413,7 @@ int main(void) goto done; } test_pqap_aqic(); + test_pqap_resets(); done: report_prefix_pop();