From patchwork Mon Apr 3 21:33:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Harrison X-Patchwork-Id: 13198808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A35C9C76188 for ; Mon, 3 Apr 2023 21:34:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D25BC10E57E; Mon, 3 Apr 2023 21:34:05 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 482D910E57E; Mon, 3 Apr 2023 21:34:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680557644; x=1712093644; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PVQacA9QABI9zE3gc6CVjH21u5LBvPl9h3diP4eUKLs=; b=f/DpIwyVIyAzevcA7q5Mqe76e1CZ4hETaXiG33WKoza6/h6XUBWn3ZTk kMgimifhpFMkDCkDpZUQGybEwwTrBnj7M+D0dAjhPC8StLfpZJojbMum7 6GsvINTW6VFpjEq3L+YZQeeXcvY/sVFrNzcHp2cVJprxVijVliiklRrfc zVgzjLMS+bjMi8svz2DNIv0m2nlY505ANcME1NPETcv+OqCYdILHA/8Tl 6sGe9ccjCWYkT2CBiI07mlGc2lt6FnCG3ROf4kmPLFznLHoIsfVAMWLbq upaJupwYaj1aitwEc6j6sh3Xv5M+qxdYpMpW8Ko5qEB1JLNQPv6GGPg64 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="407075435" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="407075435" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 14:34:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="716431966" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="716431966" Received: from relo-linux-5.jf.intel.com ([10.165.21.152]) by orsmga008.jf.intel.com with ESMTP; 03 Apr 2023 14:34:03 -0700 From: John.C.Harrison@Intel.com To: Intel-GFX@Lists.FreeDesktop.Org Subject: [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices Date: Mon, 3 Apr 2023 14:33:34 -0700 Message-Id: <20230403213334.1655239-1-John.C.Harrison@Intel.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balasubramani Vivekanandan , Alan Previn , Jani Nikula , Matt Roper , Lucas De Marchi , DRI-Devel@Lists.FreeDesktop.Org, Daniele Ceraolo Spurio , Umesh Nerlige Ramappa , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: John Harrison A pair of pre-Gen12 registers were being included in the Gen12 capture list. GuC was rejecting those as being invalid and logging errors about them. So, stop doing it. Signed-off-by: John Harrison Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.") Cc: Alan Previn Cc: Umesh Nerlige Ramappa Cc: Lucas De Marchi Cc: John Harrison Cc: Jani Nikula Cc: Matt Roper Cc: Balasubramani Vivekanandan Cc: Daniele Ceraolo Spurio Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c index cf49188db6a6e..e0e793167d61b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c @@ -31,12 +31,14 @@ { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } #define COMMON_GEN9BASE_GLOBAL \ - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ { DONE_REG, 0, 0, "DONE_REG" }, \ { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } +#define GEN9_GLOBAL \ + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } + #define COMMON_GEN12BASE_GLOBAL \ { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { static const struct __guc_mmio_reg_descr default_global_regs[] = { COMMON_BASE_GLOBAL, COMMON_GEN9BASE_GLOBAL, + GEN9_GLOBAL, }; static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {