From patchwork Wed Apr 5 11:14:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1A2BC761A6 for ; Wed, 5 Apr 2023 11:15:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6euoQ1xEgcxR0VdE34AcoTfyWzbaydDx5cYSpSPvXcY=; b=XIUTTMc/KiXIRm ngDNt/2NDe6tiuADONyX1Pv7YUjcso6NpmtMsLo/16ko3K81aeZTqijxcFVb2wW1/3hpw3SgloA4u +sy5fZnlIA7OzrRPhIpjrPCZePiYCCHe+m1egdQshYubuZIMfJXVBAbk2YqdR/x/8Rq2usUyRMuiR wbE7vl6eoxhsnqIVn82fUTBrWHu3+oIUEw9fwFhT0PmZ1KDOXPxAl1u2xxIVm+Jc+gGtBeXASF45Z LEwuPbvCMReNybccJf4l9Ph53vhJTmw/PLxzoFdfPhBTIfoqBOSRe4FAWeKfCIWcivUbQJuIZUQhU u0yrldnF15MEHzU9Nkew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk15w-004Dir-1H; Wed, 05 Apr 2023 11:14:28 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15q-004Dfp-2t for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:25 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BEFTV107840; Wed, 5 Apr 2023 06:14:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693255; bh=gJwIOSAR6mPpOZd/TA9dQZe8R4GmfYpdvlq9WvMeFY0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X2WIYs/jO2+F/t4VI0YJduBdo+MByJIJAzpa/E5GFI4Mm9hL60zevGS8ntLtVIf3I JnHunOCKiJu4qCE6vbe+aTI3H5Q+3x1BYewS5X8KqcBv2/+FjpjsRMalPofuEkz/Uy Gku/rF/Rc1wFKHcHCuT4JC4xKqfEYGL6cyuz7s0g= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BEFoH036784 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:15 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:14 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:14 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BEEVv120241; Wed, 5 Apr 2023 06:14:14 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 1/6] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Date: Wed, 5 Apr 2023 16:44:07 +0530 Message-ID: <20230405111412.151192-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041423_016704_F1D29BB5 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Siddharth Vadapalli The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..344f4ffa0b82 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +29,25 @@ l3cache-sram@200000 { }; }; + scm_conf: scm-conf@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; From patchwork Wed Apr 5 11:14:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A9D0C761A6 for ; Wed, 5 Apr 2023 11:15:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=N4evyGh4+MelOyI3qXK13jJ5l4nYnQ3HitX3c8067PE=; b=NGDm5VvOQf7coi KgR6UBlfjco4A7Xqmatl2dpIELv2NYtrn7J698xSgKLyoqzxUZXTqUUg1enmcFRahveQEGZUyPpms yX/mGWHnI76XM0GCfoYCCfCv0e4KDP8HKxtaFaZqQLBZOGzdcDpyXqGS0fGgKgJCtKT+bbCWzjHTX kpK+P8Dm7Ih53t7QRWcJ4L+T6jXD5n2V6qX4sJDBpevXGY4Fxchzbw3MZN4rcV4v+5MDEjetqPH+Q A89b9JgcAOTwwBYUFxEPwvITDPumo4b86CFgUVICyv2W/bEc3OhL/9Ay5zd+Re1Q2a4u7ig8eBWC/ F7BZ0BfU2V5994OHnwiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk15x-004DjD-1b; Wed, 05 Apr 2023 11:14:29 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15r-004Dh6-2Y for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:26 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BEGgg041314; Wed, 5 Apr 2023 06:14:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693256; bh=ZXIT24LwUDoFK65Tx0pvt8BK2CEw61Wgiziw3JaY0Mk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TK8vSCD/huykw6fYl+TYP52NhgAGGHIFhHLvUtXGjFXzWvKGhLYfSgQSg/WepqLyB ZFRxWxHxuzOrpJ5RwMlpJQeGj0UGDmKFteIZFQGakQjIdl3doCoCFY2Is4D2teCS0c UGltpCgUUZCayBCGxxTsuduA4lKwocmM9aumZUiM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BEGdU041807 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:16 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:16 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BEF0o116097; Wed, 5 Apr 2023 06:14:16 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 2/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Wed, 5 Apr 2023 16:44:08 +0530 Message-ID: <20230405111412.151192-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041423_908283_49E24563 X-CRM114-Status: GOOD ( 10.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Siddharth Vadapalli J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch. Add the device-tree nodes for the Main CPSW2G instance and enable it. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 48 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f33815953e77..aef6f53ae8ac 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -105,6 +105,30 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + main_cpsw2g_pins_default: main-cpsw2g-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + main_uart8_pins_default: main-uart8-pins-default { pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ @@ -253,3 +277,27 @@ &mcu_cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&main_cpsw1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_pins_default>; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_pins_default>; + + main_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_phy0>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 344f4ffa0b82..35b2ee07549b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -36,6 +36,12 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + cpsw1_phy_gmii_sel: phy@4034 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4034 0x4>; + #phy-cells = <1>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -777,6 +783,68 @@ cpts@310d0000 { }; }; + main_cpsw1: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw1_port1: port@1 { + reg = <1>; + label = "port1"; + phys = <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 62 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, From patchwork Wed Apr 5 11:14:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77B62C76188 for ; Wed, 5 Apr 2023 11:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/LcY+CQ1iPebQcXzaIheAcs+9tGefSIzWmHiDh5B7ZU=; b=HMf84qPcy77V/y 60cUsTJvaJ6RgAeCP15UBRW2OXk4X0NXsMiYXYE3fxWOuNMug+9m7SAVP9uhyAfI2+TBCC3TVqDPY 122LWnfX2/9RDdKACUvBl2ZzdPuU/tj33JRP3jDhDtedopWVDI3HLG2YnEX07vGW5jvDgVHYPKx/Z BOxghz3NhRY6t5yeQldu9+xhVcsMNEulge72RDZS39waoECut2XJY5/kAB2D9B8P4d2KaZZiLBP2x GVkMqrj42/xqqNtBK61tgwKXWP3ZCWxujDXBKiA1j44Mz/3YsI22fx/P8t3GjzuHoaBSOQEjSLp+R kIgtMP3ZdiEuIc0UHJwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk15y-004Dkg-2W; Wed, 05 Apr 2023 11:14:30 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15r-004DgZ-2U for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:26 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BEIRK041323; Wed, 5 Apr 2023 06:14:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693258; bh=CVJHXScW334a/UbB6PQOgmJwO4fZtgGWRX415vTbtj0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=irc9htk3gASZwHGRJrjW6kjsPg+gcGF0kYIxbswqLvItN404QJZZs2e609gf8vzIp O70Ylseeu6HxGpylU/PshklhYvY3EziyK5Gni2ncLNkCEYZsBpqLZP6qNtBZnYn1sl ENb9zWAaE+NHiEptEOJ898IdhuS7cY6G0mRqOxCI= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BEIBk004442 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:18 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:17 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:17 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BEHkU003783; Wed, 5 Apr 2023 06:14:17 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 3/6] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Date: Wed, 5 Apr 2023 16:44:09 +0530 Message-ID: <20230405111412.151192-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041423_886803_F74D9121 X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Siddharth Vadapalli J784S4 SoC has 4 Serdes instances along with their respective WIZ instances. Add device-tree nodes for them and disable them by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 + arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 171 +++++++++++++++++++++ 2 files changed, 175 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index aef6f53ae8ac..b1445b7c2aa8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -301,3 +301,7 @@ &main_cpsw1_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&main_phy0>; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 35b2ee07549b..0cd692bc52e6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -7,6 +7,15 @@ #include #include +#include +#include + +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; &cbass_main { msmc_ram: sram@70000000 { @@ -440,6 +449,168 @@ main_sdhci1: mmc@4fb0000 { status = "disabled"; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&k3_clks 404 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 404 6>; + assigned-clock-parents = <&k3_clks 404 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x00 0x5060000 0x10000>; + + status = "disabled"; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&k3_clks 405 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 405 6>; + assigned-clock-parents = <&k3_clks 405 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05070000 0x00 0x05070000 0x10000>; + + status = "disabled"; + + serdes1: serdes@5070000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05070000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&k3_clks 406 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 406 6>; + assigned-clock-parents = <&k3_clks 406 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05020000 0x00 0x05020000 0x10000>; + + status = "disabled"; + + serdes2: serdes@5020000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05020000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz2 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&k3_clks 407 5>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 407 6>; + assigned-clock-parents = <&k3_clks 407 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + + status = "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy"; + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + main_navss: bus@30000000 { compatible = "simple-bus"; #address-cells = <2>; From patchwork Wed Apr 5 11:14:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46C85C7619A for ; Wed, 5 Apr 2023 11:15:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IADX5u5v14jMl6It1h8vZbFB3bL6unOvrNnabk2baLI=; b=45YqPeypzaV6xK Y5uhdc1r16XqkTzXhYjILTF/PGLLRcz5Y9DsZhqzeFXODRxtemTgAbUuXsnnq+ZJ7jeRVkSpS56oN nmGRMj+LJwkePipDKYvjsh56nzhWVtf7/XBDWQkSlUhDiRlP/8MGMTdl7IDcSXomxlRnOIBm+8gmg 1KZtyqhytv8dfgg5coeO9yyzrn64Sl2zBkGyaCSJpUWR+JYJnZ8AKkC/SHkNKPNOFn113LnSg+ox/ ziIEXQ9Bwwq3SyTQ3YsKn3ywWBsX5QXBAcWAoGZk/p6fXXU13XRCoCYHAXRpUrEs0c1MUVBBjDewt ZeASkWjnUs242xkIYigw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk163-004DnN-0t; Wed, 05 Apr 2023 11:14:35 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15x-004Div-1y for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:31 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BEJSW019349; Wed, 5 Apr 2023 06:14:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693259; bh=ne/R9/9lcpXYVNtZtDesLZu+LTAyPLuUfK5bBFhGcXs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=U2KD8wmpGD/UfM10e3cB/ETJjIGHifyMykdvb/JRyqZt4RBbA72Hqf8BCl2ZYDSmS fAX/i1QIBNXQI25pc5IHkC4hXcnxs49ZnQFQujDV5yvHucoQ0HqQpBJKy3IRzpTgjQ nNzUXCLtZZHGlPLLgi2D2rqeUlOgd/DPOqrgidqU= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BEJsA041827 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:19 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:19 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:19 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BEISE120287; Wed, 5 Apr 2023 06:14:19 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node Date: Wed, 5 Apr 2023 16:44:10 +0530 Message-ID: <20230405111412.151192-5-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041429_744527_6ECED0C2 X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rahul T R Add DSS node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. Also add assigned clks for DSS Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index b1445b7c2aa8..ccbfca76e9ae 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -305,3 +305,14 @@ &main_cpsw1_port1 { &serdes_refclk { clock-frequency = <100000000>; }; + +&dss { + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 0cd692bc52e6..86ce6f6d4fc2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1373,4 +1373,59 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 383 1>; status = "disabled"; }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = + <0x00 0x04a00000 0x00 0x10000>, + <0x00 0x04a10000 0x00 0x10000>, + <0x00 0x04b00000 0x00 0x10000>, + <0x00 0x04b10000 0x00 0x10000>, + + <0x00 0x04a20000 0x00 0x10000>, + <0x00 0x04a30000 0x00 0x10000>, + <0x00 0x04a50000 0x00 0x10000>, + <0x00 0x04a60000 0x00 0x10000>, + + <0x00 0x04a70000 0x00 0x10000>, + <0x00 0x04a90000 0x00 0x10000>, + <0x00 0x04ab0000 0x00 0x10000>, + <0x00 0x04ad0000 0x00 0x10000>, + + <0x00 0x04a80000 0x00 0x10000>, + <0x00 0x04aa0000 0x00 0x10000>, + <0x00 0x04ac0000 0x00 0x10000>, + <0x00 0x04ae0000 0x00 0x10000>, + <0x00 0x04af0000 0x00 0x10000>; + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + }; + }; }; From patchwork Wed Apr 5 11:14:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2242DC77B60 for ; Wed, 5 Apr 2023 11:15:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M2qdom4UiWVIPbBEcGSouLODix6JP9tb5Gkrkmh9Ry8=; b=3uSBFs+mk0r2ZU m+Jfyv/in8NAugB8SC7SLWj9TApAyNHQ2+7HuVRWkdcz6M1F9/Id5y0H/AD+gZG3IBMcrMRFx30WZ WGJS5DH57EgLlPRuASs6s82qnUQr+0+FkPmsTypsRoVHL1BgAY9OUQVEfQcJT4Ea5yEXR0ljt1xdy /fO1ZFImbQvMRFWJXIkvw1E5AgkPV6hB2K6FUmDezj70UXmqSMeysIKVsNlkRg+1LrS+wsW2H9z9e 0d5PadL4ZWnV5cS4eP6jcuqZWptMNOX0BcRhm2OdFInY9JVyscpCerMD4cLNX82UG4f/7l3xwUqFW P2srFywGig4EPzVZ/xCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk164-004Do1-1U; Wed, 05 Apr 2023 11:14:36 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15y-004Djv-2U for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:32 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BELQs019354; Wed, 5 Apr 2023 06:14:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693261; bh=oFvQkBfdjln/WhbfYxZasipH1KQY08uztdM09uYGWpU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h92fslHtiMrA//l7pz56s305/kDaH+0T+qnCunmYDFK/Mtg4xELkVPSQHM8937RSZ ey0eQl875CzUfTKekHjA0pRMGJzARNFzc1fDz2+eGnfuXSrQtsHVFmxe/nOy2DiTeX 4CNXWMzyrEV/hnrrdd383hPU2dfRsXYBX/PCrqT0= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BELFV078330 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:21 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:20 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:20 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BEJ76026160; Wed, 5 Apr 2023 06:14:20 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 5/6] arm64: dts: ti: k3-j784s4-*: add DP & DP PHY Date: Wed, 5 Apr 2023 16:44:11 +0530 Message-ID: <20230405111412.151192-6-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041430_901608_5C28CF85 X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rahul T R Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add pinmux required for DP HPD. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 24 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index ccbfca76e9ae..2b414fd973d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -163,6 +163,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; }; &wkup_pmx0 { @@ -316,3 +322,21 @@ &dss { <&k3_clks 218 16>, <&k3_clks 218 22>; }; + +&serdes4 { + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 86ce6f6d4fc2..fc6071c16188 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1374,6 +1374,28 @@ main_spi7: spi@2170000 { status = "disabled"; }; + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + + reg = <0x0 0xa000000 0x0 0x30a00>, + <0x0 0x4f40000 0x0 0x20>; + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 217 11>; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + + status = "disabled"; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = From patchwork Wed Apr 5 11:14:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 13201636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8E68C76188 for ; Wed, 5 Apr 2023 11:15:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FcUeue7BcpmytGWH0KdxRNA9YgMdLGVFQhd6pKxXNK8=; b=fNWXBYWTibVoto 0UGdHaaT++IK6DXXo3j3JkKjubDi579u/+iC1q4aI7mRurBaLcX0UOfT3JltLz19315isKRxzRS3k XQPN3ImTWz5cfUe4WNvafcuYFrCwy5k2N2HiikeL4/ocKbruUmmqvwr/n6IPv6ZarFS7UQ9zkdlYu B4O8/Y0trqOlTfAeEX8Qv5usT28XcIuMe8IGo626HWaLUYdzVcGviUmB1VUDMkLPkhdu1A64KyOmJ ieJQ2rg5KLAEtANa9BZugaJdej+mzvU/eZFape01UekXY+6FnsxFuYjYtq4xwhXKlFss77lRcfRvS ks9kOScdyWCEDkqVIXog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pk165-004Dos-28; Wed, 05 Apr 2023 11:14:37 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pk15z-004DlF-29 for linux-arm-kernel@lists.infradead.org; Wed, 05 Apr 2023 11:14:33 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 335BEMNB019360; Wed, 5 Apr 2023 06:14:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680693262; bh=BRlbJsoQX8FM0khHXey+jJ5JONeai13EfiYLeaBfKNY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eSff4Eaxn78ul05w6vf89lkTujt43v1vAGU4+0872IwlIO+ZpBqgaqav2QL9Fdih7 wMqjdk1Pj4GeBIT8g/R60zcNDVgKtGJT+SB4cmN1WIn+UnWX9u77wHEdi1qDr6NKNP V7KJgfkNqNyOvHwASCNn/vG90h+agQptybrj9ajU= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 335BEMU3078340 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Apr 2023 06:14:22 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 5 Apr 2023 06:14:22 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 5 Apr 2023 06:14:22 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 335BELGm003818; Wed, 5 Apr 2023 06:14:21 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , Subject: [PATCH 6/6] arm64: dts: ti: k3-j784s4-evm: Add DP0 Date: Wed, 5 Apr 2023 16:44:12 +0530 Message-ID: <20230405111412.151192-7-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405111412.151192-1-j-choudhary@ti.com> References: <20230405111412.151192-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_041431_785412_BCCB6501 X-CRM114-Status: GOOD ( 11.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rahul T R Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required nodes gpio expander 4 and pinmux for main_i2c4 which is required for controlling DP Power and set status of all the required nodes for DP0 as okay Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 77 ++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 2b414fd973d0..03c9bf34cb1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -102,6 +102,28 @@ vdd_sd_dv: regulator-TLV71033 { states = <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -169,6 +191,13 @@ dp0_pins_default: dp0-pins-default { J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ >; }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; }; &wkup_pmx0 { @@ -313,6 +342,7 @@ &serdes_refclk { }; &dss { + status = "okay"; assigned-clocks = <&k3_clks 218 2>, <&k3_clks 218 5>, <&k3_clks 218 14>, @@ -323,7 +353,12 @@ &dss { <&k3_clks 218 22>; }; +&serdes_wiz4 { + status = "okay"; +}; + &serdes4 { + status = "okay"; serdes4_dp_link: phy@0 { reg = <0>; cdns,num-lanes = <4>; @@ -335,8 +370,50 @@ serdes4_dp_link: phy@0 { }; &mhdp { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dp0_pins_default>; phys = <&serdes4_dp_link>; phy-names = "dpphy"; }; + +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +};