From patchwork Sat Apr 8 03:47:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13205582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E194AC7619A for ; Sat, 8 Apr 2023 03:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229617AbjDHDuF (ORCPT ); Fri, 7 Apr 2023 23:50:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229454AbjDHDuD (ORCPT ); Fri, 7 Apr 2023 23:50:03 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45692CC13 for ; Fri, 7 Apr 2023 20:50:02 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id c193-20020a25c0ca000000b00b868826cdfeso18830709ybf.0 for ; Fri, 07 Apr 2023 20:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680925801; x=1683517801; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=+eQXKVk5bYBI9kU8FS6e9Eu8uo6AIYsLflVePzrnFLQ=; b=SvK9ArDgnmx3fnPqMxJtEL2EA8PQv5DaUsFb6ZhMPOQepiwwC73rxTSDunhfEkk/hU lIrPhL/eSC9EoyNsh2z9zTlSbXOc8aC1/gI0pXPrSjcY/WGhzGHiOZVJXXMH0Ne4Zm3Q woXlPoIZ/UBXaFlpUwYfR2e16fwzEEUkotPHhtuzo6vYP7RviWYk1/hG+eBoul5Cvqiw uw4a0Jx5+5Uzsbt2ouA3tcov2AMkRU42V3r4BS4uKeoppaj3o8Kh0J8mEY+kWv7f7a26 R0PWrAw6cB0T32t0JvK7/BT50X9Yzgu6qCZ7KGQ+eiL0FwPr39lUs0epEeITVdvkS8Th 69ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680925801; x=1683517801; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+eQXKVk5bYBI9kU8FS6e9Eu8uo6AIYsLflVePzrnFLQ=; b=iFlwd2R41Mr5j1M+K2CMk64431xM/O8rtTQzZGF1yAwBVHwMtB0Q7QBDy8UcFs30SF nn/yFQh2JsLtvcrxOZrcVeQtD7ZennXI5icqR9SddtvGOztdKXqMyDUP4LsZ1AWLIBaZ 0hp5JF6a9agCetJmT/uUSD1NkPvfpGmeEn3OvkxZE3pM/aQ1Olse2P3ezlni6NY06uPT ymbZ4g+ckx/cfGc5+N/183BvsKkWI9tuFvLkQP1tHKOx20Gu8vLZeMkXOf8vN4Ao+BjX C+es0Ere/8zvv9/UmM6JN/vsNs/rOmVKCZC+1YQ1/neth/xg56fi0yNXRvteYhou58XU JWCA== X-Gm-Message-State: AAQBX9cRgYXV7JKj4BAkyxAyLauT0Hhrs9ovcViQb3jbaPAO6MmS13jQ oJpsghgIzfOnGtUSo738zrGjVuyHKPc= X-Google-Smtp-Source: AKy350aQRt6i1U1RtZLFdPCYuwN2ajZD+RcM1fazysdk8uRYX0B7k4CJYjFtfCXeA2/8+WqTdrbecudjLxI= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a25:cfcf:0:b0:b8b:f1ac:9c6c with SMTP id f198-20020a25cfcf000000b00b8bf1ac9c6cmr3106735ybg.3.1680925801503; Fri, 07 Apr 2023 20:50:01 -0700 (PDT) Date: Fri, 7 Apr 2023 20:47:58 -0700 In-Reply-To: <20230408034759.2369068-1-reijiw@google.com> Mime-Version: 1.0 References: <20230408034759.2369068-1-reijiw@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Message-ID: <20230408034759.2369068-2-reijiw@google.com> Subject: [PATCH v2 1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 From: Reiji Watanabe To: Marc Zyngier , Mark Rutland , Oliver Upton , Will Deacon , Catalin Marinas , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restore the host's PMUSERENR_EL0 value instead of clearing it, before returning back to userspace, as the host's EL0 might have a direct access to PMU registers (some bits of PMUSERENR_EL0 for might not be zero for the host EL0). Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event") Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/hyp/include/hyp/switch.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 07d37ff88a3f..6718731729fd 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -81,7 +81,12 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) * EL1 instead of being trapped to EL2. */ if (kvm_arm_support_pmu_v3()) { + struct kvm_cpu_context *hctxt; + write_sysreg(0, pmselr_el0); + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0); write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); } @@ -105,8 +110,12 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); write_sysreg(0, hstr_el2); - if (kvm_arm_support_pmu_v3()) - write_sysreg(0, pmuserenr_el0); + if (kvm_arm_support_pmu_v3()) { + struct kvm_cpu_context *hctxt; + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0); + } if (cpus_have_final_cap(ARM64_SME)) { sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, From patchwork Sat Apr 8 03:47:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13205583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0876C77B6F for ; Sat, 8 Apr 2023 03:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229713AbjDHDuG (ORCPT ); Fri, 7 Apr 2023 23:50:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbjDHDuF (ORCPT ); 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Fri, 07 Apr 2023 20:50:03 -0700 (PDT) Date: Fri, 7 Apr 2023 20:47:59 -0700 In-Reply-To: <20230408034759.2369068-1-reijiw@google.com> Mime-Version: 1.0 References: <20230408034759.2369068-1-reijiw@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Message-ID: <20230408034759.2369068-3-reijiw@google.com> Subject: [PATCH v2 2/2] KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded From: Reiji Watanabe To: Marc Zyngier , Mark Rutland , Oliver Upton , Will Deacon , Catalin Marinas , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load(), and saves and restores the register value for the host on vcpu_load() and vcpu_put(). If the value of those bits are cleared on a pCPU with a vCPU loaded (armv8pmu_start() would do that when PMU counters are programmed for the guest), PMU access from the guest EL0 might be trapped to the guest EL1 directly regardless of the current PMUSERENR_EL0 value of the vCPU. Fix this by not letting armv8pmu_start() overwrite PMUSERENR on the pCPU on which a vCPU is loaded, and instead updating the saved shadow register value for the host, so that the value can be restored on vcpu_put() later. Suggested-by: Mark Rutland Suggested-by: Marc Zyngier Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event") Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 5 +++++ arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++++--- arch/arm64/kvm/pmu.c | 20 ++++++++++++++++++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index bcd774d74f34..22db2f885c17 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1028,9 +1028,14 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); #ifdef CONFIG_KVM void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); void kvm_clr_pmu_events(u32 clr); +bool kvm_set_pmuserenr(u64 val); #else static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} static inline void kvm_clr_pmu_events(u32 clr) {} +static inline bool kvm_set_pmuserenr(u64 val) +{ + return false; +} #endif void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index dde06c0f97f3..0fffe4c56c28 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -741,9 +741,25 @@ static inline u32 armv8pmu_getreset_flags(void) return value; } +static void update_pmuserenr(u64 val) +{ + lockdep_assert_irqs_disabled(); + + /* + * The current pmuserenr value might be the value for the guest. + * If that's the case, have KVM keep tracking of the register value + * for the host EL0 so that KVM can restore it before returning to + * the host EL0. Otherwise, update the register now. + */ + if (kvm_set_pmuserenr(val)) + return; + + write_sysreg(val, pmuserenr_el0); +} + static void armv8pmu_disable_user_access(void) { - write_sysreg(0, pmuserenr_el0); + update_pmuserenr(0); } static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) @@ -759,8 +775,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) armv8pmu_write_evcntr(i, 0); } - write_sysreg(0, pmuserenr_el0); - write_sysreg(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR, pmuserenr_el0); + update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); } static void armv8pmu_enable_event(struct perf_event *event) diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index 7887133d15f0..40bb2cb13317 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -209,3 +209,23 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) kvm_vcpu_pmu_enable_el0(events_host); kvm_vcpu_pmu_disable_el0(events_guest); } + +/* + * With VHE, keep track of the PMUSERENR_EL0 value for the host EL0 on + * the pCPU where vCPU is loaded, since PMUSERENR_EL0 is switched to + * the value for the guest on vcpu_load(). The value for the host EL0 + * will be restored on vcpu_put(), before returning to the EL0. + * + * Return true if KVM takes care of the register. Otherwise return false. + */ +bool kvm_set_pmuserenr(u64 val) +{ + struct kvm_cpu_context *hctxt; + + if (!kvm_arm_support_pmu_v3() || !has_vhe() || !kvm_get_running_vcpu()) + return false; + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + ctxt_sys_reg(hctxt, PMUSERENR_EL0) = val; + return true; +}