From patchwork Wed Apr 12 19:20:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 13209447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65466C7619A for ; Wed, 12 Apr 2023 19:23:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:From: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HSwKxRiHIea/lMNUV58KzHJTZHItHL+S1AUZuss1sVA=; b=s8ttQ1pVs908w2 sgIvi4kPVFZN/xwA8SumhkbiBOrhKinqLGZLEWO1lQ3GnT3bjYMZMGFB4UaUDSybnrq+Li/kqR/BE T5rvwcPce3G5OpkT+dFJuKh2xzAT3Ddf3RCRGgmcfu9PJCrPhtph8MRsY0XpDv9ioznUf4A93kv9O iX9iLVeJ0Nf5EElG27ElFIHGpnu6iDaXIx2pFunFjBwcEVQyMVWah8TphoMegnOWY8MAMmFBJlJ1F c767cEe2TULT/halYkAVqyhFrdS3k/Trja6DIwBdku/JE4slLolYAriJyiCdxUgyYddEy5Gj/iZJE sNRSLizZU1+gISaINxmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmg4D-004A69-1Z; Wed, 12 Apr 2023 19:23:41 +0000 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pmg49-004A4C-03; Wed, 12 Apr 2023 19:23:38 +0000 Received: by mail-ej1-x62a.google.com with SMTP id ud9so31351323ejc.7; Wed, 12 Apr 2023 12:23:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681327413; x=1683919413; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=6ruCafjyH/3zlOeY8HIt23X9tT9LTYcm24amx/aCjHg=; b=NInJHmo5GJ6LGF0P5Ez+b8s/XEnq2XPkad46wmzQwZ6PTlPpTzifRfDv5RUShBT8vR +ZCpzsFt+zmm3gY4xPr67LIaxTRan2Cw0w/+boQKu0m25t7oJgVQ8TpTvNt+YbE431J9 nzMvyXURMKrxVgoBETjFiiDSxQUhWo+kiJpFbx//d9ZXZ05lmOT1mDbRNUpun5jncRla VoUa8vewPb19Qsc/mukFUat+KzJHJ558lSjQLhdbhKf6CxrWPp05kQKKjRi9HXWnHwr9 AwbJGiRGJ6+HkIt/cCa/Cs7eM6PdrW7iqQnxxhIdsfToplUf4S8d7vyx0HFYmXsZMZpS en0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681327413; x=1683919413; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6ruCafjyH/3zlOeY8HIt23X9tT9LTYcm24amx/aCjHg=; b=hln+tTjngMyinpe9ANd3DumoNdgD8boBHm+EASNEgHbHk6xAtCMEUWelCXdaNV4UtL 7dStCGQJ0WjuEdSQ/Yl/mECyQ3AMOUIECs5T2W5CGJ+Hrc0aQckR3I5KstP5v8OD1GKb PVmgRUL5t9qQ9AT32NF11wh0XAB0HntKr0N5w39Kzbx050g+w0R633m3zSPhJ4sDYN3r Unfh54DiiifpdDtjP61KzzHMfX/93/mLd5xIylWHgYG7IEke1cR37bM69LemP6SdadEA ufWvvruOlUxDSohxIDIaxuTeMybhhNo1a/TkXLcouvtD8dcdA9MctI/xBxpEFgv0hDtk SDrw== X-Gm-Message-State: AAQBX9fNh3mo3A4IuXtD0wEnropQqBiNi7MXHokdbCpis0D1lPCxG4aG y/kfXcfLrr/OBy3svDt3ZcI= X-Google-Smtp-Source: AKy350ZaNzltKbVwQY5y4mdYzMETZFU620vKj2YBlg94g4V/1DYLl3tl/r9TkM4CqIyvyd5EOY4aXQ== X-Received: by 2002:a17:906:c78a:b0:947:eafc:a738 with SMTP id cw10-20020a170906c78a00b00947eafca738mr7066559ejb.60.1681327412903; Wed, 12 Apr 2023 12:23:32 -0700 (PDT) Received: from ?IPV6:2a02:3100:903d:3d00:b0e7:6bd7:f613:784b? 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[2a02:3100:903d:3d00:b0e7:6bd7:f613:784b]) by smtp.googlemail.com with ESMTPSA id f17-20020a170906739100b0094e5679dd2csm1134210ejl.165.2023.04.12.12.23.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 12:23:32 -0700 (PDT) Message-ID: <8a7c067d-b121-3bd0-b587-f53861b52bd5@gmail.com> Date: Wed, 12 Apr 2023 21:20:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: [PATCH v3 1/4] pwm: meson: switch to using struct clk_parent_data for mux parents Content-Language: en-US From: Heiner Kallweit To: Jerome Brunet , Martin Blumenstingl , Neil Armstrong , Kevin Hilman , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "thierry.reding@gmail.com" Cc: "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Amlogic Meson..." , linux-pwm@vger.kernel.org References: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> In-Reply-To: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230412_122337_055830_CD9A92F4 X-CRM114-Status: GOOD ( 12.49 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org We'll use struct clk_parent_data for mux/div/gate initialization in the follow-up patches. As a first step switch the mux from using parent_names to clk_parent_data. Suggested-by: Martin Blumenstingl Signed-off-by: Heiner Kallweit Reviewed-by: Martin Blumenstingl Tested-by: Martin Blumenstingl # --- v3: - move setting mux parent data out of the loop --- drivers/pwm/pwm-meson.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 4e5605c9d..6a66d5d58 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -61,6 +61,7 @@ #define MISC_A_EN BIT(0) #define MESON_NUM_PWMS 2 +#define MESON_MAX_MUX_PARENTS 4 static struct meson_pwm_channel_data { u8 reg_offset; @@ -484,21 +485,27 @@ MODULE_DEVICE_TABLE(of, meson_pwm_matches); static int meson_pwm_init_channels(struct meson_pwm *meson) { + struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; struct device *dev = meson->chip.dev; - struct clk_init_data init; unsigned int i; char name[255]; int err; + for (i = 0; i < meson->data->num_parents; i++) { + mux_parent_data[i].index = -1; + mux_parent_data[i].name = meson->data->parent_names[i]; + } + for (i = 0; i < meson->chip.npwm; i++) { struct meson_pwm_channel *channel = &meson->channels[i]; + struct clk_init_data init = {}; snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); init.name = name; init.ops = &clk_mux_ops; init.flags = 0; - init.parent_names = meson->data->parent_names; + init.parent_data = mux_parent_data; init.num_parents = meson->data->num_parents; channel->mux.reg = meson->base + REG_MISC_AB; From patchwork Wed Apr 12 19:21:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 13209449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EB28C77B72 for ; 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[2a02:3100:903d:3d00:b0e7:6bd7:f613:784b]) by smtp.googlemail.com with ESMTPSA id mb8-20020a170906eb0800b0094a9f434fc2sm3196299ejb.176.2023.04.12.12.23.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 12:23:33 -0700 (PDT) Message-ID: <8c6ac288-a59d-7c51-aced-3dbcfa828cdd@gmail.com> Date: Wed, 12 Apr 2023 21:21:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: [PATCH v3 2/4] pwm: meson: don't use hdmi/video clock as mux parent Content-Language: en-US From: Heiner Kallweit To: Jerome Brunet , Martin Blumenstingl , Neil Armstrong , Kevin Hilman , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "thierry.reding@gmail.com" Cc: "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Amlogic Meson..." , linux-pwm@vger.kernel.org References: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> In-Reply-To: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230412_122338_294870_AEFD4377 X-CRM114-Status: GOOD ( 11.27 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org meson_vclk may change the rate of the video clock. Therefore better don't use it as pwm mux parent. After removing this clock from the parent list pwm_gxbb_data and pwm_g12a_ee_data are the same as pwm_meson8b_data. So we can remove them. Reported-by: Martin Blumenstingl Signed-off-by: Heiner Kallweit Reviewed-by: Martin Blumenstingl --- drivers/pwm/pwm-meson.c | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 6a66d5d58..2a86867c1 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -371,7 +371,7 @@ static const struct pwm_ops meson_pwm_ops = { }; static const char * const pwm_meson8b_parent_names[] = { - "xtal", "vid_pll", "fclk_div4", "fclk_div3" + "xtal", NULL, "fclk_div4", "fclk_div3" }; static const struct meson_pwm_data pwm_meson8b_data = { @@ -379,15 +379,6 @@ static const struct meson_pwm_data pwm_meson8b_data = { .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), }; -static const char * const pwm_gxbb_parent_names[] = { - "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_gxbb_data = { - .parent_names = pwm_gxbb_parent_names, - .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names), -}; - /* * Only the 2 first inputs of the GXBB AO PWMs are valid * The last 2 are grounded @@ -437,15 +428,6 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_data = { .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), }; -static const char * const pwm_g12a_ee_parent_names[] = { - "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_g12a_ee_data = { - .parent_names = pwm_g12a_ee_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), -}; - static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -453,7 +435,7 @@ static const struct of_device_id meson_pwm_matches[] = { }, { .compatible = "amlogic,meson-gxbb-pwm", - .data = &pwm_gxbb_data + .data = &pwm_meson8b_data }, { .compatible = "amlogic,meson-gxbb-ao-pwm", @@ -469,7 +451,7 @@ static const struct of_device_id meson_pwm_matches[] = { }, { .compatible = "amlogic,meson-g12a-ee-pwm", - .data = &pwm_g12a_ee_data + .data = &pwm_meson8b_data }, { .compatible = "amlogic,meson-g12a-ao-pwm-ab", From patchwork Wed Apr 12 19:21:48 2023 Content-Type: text/plain; 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[2a02:3100:903d:3d00:b0e7:6bd7:f613:784b]) by smtp.googlemail.com with ESMTPSA id m9-20020a170906848900b00947a97a42f2sm7594773ejx.103.2023.04.12.12.23.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 12:23:35 -0700 (PDT) Message-ID: Date: Wed, 12 Apr 2023 21:21:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: [PATCH v3 3/4] pwm: meson: change clk/pwm gate from mask to bit Content-Language: en-US From: Heiner Kallweit To: Jerome Brunet , Martin Blumenstingl , Neil Armstrong , Kevin Hilman , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "thierry.reding@gmail.com" Cc: "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Amlogic Meson..." , linux-pwm@vger.kernel.org References: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> In-Reply-To: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230412_122337_375705_57045198 X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Change single-bit values from mask to bit. This facilitates CCF initialization for the clock gate in a follow-up patch. Signed-off-by: Heiner Kallweit Tested-by: Martin Blumenstingl # --- drivers/pwm/pwm-meson.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 2a86867c1..40a8709ff 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -49,16 +49,16 @@ #define PWM_HIGH_MASK GENMASK(31, 16) #define REG_MISC_AB 0x8 -#define MISC_B_CLK_EN BIT(23) -#define MISC_A_CLK_EN BIT(15) +#define MISC_B_CLK_EN 23 +#define MISC_A_CLK_EN 15 #define MISC_CLK_DIV_MASK 0x7f #define MISC_B_CLK_DIV_SHIFT 16 #define MISC_A_CLK_DIV_SHIFT 8 #define MISC_B_CLK_SEL_SHIFT 6 #define MISC_A_CLK_SEL_SHIFT 4 #define MISC_CLK_SEL_MASK 0x3 -#define MISC_B_EN BIT(1) -#define MISC_A_EN BIT(0) +#define MISC_B_EN 1 +#define MISC_A_EN 0 #define MESON_NUM_PWMS 2 #define MESON_MAX_MUX_PARENTS 4 @@ -67,22 +67,22 @@ static struct meson_pwm_channel_data { u8 reg_offset; u8 clk_sel_shift; u8 clk_div_shift; - u32 clk_en_mask; - u32 pwm_en_mask; + u8 clk_en_bit; + u8 pwm_en_bit; } meson_pwm_per_channel_data[MESON_NUM_PWMS] = { { .reg_offset = REG_PWM_A, .clk_sel_shift = MISC_A_CLK_SEL_SHIFT, .clk_div_shift = MISC_A_CLK_DIV_SHIFT, - .clk_en_mask = MISC_A_CLK_EN, - .pwm_en_mask = MISC_A_EN, + .clk_en_bit = MISC_A_CLK_EN, + .pwm_en_bit = MISC_A_EN, }, { .reg_offset = REG_PWM_B, .clk_sel_shift = MISC_B_CLK_SEL_SHIFT, .clk_div_shift = MISC_B_CLK_DIV_SHIFT, - .clk_en_mask = MISC_B_CLK_EN, - .pwm_en_mask = MISC_B_EN, + .clk_en_bit = MISC_B_CLK_EN, + .pwm_en_bit = MISC_B_EN, } }; @@ -231,7 +231,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) value = readl(meson->base + REG_MISC_AB); value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); value |= channel->pre_div << channel_data->clk_div_shift; - value |= channel_data->clk_en_mask; + value |= BIT(channel_data->clk_en_bit); writel(value, meson->base + REG_MISC_AB); value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | @@ -239,7 +239,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) writel(value, meson->base + channel_data->reg_offset); value = readl(meson->base + REG_MISC_AB); - value |= channel_data->pwm_en_mask; + value |= BIT(channel_data->pwm_en_bit); writel(value, meson->base + REG_MISC_AB); spin_unlock_irqrestore(&meson->lock, flags); @@ -253,7 +253,7 @@ static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm) spin_lock_irqsave(&meson->lock, flags); value = readl(meson->base + REG_MISC_AB); - value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask; + value &= ~BIT(meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_bit); writel(value, meson->base + REG_MISC_AB); spin_unlock_irqrestore(&meson->lock, flags); @@ -335,7 +335,7 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, value = readl(meson->base + REG_MISC_AB); - tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask; + tmp = BIT(channel_data->pwm_en_bit) | BIT(channel_data->clk_en_bit); state->enabled = (value & tmp) == tmp; tmp = value >> channel_data->clk_div_shift; From patchwork Wed Apr 12 19:23:04 2023 Content-Type: text/plain; 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[2a02:3100:903d:3d00:b0e7:6bd7:f613:784b]) by smtp.googlemail.com with ESMTPSA id u6-20020a50d506000000b004c13fe8fabfsm7147999edi.84.2023.04.12.12.23.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 12:23:36 -0700 (PDT) Message-ID: <12d4fbc1-8ed4-637e-32ca-2c09d25d60a6@gmail.com> Date: Wed, 12 Apr 2023 21:23:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: [PATCH v3 4/4] pwm: meson: make full use of common clock framework Content-Language: en-US From: Heiner Kallweit To: Jerome Brunet , Martin Blumenstingl , Neil Armstrong , Kevin Hilman , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "thierry.reding@gmail.com" Cc: "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Amlogic Meson..." , linux-pwm@vger.kernel.org References: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> In-Reply-To: <29973c8a-2b14-3d0c-bee8-8aff36c265e3@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230412_122338_507654_3310CC93 X-CRM114-Status: GOOD ( 31.51 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Newer versions of the PWM block use a core clock with external mux, divider, and gate. These components either don't exist any longer in the PWM block, or they are bypassed. To minimize needed changes for supporting the new version, the internal divider and gate should be handled by CCF too. I didn't see a good way to split the patch, therefore it's somewhat bigger. What it does: - The internal mux is handled by CCF already. Register also internal divider and gate with CCF, so that we have one representation of the input clock: [mux] parent of [divider] parent of [gate] - Now that CCF selects an appropriate mux parent, we don't need the DT-provided default parent any longer. Accordingly we can also omit setting the mux parent directly in the driver. - Instead of manually handling the pre-div divider value, let CCF set the input clock. Targeted input clock frequency is 0xffff * 1/period for best precision. - For the "inverted pwm disabled" scenario target an input clock frequency of 1GHz. This ensures that the remaining low pulses have minimum length. I don't have hw with the old PWM block, therefore I couldn't test this patch. With the not yet included extension for the new PWM block (channel->clock directly coming from get_clk(external_clk)) I didn't notice any problem. My system uses PWM for the CPU voltage regulator and for the SDIO 32kHz clock. Note: The clock gate in the old PWM block is permanently disabled. This seems to indicate that it's not used by the new PWM block. Signed-off-by: Heiner Kallweit Tested-by: Martin Blumenstingl # --- Changes to RFT/RFC version: - use parent_hws instead of parent_names for div/gate clock - use devm_clk_hw_register where the struct clk * returned by devm_clk_register isn't needed v2: - add patch 1 - add patch 3 - switch to using clk_parent_data in all relevant places v3: - add flag CLK_IGNORE_UNUSED --- drivers/pwm/pwm-meson.c | 134 +++++++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 58 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 40a8709ff..6d401fd0d 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -51,7 +51,7 @@ #define REG_MISC_AB 0x8 #define MISC_B_CLK_EN 23 #define MISC_A_CLK_EN 15 -#define MISC_CLK_DIV_MASK 0x7f +#define MISC_CLK_DIV_WIDTH 7 #define MISC_B_CLK_DIV_SHIFT 16 #define MISC_A_CLK_DIV_SHIFT 8 #define MISC_B_CLK_SEL_SHIFT 6 @@ -87,12 +87,13 @@ static struct meson_pwm_channel_data { }; struct meson_pwm_channel { + unsigned long rate; unsigned int hi; unsigned int lo; - u8 pre_div; - struct clk *clk_parent; struct clk_mux mux; + struct clk_divider div; + struct clk_gate gate; struct clk *clk; }; @@ -125,16 +126,6 @@ static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) struct device *dev = chip->dev; int err; - if (channel->clk_parent) { - err = clk_set_parent(channel->clk, channel->clk_parent); - if (err < 0) { - dev_err(dev, "failed to set parent %s for %s: %d\n", - __clk_get_name(channel->clk_parent), - __clk_get_name(channel->clk), err); - return err; - } - } - err = clk_prepare_enable(channel->clk); if (err < 0) { dev_err(dev, "failed to enable clock %s: %d\n", @@ -157,8 +148,9 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, const struct pwm_state *state) { struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; - unsigned int duty, period, pre_div, cnt, duty_cnt; + unsigned int duty, period, cnt, duty_cnt; unsigned long fin_freq; + u64 freq; duty = state->duty_cycle; period = state->period; @@ -166,7 +158,11 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, if (state->polarity == PWM_POLARITY_INVERSED) duty = period - duty; - fin_freq = clk_get_rate(channel->clk); + freq = div64_u64(NSEC_PER_SEC * (u64)0xffff, period); + if (freq > ULONG_MAX) + freq = ULONG_MAX; + + fin_freq = clk_round_rate(channel->clk, freq); if (fin_freq == 0) { dev_err(meson->chip.dev, "invalid source clock frequency\n"); return -EINVAL; @@ -174,46 +170,35 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); - pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); - if (pre_div > MISC_CLK_DIV_MASK) { - dev_err(meson->chip.dev, "unable to get period pre_div\n"); - return -EINVAL; - } - - cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); + cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC); if (cnt > 0xffff) { dev_err(meson->chip.dev, "unable to get period cnt\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, - pre_div, cnt); + dev_dbg(meson->chip.dev, "period=%u cnt=%u\n", period, cnt); if (duty == period) { - channel->pre_div = pre_div; channel->hi = cnt; channel->lo = 0; } else if (duty == 0) { - channel->pre_div = pre_div; channel->hi = 0; channel->lo = cnt; } else { - /* Then check is we can have the duty with the same pre_div */ - duty_cnt = div64_u64(fin_freq * (u64)duty, - NSEC_PER_SEC * (pre_div + 1)); + duty_cnt = div64_u64(fin_freq * (u64)duty, NSEC_PER_SEC); if (duty_cnt > 0xffff) { dev_err(meson->chip.dev, "unable to get duty cycle\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", - duty, pre_div, duty_cnt); + dev_dbg(meson->chip.dev, "duty=%u duty_cnt=%u\n", duty, duty_cnt); - channel->pre_div = pre_div; channel->hi = duty_cnt; channel->lo = cnt - duty_cnt; } + channel->rate = fin_freq; + return 0; } @@ -223,16 +208,15 @@ static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) struct meson_pwm_channel_data *channel_data; unsigned long flags; u32 value; + int err; channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; - spin_lock_irqsave(&meson->lock, flags); + err = clk_set_rate(channel->clk, channel->rate); + if (err) + dev_err(meson->chip.dev, "setting clock rate failed\n"); - value = readl(meson->base + REG_MISC_AB); - value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); - value |= channel->pre_div << channel_data->clk_div_shift; - value |= BIT(channel_data->clk_en_bit); - writel(value, meson->base + REG_MISC_AB); + spin_lock_irqsave(&meson->lock, flags); value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | FIELD_PREP(PWM_LOW_MASK, channel->lo); @@ -271,16 +255,16 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* * This IP block revision doesn't have an "always high" * setting which we can use for "inverted disabled". - * Instead we achieve this using the same settings - * that we use a pre_div of 0 (to get the shortest - * possible duration for one "count") and + * Instead we achieve this by setting an arbitrary, + * very high frequency, resulting in the shortest + * possible duration for one "count" and * "period == duty_cycle". This results in a signal * which is LOW for one "count", while being HIGH for * the rest of the (so the signal is HIGH for slightly * less than 100% of the period, but this is the best * we can achieve). */ - channel->pre_div = 0; + channel->rate = 1000000000; channel->hi = ~0; channel->lo = 0; @@ -305,7 +289,6 @@ static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct meson_pwm *meson = to_meson_pwm(chip); struct meson_pwm_channel *channel; unsigned long fin_freq; - u32 fin_ns; /* to_meson_pwm() can only be used after .get_state() is called */ channel = &meson->channels[pwm->hwpwm]; @@ -314,9 +297,7 @@ static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip, if (fin_freq == 0) return 0; - fin_ns = div_u64(NSEC_PER_SEC, fin_freq); - - return cnt * fin_ns * (channel->pre_div + 1); + return div_u64(NSEC_PER_SEC * (u64)cnt, fin_freq); } static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, @@ -335,11 +316,8 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, value = readl(meson->base + REG_MISC_AB); - tmp = BIT(channel_data->pwm_en_bit) | BIT(channel_data->clk_en_bit); - state->enabled = (value & tmp) == tmp; - - tmp = value >> channel_data->clk_div_shift; - channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp); + tmp = BIT(channel_data->pwm_en_bit); + state->enabled = __clk_is_enabled(channel->clk) && (value & tmp) == tmp; value = readl(meson->base + channel_data->reg_offset); @@ -480,6 +458,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) for (i = 0; i < meson->chip.npwm; i++) { struct meson_pwm_channel *channel = &meson->channels[i]; + struct clk_parent_data div_parent = {}, gate_parent = {}; struct clk_init_data init = {}; snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); @@ -499,18 +478,57 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) channel->mux.table = NULL; channel->mux.hw.init = &init; - channel->clk = devm_clk_register(dev, &channel->mux.hw); - if (IS_ERR(channel->clk)) { - err = PTR_ERR(channel->clk); + err = devm_clk_hw_register(dev, &channel->mux.hw); + if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } - snprintf(name, sizeof(name), "clkin%u", i); + snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); + + init.name = name; + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + div_parent.index = -1; + div_parent.hw = &channel->mux.hw; + init.parent_data = &div_parent; + init.num_parents = 1; + + channel->div.reg = meson->base + REG_MISC_AB; + channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift; + channel->div.width = MISC_CLK_DIV_WIDTH; + channel->div.hw.init = &init; + channel->div.flags = 0; + channel->div.lock = &meson->lock; + + err = devm_clk_hw_register(dev, &channel->div.hw); + if (err) { + dev_err(dev, "failed to register %s: %d\n", name, err); + return err; + } - channel->clk_parent = devm_clk_get_optional(dev, name); - if (IS_ERR(channel->clk_parent)) - return PTR_ERR(channel->clk_parent); + snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); + + init.name = name; + init.ops = &clk_gate_ops; + init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; + gate_parent.index = -1; + gate_parent.hw = &channel->div.hw; + init.parent_data = &gate_parent; + init.num_parents = 1; + + channel->gate.reg = meson->base + REG_MISC_AB; + channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_bit; + channel->gate.hw.init = &init; + channel->gate.flags = 0; + channel->gate.lock = &meson->lock; + + channel->clk = devm_clk_register(dev, &channel->gate.hw); + if (IS_ERR(channel->clk)) { + err = PTR_ERR(channel->clk); + dev_err(dev, "failed to register %s: %d\n", name, err); + return err; + } } return 0;