From patchwork Thu Apr 13 16:49:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13210453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89075C77B61 for ; Thu, 13 Apr 2023 16:49:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B81C10E294; Thu, 13 Apr 2023 16:49:41 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49E6F10E086; Thu, 13 Apr 2023 16:49:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681404579; x=1712940579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e16JYrNG13ZK09W8a6cvMfAnKuNMv4L12FVaChTOJe0=; b=akRz2JXpfMRtD20cuemNL/C0x0Dzw7BiZdZeLdXgM4xCmzI8Anlm7bxb DAUhZz9NU6/ve/iO3UnrKMv6KAcoSd0sEYQuh2njzEdeGmDBzvz2s9sQw nCAE1BJVVrgWE6LmS/kgEbqaPRyJ5PNqBum9L89Gc96v9EnHRlgoJXYMh Zhf4Nv6a9svApqDqOniYfpPy4GOfnOOAPlRDo4LEdWpJ2728aBqgvGyES Rf5ei4Ff2G259kpTkrIteaRIiAx3UnVSQ/yyF8FIweeIKEwbuTO6it0Dr UdqG+S9Ac3lYAHwytnaHIEUCAgpd82CpQvU778uPmo5L0umRyoGn2sMZy A==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="342991055" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="342991055" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 09:49:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="692037916" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="692037916" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2023 09:49:20 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:19 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 1/7] drm/uapi: Document CTM matrix better Date: Thu, 13 Apr 2023 19:49:10 +0300 Message-Id: <20230413164916.4221-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä Document in which order the CTM matrix elements are stored. Signed-off-by: Ville Syrjälä --- include/uapi/drm/drm_mode.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 46becedf5b2f..43691058d28f 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -834,6 +834,11 @@ struct drm_color_ctm { /* * Conversion matrix in S31.32 sign-magnitude * (not two's complement!) format. + * + * out matrix in + * |R| |0 1 2| |R| + * |G| = |3 4 5| x |G| + * |B| |6 7 8| |B| */ __u64 matrix[9]; }; From patchwork Thu Apr 13 16:49:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13210455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05C92C77B6E for ; Thu, 13 Apr 2023 16:49:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0C9710EB90; Thu, 13 Apr 2023 16:49:45 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 576ED10E086; Thu, 13 Apr 2023 16:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681404580; x=1712940580; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VO+hzf+JZT0LDwb9AwFVSgz/6tqEyB7SG90J+rO9ms0=; b=Uy60H/tBh3P2y4ldI/zsxQEcFyjexd7vu6PoDQF14KoIg4i7IqimGdrH U7WQt3wjJxiYGEXGkTu4bwP4e7ZmTqA2Rxvt0KqgrT0bqXl8gqXiUCEob kCH7mppGM8bfNDfAVAufieTAgFrQK+RQ9QkzpM6yj/BXPag7BdLgH0QLV MXVDTJt50zUATdK18MTiPGIb0rbAgJuVhUydUHv36YNTo2Yn169icCOdS NTkosRQrUqIBFZAslENU18+wbiW+oH6N6JIJVexIEd02JwIqA4J6NkxsK JhSRhkSrJmStVq7Zbe43YXPHypE+cC1m2/JuejE2r7N2QcByRtX6wZtMh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="342991073" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="342991073" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 09:49:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="692037919" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="692037919" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2023 09:49:23 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:22 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb Date: Thu, 13 Apr 2023 19:49:11 +0300 Message-Id: <20230413164916.4221-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä The ilk/snb code is internally fully capable of handling the CTM property, so expose it. Note that we still choose not to expose DEGAMMA_LUT though. The hardware is capable if degamma or gamma, but not both similtanously due to lack of the split gamma mode. Exposing both LUTs might encourage userspace to try enabling both at the same time. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 07f1afe1d406..4fc16cac052d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc) gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; - has_ctm = degamma_lut_size != 0; + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915); /* * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the From patchwork Thu Apr 13 16:49:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13210454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28D62C77B73 for ; Thu, 13 Apr 2023 16:49:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3EC110EB8D; Thu, 13 Apr 2023 16:49:45 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA5F410E380; Thu, 13 Apr 2023 16:49:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681404581; x=1712940581; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xt8zT1YZRdFHhWLsgQphruGj5/L9fb/AakwpLz1znqY=; b=mCT/P9uxAxcjfX5eWjWFK2ADjiYnYK6WqHI2JBhUwpY9vqs/J8ir6Jwf +xEP0muFmxSMCLlw4Nh7KhUrSLcTQxQAe+O+Aa5wKXQfp6WJ4VAHmjwBq JlF9fnmDBvNANFoTGpzWRUZ4Mp6zIwOkM5tF6CEX0B0VBrJcqYmURhhfJ IpJJg/yCtsx2SGL+osflIsT2TcmhHVPDlcaIkrjIUYjGG+FDgW5kSJTL9 iU8hvsOPxbgEJ0l7CdzquebAFgtb+voBaTr/INevGTBNDb+tyQZNBl+S0 5NjsGQc2mCrHQPkGFhTK2Z1nPPDFfPua4K3MYAIPXJiQ46Qm2e9a9KA75 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="342991084" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="342991084" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 09:49:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="692037930" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="692037930" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2023 09:49:26 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:25 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling Date: Thu, 13 Apr 2023 19:49:12 +0300 Message-Id: <20230413164916.4221-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM->CGM conversion to handle that correctly instead of pretending that the hw coefficients are also in some sign-magnitude format. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++-------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4fc16cac052d..63141f4ed372 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) icl_update_output_csc(crtc, &crtc_state->output_csc); } +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits) +{ + s64 c = CTM_COEFF_ABS(coeff); + + /* leave an extra bit for rounding */ + c >>= 32 - frac_bits - 1; + + /* round and drop the extra bit */ + c = (c + 1) >> 1; + + if (CTM_COEFF_NEGATIVE(coeff)) + c = -c; + + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1), + (s64)(BIT(int_bits + frac_bits - 1) - 1)); + + return c & (BIT(int_bits + frac_bits) - 1); +} + +/* + * CHV Color Gamut Mapping (CGM) CSC + * |r| | c0 c1 c2 | |r| + * |g| = | c3 c4 c5 | x |g| + * |b| | c6 c7 c8 | |b| + * + * Coefficients are two's complement s4.12. + */ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state, struct intel_csc_matrix *csc) { const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; int i; - for (i = 0; i < 9; i++) { - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; - - /* Round coefficient. */ - abs_coeff += 1 << (32 - 13); - /* Clamp to hardware limits. */ - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); - - csc->coeff[i] = 0; - - /* Write coefficients in S3.12 format. */ - if (ctm->matrix[i] & (1ULL << 63)) - csc->coeff[i] |= 1 << 15; - - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12; - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff; - } + for (i = 0; i < 9; i++) + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12); } static void chv_load_cgm_csc(struct intel_crtc *crtc, From patchwork Thu Apr 13 16:49:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13210456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEEA7C77B71 for ; Thu, 13 Apr 2023 16:49:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB4F010EB95; Thu, 13 Apr 2023 16:49:46 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 875A710E380; Thu, 13 Apr 2023 16:49:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681404582; x=1712940582; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xUlOujp3VBoiGcCZqWhzgbXO97qHTua64Yy9wHHgCSs=; b=PslrpN4UWlgquiwONI/ihNCpME7AE06BE8FZzMiexvWq6mEiFJs+Wc39 kUmxaoMBQqyehoxIxlLIj2aciHVHPBdBwDSWT1dJ9sbqxtcJgpfX2u0HM Yc/FVCEYjvvEDfCZpyeOoXQJz5x2AyevcB2k3ZnAF51PswIC2sWvGZ91A qItb5bqjF2RjXXKFGHw4dwfeljxIP9hGMwmOONXv5V7bd7jeUeuqrteO/ b1IclS88thHgArH5oSw56C7PlM21vun+r2BtCGtkJa+qT8YvO1yOERGfw ofx/VplnBna98aa34j41zLf6IWlLXzLM49FLFtxr97VUdcRorWCIr2Jfh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="342991103" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="342991103" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 09:49:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="692037932" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="692037932" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2023 09:49:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:28 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV Date: Thu, 13 Apr 2023 19:49:13 +0300 Message-Id: <20230413164916.4221-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä On CHV toggling the CGM CSC on/off while the pipe is running leads to underruns. Looks like we'd have to do the toggling strictly inside the start_of_vblank-frame_start window to avoid this, but that window is less than a scanline so there's no way we can guarantee hitting it. As a workaround let's just leave the CGM CSC permanently enabled. Fortunately the CGM gamma/degamma units don't seem to suffer from this malady. I also tried turning off CGM unit clock gating, but that did not help. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 63141f4ed372..7a705e7d8776 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state, csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12); } +#define CHV_CGM_CSC_COEFF_1_0 (1 << 12) + +static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = { + .coeff = { + CHV_CGM_CSC_COEFF_1_0, 0, 0, + 0, CHV_CGM_CSC_COEFF_1_0, 0, + 0, 0, CHV_CGM_CSC_COEFF_1_0, + }, +}; + static void chv_load_cgm_csc(struct intel_crtc *crtc, const struct intel_csc_matrix *csc) { @@ -667,9 +677,9 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state) chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc); } else { - drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) != 0); + drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0); - intel_csc_clear(&crtc_state->csc); + crtc_state->csc = chv_cgm_csc_matrix_identity; } } @@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) !lut_is_legacy(crtc_state->hw.gamma_lut)) cgm_mode |= CGM_PIPE_MODE_GAMMA; + /* + * Toggling the CGM CSC on/off outside of the tiny window + * between start of vblank and frame start causes underruns. + * Always enable the CGM CSC as a workaround. + */ + cgm_mode |= CGM_PIPE_MODE_CSC; + return cgm_mode; } From patchwork Thu Apr 13 16:49:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13210457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8EB4C77B6E for ; Thu, 13 Apr 2023 16:49:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 74AC710EB92; Thu, 13 Apr 2023 16:49:47 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A45610EB90; Thu, 13 Apr 2023 16:49:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681404584; x=1712940584; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NlYVoYJTuZFSAx8XfiGJZwoH1fmyWOAHEqRQSyT92/Q=; b=JP3XfAAVcydkDLJ47gGAGs6mKNyp8YBJr/SbOWPpKd+8K85yS5/eXVyt TltYVA+IhfHCtqRsY1/rKrSSF2wBqy8YX96PjKyJN5fERGKEI/7Ncuy8K hQ0MB7aA54Gxk6WW63RKEKBYFg3wDJ6wRBfeGmD1scCq1PLf1kNS2Bnzz qO+roHFqgG177UcQH45XLXy52LMU1WOE+4PExrDKTKMycHC+7l49g0nnM V4h5teF3Pnxq3/YXau2o5S8qVdxsoneeyHldASShzxBa9PA/TBqA6zPbC GzLI4ZeqovQdN/NBPliQe5p0WA0cCL6YRXvtyiWSHC2bHdDcLpEgM7u9D g==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="342991123" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="342991123" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 09:49:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="692037949" X-IronPort-AV: E=Sophos;i="5.99,194,1677571200"; d="scan'208";a="692037949" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2023 09:49:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV Date: Thu, 13 Apr 2023 19:49:14 +0300 Message-Id: <20230413164916.4221-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä VLV has a so called "wide gamut color correction" unit (WGC). What it is is a 3x3 matrix similar to the later CHV CGM CSC, which less precisions/range. In fact CHV also has the WGC but using it there doesn't reall make sense when you have the superior CGM CSC around. Hook up the necessary stuff to expose the WGC as the CTM crtc property. One additional crazy idea that came to mind would be to use the WGC as an output CSC on CHV for YCbCr output. But it would be incompatible with the legacy LUT usage. In fact since the WGC lacks post-offsets we'd probably have to use the legacy LUT to do that final part of the RGB->YCbCr conversion. Sounds doable, but perhaps not worth the hassle. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++- .../drm/i915/display/intel_crtc_state_dump.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 8 + .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 15 ++ 5 files changed, 198 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7a705e7d8776..e36d8c248b84 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits) return c & (BIT(int_bits + frac_bits) - 1); } +/* + * VLV/CHV Wide Gamut Color Correction (WGC) CSC + * |r| | c0 c1 c2 | |r| + * |g| = | c3 c4 c5 | x |g| + * |b| | c6 c7 c8 | |b| + * + * Coefficients are two's complement s2.10. + */ +static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state, + struct intel_csc_matrix *csc) +{ + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; + int i; + + for (i = 0; i < 9; i++) + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10); +} + +static void vlv_load_wgc_csc(struct intel_crtc *crtc, + const struct intel_csc_matrix *csc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe), + csc->coeff[1] << 16 | csc->coeff[0]); + intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe), + csc->coeff[2]); + + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe), + csc->coeff[4] << 16 | csc->coeff[3]); + intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe), + csc->coeff[5]); + + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe), + csc->coeff[7] << 16 | csc->coeff[6]); + intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe), + csc->coeff[8]); +} + +static void vlv_read_wgc_csc(struct intel_crtc *crtc, + struct intel_csc_matrix *csc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + u32 tmp; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe)); + csc->coeff[0] = tmp & 0xffff; + csc->coeff[1] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe)); + csc->coeff[2] = tmp & 0xffff; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe)); + csc->coeff[3] = tmp & 0xffff; + csc->coeff[4] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe)); + csc->coeff[5] = tmp & 0xffff; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe)); + csc->coeff[6] = tmp & 0xffff; + csc->coeff[7] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe)); + csc->coeff[8] = tmp & 0xffff; +} + +static void vlv_read_csc(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (crtc_state->wgc_enable) + vlv_read_wgc_csc(crtc, &crtc_state->csc); +} + +static void vlv_assign_csc(struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (crtc_state->hw.ctm) { + drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable); + + vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc); + } else { + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable); + + intel_csc_clear(&crtc_state->csc); + } +} + /* * CHV Color Gamut Mapping (CGM) CSC * |r| | c0 c1 c2 | |r| @@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable); + if (crtc_state->hw.ctm) { drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0); @@ -1574,6 +1668,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) } } +static void vlv_load_luts(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (crtc_state->wgc_enable) + vlv_load_wgc_csc(crtc, &crtc_state->csc); + + i965_load_luts(crtc_state); +} + static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) { return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) | @@ -1728,6 +1832,18 @@ static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state !old_crtc_state->pre_csc_lut; } +static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); + struct intel_atomic_state *state = + to_intel_atomic_state(new_crtc_state->uapi.state); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + + return !old_crtc_state->wgc_enable && + !old_crtc_state->post_csc_lut; +} + static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); @@ -1744,7 +1860,7 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) return false; - return !old_crtc_state->post_csc_lut; + return vlv_can_preload_luts(new_crtc_state); } int intel_color_check(struct intel_crtc_state *crtc_state) @@ -2031,6 +2147,39 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) return 0; } +/* + * VLV color pipeline: + * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 + */ +static int vlv_color_check(struct intel_crtc_state *crtc_state) +{ + int ret; + + ret = check_luts(crtc_state); + if (ret) + return ret; + + crtc_state->gamma_enable = + crtc_state->hw.gamma_lut && + !crtc_state->c8_planes; + + crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); + + crtc_state->wgc_enable = crtc_state->hw.ctm; + + ret = intel_color_add_affected_planes(crtc_state); + if (ret) + return ret; + + intel_assign_luts(crtc_state); + + vlv_assign_csc(crtc_state); + + crtc_state->preload_luts = vlv_can_preload_luts(crtc_state); + + return 0; +} + static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) { u32 cgm_mode = 0; @@ -2081,6 +2230,12 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) crtc_state->cgm_mode = chv_cgm_mode(crtc_state); + /* + * We always bypass the WGC CSC and use the CGM CSC + * instead since it has degamma and better precision. + */ + crtc_state->wgc_enable = false; + ret = intel_color_add_affected_planes(crtc_state); if (ret) return ret; @@ -3395,6 +3550,15 @@ static const struct intel_color_funcs chv_color_funcs = { .read_csc = chv_read_csc, }; +static const struct intel_color_funcs vlv_color_funcs = { + .color_check = vlv_color_check, + .color_commit_arm = i9xx_color_commit_arm, + .load_luts = vlv_load_luts, + .read_luts = i965_read_luts, + .lut_equal = i965_lut_equal, + .read_csc = vlv_read_csc, +}; + static const struct intel_color_funcs i965_color_funcs = { .color_check = i9xx_color_check, .color_commit_arm = i9xx_color_commit_arm, @@ -3502,7 +3666,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc) gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; - has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915); + has_ctm = DISPLAY_VER(i915) >= 5; /* * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the @@ -3540,6 +3704,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915) if (HAS_GMCH(i915)) { if (IS_CHERRYVIEW(i915)) i915->display.funcs.color = &chv_color_funcs; + else if (IS_VALLEYVIEW(i915)) + i915->display.funcs.color = &vlv_color_funcs; else if (DISPLAY_VER(i915) >= 4) i915->display.funcs.color = &i965_color_funcs; else diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 0cdcaa49656f..dd0895b24682 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char *name, } static void -chv_dump_csc(struct drm_i915_private *i915, const char *name, +vlv_dump_csc(struct drm_i915_private *i915, const char *name, const struct intel_csc_matrix *csc) { int i; @@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, if (!HAS_GMCH(i915)) ilk_dump_csc(i915, "pipe csc", &pipe_config->csc); else if (IS_CHERRYVIEW(i915)) - chv_dump_csc(i915, "cgm csc", &pipe_config->csc); + vlv_dump_csc(i915, "cgm csc", &pipe_config->csc); + else if (IS_VALLEYVIEW(i915)) + vlv_dump_csc(i915, "wgc csc", &pipe_config->csc); dump_planes: if (!state) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0334565cec82..962bbd13a5bf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2931,6 +2931,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); + if (crtc_state->wgc_enable) + val |= TRANSCONF_WGC_ENABLE; + val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); @@ -3123,6 +3126,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + (tmp & TRANSCONF_WGC_ENABLE)) + pipe_config->wgc_enable = true; + if (IS_CHERRYVIEW(dev_priv)) pipe_config->cgm_mode = intel_de_read(dev_priv, CGM_PIPE_MODE(crtc->pipe)); @@ -5711,6 +5718,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_X(csc_mode); PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + PIPE_CONF_CHECK_BOOL(wgc_enable); PIPE_CONF_CHECK_I(linetime); PIPE_CONF_CHECK_I(ips_linetime); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b28c8dc48e24..5357664cdf55 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1295,6 +1295,9 @@ struct intel_crtc_state { /* enable pipe csc? */ bool csc_enable; + /* enable vlv/chv wgc csc? */ + bool wgc_enable; + /* big joiner pipe bitmask */ u8 bigjoiner_pipes; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e9dd19cc66a2..e1a6ba6839b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2550,6 +2550,7 @@ #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ @@ -6382,6 +6383,20 @@ enum skl_power_gate { (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ (index) * 4) +#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */ +#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */ +#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */ +#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */ +#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */ +#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */ + +#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00) +#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02) +#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10) +#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12) +#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20) +#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Thu Apr 13 16:49:15 2023 Content-Type: text/plain; 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13 Apr 2023 09:49:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts Date: Thu, 13 Apr 2023 19:49:15 +0300 Message-Id: <20230413164916.4221-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop claiming otherwise. As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can be set but it has no effect on the output. PNV seems to be the only slight exception, but generally the desktop PNV variant looks more like a mobile part so this is not entirely surprising. Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3") Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/i915_pci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index cddb6e197972..305c05c3f93b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = { .dma_mask_size = 32, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ - I9XX_COLORS, \ GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS static const struct intel_device_info i915g_info = { GEN3_FEATURES, PLATFORM(INTEL_I915G), + I845_COLORS, .has_coherent_ggtt = false, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static const struct intel_device_info i915gm_info = { GEN3_FEATURES, PLATFORM(INTEL_I915GM), + I9XX_COLORS, .is_mobile = 1, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static const struct intel_device_info i945g_info = { GEN3_FEATURES, PLATFORM(INTEL_I945G), + I845_COLORS, .display.has_hotplug = 1, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static const struct intel_device_info i945gm_info = { GEN3_FEATURES, PLATFORM(INTEL_I945GM), + I9XX_COLORS, .is_mobile = 1, .display.has_hotplug = 1, .display.cursor_needs_physical = 1, @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static const struct intel_device_info g33_info = { GEN3_FEATURES, PLATFORM(INTEL_G33), + I845_COLORS, .display.has_hotplug = 1, .display.has_overlay = 1, .dma_mask_size = 36, @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static const struct intel_device_info pnv_g_info = { GEN3_FEATURES, PLATFORM(INTEL_PINEVIEW), + I9XX_COLORS, .display.has_hotplug = 1, .display.has_overlay = 1, .dma_mask_size = 36, @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static const struct intel_device_info pnv_m_info = { GEN3_FEATURES, PLATFORM(INTEL_PINEVIEW), + I9XX_COLORS, .is_mobile = 1, .display.has_hotplug = 1, .display.has_overlay = 1, From patchwork Thu Apr 13 16:49:16 2023 Content-Type: text/plain; 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13 Apr 2023 09:49:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Apr 2023 19:49:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 7/7] drm/i915: Do state check for color management changes Date: Thu, 13 Apr 2023 19:49:16 +0300 Message-Id: <20230413164916.4221-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413164916.4221-1-ville.syrjala@linux.intel.com> References: <20230413164916.4221-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä In order to validate LUT programming more thoroughly let's do a state check for all color management updates as well. Not sure we really want this outside CI. It is rather heavy and color management updates could become rather common with all the HDR/etc. stuff happening. Maybe we should have an extra knob for this that we could enable in CI? v2: Skip for initial_commit to avoid FDI dotclock sanity checks/etc. tripping up Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 842d70f0dfd2..9e4767e1b900 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc, struct intel_crtc_state *new_crtc_state) { if (!intel_crtc_needs_modeset(new_crtc_state) && + (!intel_crtc_needs_color_update(new_crtc_state) || + new_crtc_state->inherited) && !intel_crtc_needs_fastset(new_crtc_state)) return;