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Thu, 13 Apr 2023 17:44:57 -0700 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [V6 1/9] MAINTAINERS: Add HTE/timestamp subsystem details Date: Thu, 13 Apr 2023 17:44:47 -0700 Message-ID: <20230414004455.19275-2-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230414004455.19275-1-dipenp@nvidia.com> References: <20230414004455.19275-1-dipenp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: timestamp@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT024:EE_|SA0PR12MB4447:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f2fafd5-cc6b-4a2c-a400-08db3c817fd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dtvK7lrHedLlSn2CQq3DykfaVuGR6cYsZa3JFUdzRJKRZJItsvauMoXG/TD5iMaHL7S0u9GoLDwK/i35tPtOS0IbdzjjBPiTfM84963T8kaJGpbQRUfpSrl//LbudraA62R0KoS30JLjvJEMHwx0tP2YjNHOawUnQe3pTcB+3Pthds3Mye2ZVSLch1OyJQsTEtM+oKgSQ96rA5P6x+o4vvm414YREJ4VhP5EWdLMjtRrwza2JQgBfabIwTTwNCJd2UNZNh1vpSlQq0t0zje8meikemyk0rGKQ+RbRx3uZ5JCrz2/3J4qtuJer0Yx6w9/ZUKMYC9oUI4l6TMiOF0aV/KyzuAHgRCuxu8AjcLwRrhzTCmaMJKGnUjh5CW3ZfFR4LCXnQtWDLFGVrw0AYaZ/pu51Fypqt1C+WRQVGexDmuDe+6z2TEWNsQy7e+c8WLZoBko/qGkqj/1bfOJJ3H792rwmBDaDochxymrJhNfySRUKG6KlS9QeohH9qj+9uqfzpJ2Peu8vScAKaZmZvzcMV4CogJbVz+YanuVVRCsiejoX9VFhr6IzVw52UigwSx5vS0A2Gv+xQUzydx5j+Y2NtxyOU49Y0f6q8XmS5A8lAITzLhNkfkMKtF+Dap3xq0X729T6GAg/EWobAg6aMbyROaWulp+YLPA8Xjfg2e7U+R/e0FgtIzcmF+aJN1LSnbRz2pAVoZY2DjHrgWxFF7yW1GVR7Ku/aKRARCpQNSp+TF4SUPs8wtMNgebXgvl38eJO77O/42k85of2kCmj6fbWS21xhs7IrTfh4yDUssQ2lPrm+MynrIBTFNuO7q68xjS4bNME6pUjtmIcr4WAo1Rstm85VqDMAHbjSa9Qo9fE1tagNVOxm3Ciy5e+njyLW7XUI7dtzVJh0mEq5j1vTPin0NDyZ12Ft7b/2aii/Cc66Q= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199021)(5400799015)(36840700001)(40470700004)(46966006)(70206006)(8676002)(4326008)(70586007)(2906002)(4744005)(41300700001)(316002)(5660300002)(7416002)(8936002)(478600001)(110136005)(966005)(7696005)(40460700003)(82310400005)(1076003)(2616005)(6666004)(26005)(40480700001)(36756003)(47076005)(356005)(336012)(426003)(107886003)(36860700001)(82740400003)(186003)(34020700004)(921005)(7636003)(86362001)(2101003)(83996005)(12100799027);DIR:OUT;SFP:1501; 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..65b58963f0d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9425,6 +9425,9 @@ F: drivers/input/touchscreen/htcpen.c HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ From patchwork Fri Apr 14 00:44:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 13210809 X-Patchwork-Delegate: dipenp@nvidia.com Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04hn2218.outbound.protection.outlook.com [52.100.163.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 147DB369 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:05.1207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff17f82b-95d3-4cb5-39de-08db3c817d35 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5857 Added timestamp provider support for the Tegra234 in devicetree bindings. From Tegra234 SoC onwards, the nvidia,gpio-controller property is required. This is needed as the tegra always-on (AON) GPIO HTE/GTE provider depends on the AON GPIO controller where it needs to do namespace conversion between GPIO line number (belonging to AON GPIO controller instance) and the GTE slice bits. Signed-off-by: Dipen Patel Reviewed-by: Krzysztof Kozlowski --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. v3: - Explained changes in detail in commit message - Added allOf section per review comment v4: - Logically divide the v3 patch as follows - Created Tegra234 support patch - Created depracate nvidia,slices property patch - Created addition of the nvidia,gpio-controller property patch v6: - Merges the patch 3 from v5 into this patch .../timestamp/nvidia,tegra194-hte.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..5de1eca9cbcd 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -43,9 +45,14 @@ properties: description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + property and the value depends on the HTE instance in the chip. + enum: [3, 11, 17] + + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to AON gpio controller instance. This is required to handle + namespace conversion between GPIO and GTE. '#timestamp-cells': description: @@ -62,6 +69,51 @@ required: - nvidia,slices - "#timestamp-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon + then: + properties: + nvidia,slices: + const: 3 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-lic + then: + properties: + nvidia,slices: + const: 11 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-lic + then: + properties: + nvidia,slices: + const: 17 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-aon + then: + required: + - nvidia,gpio-controller + additionalProperties: false examples: From patchwork Fri Apr 14 00:44:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 13210815 X-Patchwork-Delegate: dipenp@nvidia.com Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11hn2206.outbound.protection.outlook.com [52.100.173.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69610620 for ; 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Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij Acked-by: Rob Herring --- .../bindings/timestamp/nvidia,tegra194-hte.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 5de1eca9cbcd..456797967adc 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -42,10 +42,13 @@ properties: nvidia,slices: $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and the value depends on the HTE instance in the chip. + property and the value depends on the HTE instance in the chip. The AON + GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 + LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] nvidia,gpio-controller: @@ -66,7 +69,6 @@ required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" allOf: @@ -123,7 +125,6 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; #timestamp-cells = <1>; }; @@ -133,7 +134,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; }; From patchwork Fri Apr 14 00:44:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 13210811 X-Patchwork-Delegate: dipenp@nvidia.com Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11hn2200.outbound.protection.outlook.com [52.100.171.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08DD7622 for ; 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fe8eda7654d..54790c6b6a2c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1156,6 +1156,14 @@ clock-names = "fuse"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra234-gte-lic"; + reg = <0x0 0x3aa0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; @@ -1673,6 +1681,15 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0x0 0xc1e0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:10.6952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f02c7130-b1f0-4370-84b0-08db3c818098 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6775 Make Tegra194 API document generic to make it applicable for current and future tegra hte providers. Signed-off-by: Dipen Patel Reviewed-by: Bagas Sanjaya --- v5: - rename tegra194-hte.rst to tegra-hte.rst Documentation/driver-api/hte/index.rst | 2 +- .../hte/{tegra194-hte.rst => tegra-hte.rst} | 33 +++++++++---------- 2 files changed, 17 insertions(+), 18 deletions(-) rename Documentation/driver-api/hte/{tegra194-hte.rst => tegra-hte.rst} (50%) diff --git a/Documentation/driver-api/hte/index.rst b/Documentation/driver-api/hte/index.rst index 9f43301c05dc..29011de9a4b8 100644 --- a/Documentation/driver-api/hte/index.rst +++ b/Documentation/driver-api/hte/index.rst @@ -18,5 +18,5 @@ HTE Tegra Provider .. toctree:: :maxdepth: 1 - tegra194-hte + tegra-hte diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/driver-api/hte/tegra-hte.rst similarity index 50% rename from Documentation/driver-api/hte/tegra194-hte.rst rename to Documentation/driver-api/hte/tegra-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and the -driver converts clock tick rate to nanoseconds before storing it as timestamp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp value. GPIO GTE -------- This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller instance -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE -and AON GPIO controller are tightly coupled as it requires very specific bits -to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to HTE -subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how a +consumer can request an GPIO line. See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timestamp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is a one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ number that they are interested in. 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Thu, 13 Apr 2023 17:45:01 -0700 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [V6 6/9] hte: Add Tegra234 provider Date: Thu, 13 Apr 2023 17:44:52 -0700 Message-ID: <20230414004455.19275-7-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230414004455.19275-1-dipenp@nvidia.com> References: <20230414004455.19275-1-dipenp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: timestamp@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT060:EE_|CH0PR12MB5106:EE_ X-MS-Office365-Filtering-Correlation-Id: c51a37e2-faec-4b95-b09b-08db3c817e74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MMLwFPJ6u1xLZf9SK+awdk7jNJQu+pe0RD354nnDNwae3B70Zo5Jyi7sQ6Jty/kJZqPeBMaLoTyHy0x5kZKmOK7z2Z9JIcSqVsfrpR5c+poRJVYLBjwh0rCJzermTA28vEoXF2hsn/g8x1GPqqtPEihWNojTmrYp/8hGGyKirqgQRk6Nz9EwWoy6MOesZpPVvK/eMmU/L0RDOxL5ZPeb7xUQHd4mQuVKbIyQgmmtr1/a5/VuENfKlNHbManOzWqCv7835uo0C/XmqrKpR/Yn+eFBfF5D4TnA8nahWmJdd/EFRFvkAUDHo+Zp4mJaWrRzyLEyeh+eB+w6JjdjuFToagUvG+w6UqSDJ0ZTkuelDDlZpfe4aFx7s9iWoEMg0J5HIjdZt7KFzT2BvIAPET9E88fxbCzVOKraloiQQJGxLn+tjWMlISnPT8vdJMtya4RZN1uGCJrYpOBH4qffVZJfNMG7sNy5tzelB+712XeJpt+hh3KAk7yKjiqvKgRpfmIJX8NnY8cvq0IO/SIoR+SFO4PkEwHXI2MCFbA9LhJbG1n8yoYbms2b6HV/Id+JvcXtQ+FRliNUICMYUYdNsksSqccfYNv3QXdIOuRwwY5/rjyp/q/kd57Ng0r5b6iP3A78r+IFijfX/7DoYa9PnOe66fJxtC5OBZUI96qoY5ASqQgpUdZao9RoSYFis2hIpuYtPtZTlQZ0eWxbNHZlG9bo89OV+n3poNt9cPIMeYxxzsTHLd19gP+FDCejL69gyB/mhT5T/h7NjBLJEhzIRblL6wMZEDIjXtmcfuYeu4OQQjXgydx/vrW20Slee0+l507k6W/OWhGy/1BX1E2qfRHDnqGZhKTGyxVIxtBfs9pME0BwdKbqRm9X9d35NFwWJZpS X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(346002)(376002)(396003)(451199021)(5400799015)(36840700001)(40470700004)(46966006)(36756003)(110136005)(41300700001)(316002)(478600001)(8676002)(70206006)(70586007)(4326008)(7696005)(86362001)(6666004)(7416002)(40480700001)(82310400005)(5660300002)(8936002)(82740400003)(2906002)(34020700004)(356005)(36860700001)(186003)(7636003)(921005)(83380400001)(107886003)(1076003)(336012)(426003)(2616005)(26005)(47076005)(40460700003)(83996005)(2101003)(12100799027);DIR:OUT;SFP:1501; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:07.2144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c51a37e2-faec-4b95-b09b-08db3c817e74 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5106 The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it also requires to add mapping between GPIO and HTE framework same as it was done with Tegra194 SoC. Signed-off-by: Dipen Patel --- v2: - Changed how gpio_chip could be aquired for the mapping v3: - Renamed gpio_chip matching function - Used of_node to fwnode field in gpio_chip matching function as data as gpio_chip struct does not have of_node member anymore. v4: - Logically divide the original v3 patch as follows - Created this Tegra234 support patch - Created deprecated nvidia,slices patch - Created handle nvidia,gpio-controller patch drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 124 ++++++++++++++++++++++++++++++-- 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for this diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..5d1f947db0f6 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -220,7 +224,100 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { [39] = {NV_AON_SLICE_INVALID, 0}, }; -static const struct tegra_hte_data aon_hte = { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] = {NV_AON_SLICE_INVALID, 0}, + [13] = {NV_AON_SLICE_INVALID, 0}, + [14] = {NV_AON_SLICE_INVALID, 0}, + [15] = {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] = {NV_AON_SLICE_INVALID, 0}, + [28] = {NV_AON_SLICE_INVALID, 0}, + [29] = {NV_AON_SLICE_INVALID, 0}, + [30] = {NV_AON_SLICE_INVALID, 0}, + [31] = {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte = { .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), .map = tegra194_aon_gpio_map, .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), @@ -228,6 +325,14 @@ static const struct tegra_hte_data aon_hte = { .type = HTE_TEGRA_TYPE_GPIO, }; +static const struct tegra_hte_data t234_aon_hte = { + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), + .map = tegra234_aon_gpio_map, + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map = tegra234_aon_gpio_sec_map, + .type = HTE_TEGRA_TYPE_GPIO, +}; + static const struct tegra_hte_data lic_hte = { .map_sz = 0, .map = NULL, @@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, static const struct of_device_id tegra_hte_of_match[] = { { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte}, + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; - hte_dev->c = gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + if (of_device_is_compatible(dev->of_node, + "nvidia,tegra194-gte-aon")) + hte_dev->c = gpiochip_find("tegra194-gpio-aon", + tegra_get_gpiochip_from_name); + else if (of_device_is_compatible(dev->of_node, + "nvidia,tegra234-gte-aon")) + hte_dev->c = gpiochip_find("tegra234-gpio-aon", + tegra_get_gpiochip_from_name); + else + return -ENODEV; + if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); From patchwork Fri Apr 14 00:44:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 13210812 X-Patchwork-Delegate: dipenp@nvidia.com Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12hn2223.outbound.protection.outlook.com [52.100.166.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A571623 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:08.0581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c8196aa-52cc-4230-7070-08db3c817ef5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4223 The relevant DT bindings deprecates nvidia,slices property from Tegra234 SoC onwards, moving the slices value per SoC data structure instead. Signed-off-by: Dipen Patel --- drivers/hte/hte-tegra194.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 5d1f947db0f6..945c68c5e476 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -118,6 +118,7 @@ struct tegra_hte_line_data { struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -323,6 +324,7 @@ static const struct tegra_hte_data t194_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map = tegra194_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; static const struct tegra_hte_data t234_aon_hte = { @@ -331,12 +333,21 @@ static const struct tegra_hte_data t234_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), .sec_map = tegra234_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; -static const struct tegra_hte_data lic_hte = { +static const struct tegra_hte_data t194_lic_hte = { .map_sz = 0, .map = NULL, .type = HTE_TEGRA_TYPE_LIC, + .slices = 11, +}; + +static const struct tegra_hte_data t234_lic_hte = { + .map_sz = 0, + .map = NULL, + .type = HTE_TEGRA_TYPE_LIC, + .slices = 17, }; static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -639,9 +650,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, } static const struct of_device_id tegra_hte_of_match[] = { - { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, - { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; @@ -679,13 +690,6 @@ static int tegra_hte_probe(struct platform_device *pdev) dev = &pdev->dev; - ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret != 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; 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Thu, 13 Apr 2023 17:45:03 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 13 Apr 2023 17:45:02 -0700 Received: from dipenp.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 13 Apr 2023 17:45:02 -0700 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [V6 8/9] hte: handle nvidia,gpio-controller property Date: Thu, 13 Apr 2023 17:44:54 -0700 Message-ID: <20230414004455.19275-9-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230414004455.19275-1-dipenp@nvidia.com> References: <20230414004455.19275-1-dipenp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: timestamp@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT028:EE_|SJ2PR12MB8875:EE_ X-MS-Office365-Filtering-Correlation-Id: d377e27d-c0d1-4b8c-f2c4-08db3c817fdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:09.5753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d377e27d-c0d1-4b8c-f2c4-08db3c817fdc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8875 The dt binding adds nvidia,gpio-controller property from Tegra234 SoC onwards to simplify code handling gpio chip search. The gpio chip search is needed for the AON GPIO GTE instances to map the hardware timestamp GPIO request (coming from the GPIO framework) to the tegra HTE providers. The patch also adds new gpio chip match function to match from the fwnode instead of the gpio controller label. The addition of the property does not break ABI for the existing Tegra194 code. Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- drivers/hte/hte-tegra194.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 945c68c5e476..2c485ff5be22 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -679,6 +679,11 @@ static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) return !strcmp(chip->label, data); } +static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) +{ + return chip->fwnode == of_node_to_fwnode(data); +} + static int tegra_hte_probe(struct platform_device *pdev) { int ret; @@ -687,6 +692,7 @@ static int tegra_hte_probe(struct platform_device *pdev) struct device *dev; struct tegra_hte_soc *hte_dev; struct hte_chip *gc; + struct device_node *gpio_ctrl; dev = &pdev->dev; @@ -754,15 +760,23 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; if (of_device_is_compatible(dev->of_node, - "nvidia,tegra194-gte-aon")) + "nvidia,tegra194-gte-aon")) { hte_dev->c = gpiochip_find("tegra194-gpio-aon", tegra_get_gpiochip_from_name); - else if (of_device_is_compatible(dev->of_node, - "nvidia,tegra234-gte-aon")) - hte_dev->c = gpiochip_find("tegra234-gpio-aon", - tegra_get_gpiochip_from_name); - else - return -ENODEV; + } else { + gpio_ctrl = of_parse_phandle(dev->of_node, + "nvidia,gpio-controller", + 0); + if (!gpio_ctrl) { + dev_err(dev, + "gpio controller node not found\n"); + return -ENODEV; + } + + hte_dev->c = gpiochip_find(gpio_ctrl, + tegra_gpiochip_match); + of_node_put(gpio_ctrl); + } if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, From patchwork Fri Apr 14 00:44:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 13210818 X-Patchwork-Delegate: dipenp@nvidia.com Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02hn2223.outbound.protection.outlook.com [52.100.160.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EF2E622 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 00:45:13.2782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e68dc6d-848a-4177-f71c-08db3c818211 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5819 To enable timestamp support for the Tegra234, has_gte variable needs to be set true. Signed-off-by: Dipen Patel Acked-by: Thierry Reding Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 14c872b6ad05..b904de0b1784 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \