From patchwork Fri Apr 14 08:06:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D8D7C77B71 for ; Fri, 14 Apr 2023 08:07:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229625AbjDNIHf (ORCPT ); Fri, 14 Apr 2023 04:07:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjDNIHe (ORCPT ); Fri, 14 Apr 2023 04:07:34 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ED136EB2 for ; Fri, 14 Apr 2023 01:07:30 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id B10605C00F3; Fri, 14 Apr 2023 04:07:29 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Fri, 14 Apr 2023 04:07:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1681459649; x= 1681546049; bh=UJXAY6egY3qR1MS2CQgEgO1i8Jea+v/THDqVOPcw8vo=; b=p YVTy3GFw4Xh2wLvojchHNTAFDPw6FzaR9DMLFeL2oFQDS1pXbG3L82XoQGlGEepT wuWSulieMUYP+2CbltvTF9+nFmrKBGa7YK0EA4dzncAomlx12r4ermvrlWsl7AEj KQcHKwNExPA8oACA9uJCgnzYterwva06aBmwfdKmozZ4RzE+/DjNmUbB5eFBduRi s2GWOma9+rjULHTy7qPQnwpCk5i5ZsJ0mMlF8EOn3PnI5RB0tbgt0OexaR9I2lym UyMhbJ0ANgkkNou0p+AT50IVN3bLH6HYKmseq8iggIVd2L7qs8HpE5xkk1BpmVl8 SGqbirEAvo41tmUlcIC2Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1681459649; x= 1681546049; bh=UJXAY6egY3qR1MS2CQgEgO1i8Jea+v/THDqVOPcw8vo=; b=R khaI4lqXxOEv+j1p21BTb6/SoqjF+UFKMSn7N+D+nXE8aAJTEYPHYMltd0RyERzF 1NNd0gJSsNf7SPQ+hSKfyplkdGvgPtGThaJo9w2CpumLcLaHwX7USPs5hK0S+QM1 GhNlH2KrUhqfW9GCgC0x5MjRi/ZgLMEhKyWsajkv+ZjAKGzxtyy1vk60y6eyQ9/g +6HS5W07bN4LSDTuufbGudI/0LzmgEIb24VIyj7XHAYHTUdvK9IMCirTkM/JqHv2 4ecaMkhs5xlcDEBOHD8yQbt3LeOr8NXDNgMswNuzDyanMtkfSJRZbE8lcdB3l4K7 r4jgzGE3a8F+nqAGENdmA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdekledgudeftdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 14 Apr 2023 04:07:28 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig Date: Fri, 14 Apr 2023 09:06:55 +0100 Message-Id: <20230414080701.15503-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use Kconfig to perform Kconfig toolchain feature check, so we will be able to have toolchain feature availablility information in Kconfig to guard relevant options. Signed-off-by: Jiaxun Yang --- v2: Fix a typo --- arch/mips/Kconfig | 27 +++++++++++++++++++++++++++ arch/mips/Makefile | 29 +++-------------------------- arch/mips/crypto/crc32-mips.c | 4 ++-- arch/mips/include/asm/asmmacro.h | 8 ++++---- arch/mips/include/asm/ginvt.h | 2 +- arch/mips/include/asm/mipsregs.h | 10 +++++----- arch/mips/include/asm/msa.h | 4 ++-- 7 files changed, 44 insertions(+), 40 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 770d098b11bf..41ac4dc5aae4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3157,6 +3157,12 @@ config MIPS32_N32 If unsure, say N. +config CC_HAS_SMARTMIPS + def_bool $(cc-option,-msmartmips) + +config CC_HAS_MICROMIPS + def_bool $(cc-option,-mmicromips) + config CC_HAS_MNO_BRANCH_LIKELY def_bool y depends on $(cc-option,-mno-branch-likely) @@ -3165,6 +3171,27 @@ config CC_HAS_MNO_BRANCH_LIKELY config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG +config AS_HAS_MSA + def_bool $(cc-option,-Wa$(comma)-mmsa) + +config AS_HAS_VIRT + def_bool $(cc-option,-Wa$(comma)-mvirt) + +# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which +# only warns +config AS_HAS_XPA + def_bool $(cc-option,-Wa$(comma)-mxpa) if !CPU_MICROMIPS + def_bool $(cc-option,-mmicromips -Wa$(comma)-fatal-warnings -Wa$(comma)-mxpa) if CPU_MICROMIPS + +config AS_HAS_CRC + def_bool $(cc-option,-Wa$(comma)-mcrc) + +config AS_HAS_DSP + def_bool $(cc-option,-Wa$(comma)-mdsp) + +config AS_HAS_GINV + def_bool $(cc-option,-Wa$(comma)-mginv) + menu "Power management options" config ARCH_HIBERNATION_POSSIBLE diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a7a4ee66a9d3..3aa0f9d4ceb6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -233,32 +233,9 @@ cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has # been fixed properly. mips-cflags := $(cflags-y) -ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y) -smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips) -cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn -endif -ifeq ($(CONFIG_CPU_MICROMIPS),y) -micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips) -cflags-$(micromips-ase) += -mmicromips -endif -ifeq ($(CONFIG_CPU_HAS_MSA),y) -toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa) -cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA -endif -toolchain-virt := $(call cc-option-yn,$(mips-cflags) -mvirt) -cflags-$(toolchain-virt) += -DTOOLCHAIN_SUPPORTS_VIRT -# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which -# only warns -xpa-cflags-y := $(mips-cflags) -xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings -toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa) -cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA -toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc) -cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC -toolchain-dsp := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp) -cflags-$(toolchain-dsp) += -DTOOLCHAIN_SUPPORTS_DSP -toolchain-ginv := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mginv) -cflags-$(toolchain-ginv) += -DTOOLCHAIN_SUPPORTS_GINV + +cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += -msmartmips -Wa,--no-warn +cflags-$(CONFIG_CPU_MICROMIPS) += -mmicromips # # Firmware support diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c index 3e4f5ba104f8..54bbcfae06d5 100644 --- a/arch/mips/crypto/crc32-mips.c +++ b/arch/mips/crypto/crc32-mips.c @@ -27,7 +27,7 @@ enum crc_type { crc32c, }; -#ifndef TOOLCHAIN_SUPPORTS_CRC +#ifndef CONFIG_AS_HAS_CRC #define _ASM_SET_CRC(OP, SZ, TYPE) \ _ASM_MACRO_3R(OP, rt, rs, rt2, \ ".ifnc \\rt, \\rt2\n\t" \ @@ -38,7 +38,7 @@ _ASM_MACRO_3R(OP, rt, rs, rt2, \ _ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \ ((SZ) << 14) | ((TYPE) << 3))) #define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t" -#else /* !TOOLCHAIN_SUPPORTS_CRC */ +#else /* !CONFIG_AS_HAS_CRC */ #define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t" #define _ASM_UNSET_CRC(op, SZ, TYPE) #endif diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 067a635d3bc8..74c2dedc55b4 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -239,7 +239,7 @@ .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA .macro _cfcmsa rd, cs .set push .set mips32r2 @@ -507,7 +507,7 @@ .endm #endif -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA #define FPR_BASE_OFFS THREAD_FPR0 #define FPR_BASE $1 #else @@ -518,7 +518,7 @@ .macro msa_save_all thread .set push .set noat -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS #endif st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE @@ -565,7 +565,7 @@ .set hardfloat lw $1, THREAD_MSA_CSR(\thread) _ctcmsa MSA_CSR, $1 -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS #endif ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h index 87b2974ffc53..20244a622552 100644 --- a/arch/mips/include/asm/ginvt.h +++ b/arch/mips/include/asm/ginvt.h @@ -10,7 +10,7 @@ enum ginvt_type { GINVT_MMID, }; -#ifdef TOOLCHAIN_SUPPORTS_GINV +#ifdef CONFIG_AS_HAS_GINV # define _ASM_SET_GINV ".set ginv\n" # define _ASM_UNSET_GINV #else diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 2d53704d9f24..8f0ebc399338 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1604,7 +1604,7 @@ do { \ local_irq_restore(__flags); \ } while (0) -#ifndef TOOLCHAIN_SUPPORTS_XPA +#ifndef CONFIG_AS_HAS_XPA #define _ASM_SET_MFHC0 \ _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, \ _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \ @@ -1615,7 +1615,7 @@ do { \ _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \ _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11)) #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t" -#else /* !TOOLCHAIN_SUPPORTS_XPA */ +#else /* !CONFIG_AS_HAS_XPA */ #define _ASM_SET_MFHC0 ".set\txpa\n\t" #define _ASM_SET_MTHC0 ".set\txpa\n\t" #define _ASM_UNSET_MFHC0 @@ -2040,7 +2040,7 @@ do { \ * Macros to access the guest system control coprocessor */ -#ifndef TOOLCHAIN_SUPPORTS_VIRT +#ifndef CONFIG_AS_HAS_VIRT #define _ASM_SET_MFGC0 \ _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \ _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \ @@ -2077,7 +2077,7 @@ do { \ #define __tlbginvf() \ _ASM_INSN_IF_MIPS(0x4200000c) \ _ASM_INSN32_IF_MM(0x0000517c) -#else /* !TOOLCHAIN_SUPPORTS_VIRT */ +#else /* !CONFIG_AS_HAS_VIRT */ #define _ASM_SET_VIRT ".set\tvirt\n\t" #define _ASM_SET_MFGC0 _ASM_SET_VIRT #define _ASM_SET_DMFGC0 _ASM_SET_VIRT @@ -2395,7 +2395,7 @@ do { \ : : "r" (val)); \ } while (0) -#ifdef TOOLCHAIN_SUPPORTS_DSP +#ifdef CONFIG_AS_HAS_DSP #define rddsp(mask) \ ({ \ unsigned int __dspctl; \ diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index 236a49ee2e3e..a9ca57e3f780 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -156,7 +156,7 @@ static inline void init_msa_upper(void) _init_msa_upper(); } -#ifndef TOOLCHAIN_SUPPORTS_MSA +#ifndef CONFIG_AS_HAS_MSA /* * Define assembler macros using .word for the c[ft]cmsa instructions in order * to allow compilation with toolchains that do not support MSA. Once all @@ -173,7 +173,7 @@ static inline void init_msa_upper(void) _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6) \ _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6)) #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t" -#else /* TOOLCHAIN_SUPPORTS_MSA */ +#else /* CONFIG_AS_HAS_MSA */ #define _ASM_SET_CFCMSA \ ".set\tfp=64\n\t" \ ".set\tmsa\n\t" From patchwork Fri Apr 14 08:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC983C77B70 for ; Fri, 14 Apr 2023 08:07:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229902AbjDNIHh (ORCPT ); Fri, 14 Apr 2023 04:07:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229949AbjDNIHg (ORCPT ); Fri, 14 Apr 2023 04:07:36 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E274C65BD for ; Fri, 14 Apr 2023 01:07:31 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 50C9A5C0086; Fri, 14 Apr 2023 04:07:31 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Fri, 14 Apr 2023 04:07:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1681459651; x= 1681546051; bh=GbyH8yAqRFdY13pD1/k/d2AWpv4tW8BU4FUnkwA1skE=; b=N lOAZMQ2o/l70VEG3Alx2mVkIUPMtbJr6goBY1/W30DNIdwtRk3a4weqdyKo6+PHI lOMMFAlL8KcNgRFeXzWXOMfxVddKKQwQz9q2XZZMyHSDsNAHUHEAQIiknUVET6Vs yIEQjbXVMFm7a1swgIZH2nki4d5MHoW3Sps3mBL2O1LMgOUfuqGHldv4pSo3oy8r gThYF/+Q6xsMClJ8kknxsu5zo8vNPVTa9Q3XKhQD2h8NRL5L/lT2g+dC7cxFdOyB Q/BrF0HqO9f5DcfT8+fnnnfYwZAl5vJXSTcWxbEqAQL+lhAQhPYT3nprgq+Lp2LH V0jaNvLPGdu3Pc9l03gbw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1681459651; x= 1681546051; bh=GbyH8yAqRFdY13pD1/k/d2AWpv4tW8BU4FUnkwA1skE=; b=B DQb+yrhEKHc5ZgMH5q0B35Pxt4Hm3QmTtjZRCspfoxfAIq5s9LilLoctBdzE4QAj ikO+/Kxis6YDbxHzZEJfE8SM2nwJe4H6/5Hv0bfwwVOCFnU9vkd5OcomlGZT2RwA fxwZUqNyB5Uq6fh/eNglXTT/SdhYBYUwrDUa088QUo/fVOcAPNN/pOxn3rB7R8rG GKEiZjWA79oaqzacWzMCoDk6tQTmVkh/QPCEjw4Sb+be9M0d/iA4LbjB7aNkz11r V+w3Z7l9TZWaFkjFxGEWoxaIj7R2aC75O0G6UqVhxL56lJxnAE3jLMXlcS1fpb8g e33R0+1/g2RxMekg2dkLg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdekledgudeftdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 14 Apr 2023 04:07:29 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Date: Fri, 14 Apr 2023 09:06:56 +0100 Message-Id: <20230414080701.15503-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org microMIPS smartMIPS kernel can only be compiled if they are supported by toolchain. Signed-off-by: Jiaxun Yang Reviewed-by: Nick Desaulniers --- arch/mips/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 41ac4dc5aae4..0b270562c3eb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS Select this if you want neither microMIPS nor SmartMIPS support config CPU_HAS_SMARTMIPS - depends on SYS_SUPPORTS_SMARTMIPS + depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS bool "SmartMIPS" help SmartMIPS is a extension of the MIPS32 architecture aimed at @@ -2373,6 +2373,7 @@ config CPU_HAS_SMARTMIPS config CPU_MICROMIPS depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6 + depends on CC_HAS_MICROMIPS bool "microMIPS" help When this option is enabled the kernel will be built using the From patchwork Fri Apr 14 08:06:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CDCDC77B6E for ; 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Fri, 14 Apr 2023 04:07:31 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig Date: Fri, 14 Apr 2023 09:06:57 +0100 Message-Id: <20230414080701.15503-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM toolchain does not support most of workarounds, detect those supports in Kconfig so we can hide unsupported workarounds to user. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Signed-off-by: Jiaxun Yang Reviewed-by: Nick Desaulniers --- arch/mips/Kconfig | 28 +++++++++++++++++++++++++--- arch/mips/Makefile | 6 +++--- arch/mips/cavium-octeon/Kconfig | 1 + 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0b270562c3eb..0cd9cd01b7ab 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -371,9 +371,9 @@ config MACH_DECSTATION select CEVT_R4K if CPU_R4X00 select CSRC_IOASIC select CSRC_R4K if CPU_R4X00 - select CPU_DADDI_WORKAROUNDS if 64BIT - select CPU_R4000_WORKAROUNDS if 64BIT - select CPU_R4400_WORKAROUNDS if 64BIT + imply CPU_DADDI_WORKAROUNDS + imply CPU_R4000_WORKAROUNDS + imply CPU_R4400_WORKAROUNDS select DMA_NONCOHERENT select NO_IOPORT_MAP select IRQ_MIPS_CPU @@ -1723,6 +1723,7 @@ config CPU_JUMP_WORKAROUNDS config CPU_LOONGSON2F_WORKAROUNDS bool "Loongson 2F Workarounds" default y + depends on AS_HAS_NOP_WORKAROUNDS && AS_HAS_JUMP_WORKAROUNDS select CPU_NOP_WORKAROUNDS select CPU_JUMP_WORKAROUNDS help @@ -2457,6 +2458,7 @@ config CPU_HAS_SYNC # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 config CPU_DADDI_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_DADDI_WORKAROUNDS # Work around certain R4000 CPU errata (as implemented by GCC): # @@ -2478,6 +2480,7 @@ config CPU_DADDI_WORKAROUNDS # erratum #52 config CPU_R4000_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_R4000_WORKAROUNDS select CPU_R4400_WORKAROUNDS # Work around certain R4400 CPU errata (as implemented by GCC): @@ -2488,6 +2491,7 @@ config CPU_R4000_WORKAROUNDS # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 config CPU_R4400_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_R4400_WORKAROUNDS config CPU_R4X00_BUGS64 bool @@ -3168,6 +3172,15 @@ config CC_HAS_MNO_BRANCH_LIKELY def_bool y depends on $(cc-option,-mno-branch-likely) +config CC_HAS_R4000_WORKAROUNDS + def_bool $(cc-option,-mfix-r4000) + +config CC_HAS_R4400_WORKAROUNDS + def_bool $(cc-option,-mfix-r4400) + +config CC_HAS_DADDI_WORKAROUNDS + def_bool $(cc-option,-mno-daddi) + # https://github.com/llvm/llvm-project/issues/61045 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG @@ -3193,6 +3206,15 @@ config AS_HAS_DSP config AS_HAS_GINV def_bool $(cc-option,-Wa$(comma)-mginv) +config AS_HAS_CN63XXP1_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-cn63xxp1) + +config AS_HAS_NOP_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-nop) + +config AS_HAS_JUMP_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-jump) + menu "Power management options" config ARCH_HIBERNATION_POSSIBLE diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 3aa0f9d4ceb6..344fe5f00f7b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -193,9 +193,9 @@ cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 endif cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi) -cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) -cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) -cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += -mfix-r4000 +cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += -mfix-r4400 +cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += -mno-daddi ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 450e979ef5d9..38c9dc89cd5f 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -4,6 +4,7 @@ if CPU_CAVIUM_OCTEON config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata workarounds" default "n" + depends on AS_HAS_CN63XXP1_WORKAROUNDS help The CN63XXP1 chip requires build time workarounds to function reliably, select this option to enable them. These From patchwork Fri Apr 14 08:06:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEE42C77B71 for ; Fri, 14 Apr 2023 08:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229951AbjDNIHj (ORCPT ); Fri, 14 Apr 2023 04:07:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229949AbjDNIHj (ORCPT ); Fri, 14 Apr 2023 04:07:39 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A0A26E91 for ; Fri, 14 Apr 2023 01:07:34 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id CA8255C00E8; Fri, 14 Apr 2023 04:07:33 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Fri, 14 Apr 2023 04:07:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1681459653; x= 1681546053; bh=319qtseuj6dXrXziMf2n5r9XqioLOhb85xW0q9IWu6c=; b=Q GDKSP1QW1DnvFoT+CClJqCOG0D4Hc92n/pTVeYpOF/5Ez7ctcmp8iEmQAvsUPv2B CJA1Dc4s63Ndq3g71yoDXyevx5QvyIQ6B9KNBDjG13Vcr2iFmx8llKN1tqPB6QVX Zkel71+emHrbO2N2zHlnf4t4ZLyxTyW4HYxGJIkzgIcDaQceFclIszsDAxf4XbsS 3q/klnFqxvmKciyH3w0HziGl9sbUnqLZOJeOs7dEMrE8WcfIRLpAEGeUmCNs90pm uS166Ic/74ZR0wQXHDj8UyDpVRzLjHuTYQ1mHEDIuYTJjhdufRClcr6TGX/1YFVH HDgT77Vi9HMT0kOickrVA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1681459653; x= 1681546053; bh=319qtseuj6dXrXziMf2n5r9XqioLOhb85xW0q9IWu6c=; b=Y sBATC9nHm2ybLd9oVhWelVnlS+aPi0rljO4G7UaOE/2iIKxd5tuzXCbALHvUd1sU PVYRJ0KHhpJ+cgaB5zTrmMLYddswKD2O2B0HbekJw+8apuBS6mlVt4gFiHoJFvLb ZMWSVAhtvt6hqh39YHwOwyDShZVQ89270Qb40fuOtqPo7HWP8Twr/+CMapxasy+b nFu/UKCEWkrz0h97lS1TWjUaLp1Fv95Cp7qoZC4pR7Hei986Dr3Eb+5NM7EcLEHV TNlXcE3wx0lRuS67iWOY5HEXyoKjB7tyjTNW1w63xA+Df2Znn2hEk2tXfxv4Dr6D ufa4fvd9WFd+GnNVbzO3A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdekledgudeftdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeeifefhvedthfejve evgfekueduieelfeetffdtveetffefgeelieetgfffueejkeenucffohhmrghinhepghhi thhhuhgsrdgtohhmnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilh hfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 14 Apr 2023 04:07:32 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 4/7] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Date: Fri, 14 Apr 2023 09:06:58 +0100 Message-Id: <20230414080701.15503-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit kernel is unsupported. Detect this in Kconfig to prevent user select 32 bit kernel with unsupported toolchain. Link: https://github.com/ClangBuiltLinux/linux/issues/884 Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0cd9cd01b7ab..2374f859e001 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2016,6 +2016,7 @@ choice config 32BIT bool "32-bit kernel" depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + depends on CC_HAS_O32_ABI select TRAD_SIGNALS help Select this option if you want to build a 32-bit kernel. @@ -3137,7 +3138,7 @@ config COMPAT config MIPS32_O32 bool "Kernel support for o32 binaries" - depends on 64BIT + depends on 64BIT && CC_HAS_O32_ABI select ARCH_WANT_OLD_COMPAT_IPC select COMPAT select MIPS32_COMPAT @@ -3185,6 +3186,10 @@ config CC_HAS_DADDI_WORKAROUNDS config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG +config CC_HAS_O32_ABI + def_bool y + depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32) + config AS_HAS_MSA def_bool $(cc-option,-Wa$(comma)-mmsa) From patchwork Fri Apr 14 08:06:59 2023 Content-Type: text/plain; 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Fri, 14 Apr 2023 04:07:33 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 5/7] MIPS: Remove cc-option checks for -march=octeon Date: Fri, 14 Apr 2023 09:06:59 +0100 Message-Id: <20230414080701.15503-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Nowadays our minimal supported GCC/Clang all support -march=octeon. Remove cc-option checks to simplify code. Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 344fe5f00f7b..af3d17ec35d3 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -174,10 +174,7 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ -Wa,--trap -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap -ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon -endif +cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap From patchwork Fri Apr 14 08:07:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AAB0C77B6E for ; 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Fri, 14 Apr 2023 04:07:35 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Date: Fri, 14 Apr 2023 09:07:00 +0100 Message-Id: <20230414080701.15503-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM does not implement some of -march options. However those options are not mandatory for kernel to build for those CPUs. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- v2: Reword commit message --- arch/mips/Makefile | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index af3d17ec35d3..0fa84fc395c9 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # # CPU-dependent compiler/assembler options for optimization. # -cflags-$(CONFIG_CPU_R3000) += -march=r3000 -cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap -cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_R3000) += $(call cc-option,-march=r3000,-march=mips1) +cflags-$(CONFIG_CPU_R4300) += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg @@ -160,26 +160,30 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap -cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg -cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap -cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \ +cflags-$(CONFIG_CPU_P5600) += $(call cc-option,-march=p5600,-march=mips32r5) \ + -Wa,--trap -modd-spreg +cflags-$(CONFIG_CPU_R5000) += $(call cc-option,-march=r5000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ +cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ +cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ + -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) -cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ +cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap # Some -march= flags enable MMI instructions, and GCC complains about that # support being enabled alongside -msoft-float. Thus explicitly disable MMI. cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi) From patchwork Fri Apr 14 08:07:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13211092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D76DC77B6E for ; Fri, 14 Apr 2023 08:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229949AbjDNIHo (ORCPT ); Fri, 14 Apr 2023 04:07:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbjDNIHm (ORCPT ); Fri, 14 Apr 2023 04:07:42 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FA2072AA for ; Fri, 14 Apr 2023 01:07:38 -0700 (PDT) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id C9D3D5C00C5; Fri, 14 Apr 2023 04:07:37 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Fri, 14 Apr 2023 04:07:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1681459657; x= 1681546057; bh=60PlD2MyZgNIk/JWFkkJ/HhQAbjvbcqYgeFeUzfxVX4=; b=H He3OMK/2SxbRROumRYhSngFQvhDhE4kCRXRU8t6K90E9JEud15H9tcWYRg7TIjzK iKrE+81nDS/z4MTLXZDh7OZ9EVj9YS74G8NzjK8IATp9PWKDAweEuZS6Wg3Ms5jr YasvTSAE63Xt0p1VQRYyYsEyCTQiD+b+iLgDWi/chNVeKBR1ShZnWZGvIZAr2eL8 YY/2bxhnI77u6coDnfSmG4gyu+WZaBEQLtoo1m+an2MyiHmuYEjmIoz+KkamR4ZH 0AzvOtJIz1ApZkPlGMwvW6EvSbnZPfaFvoeZ0lqSBTkyP+soJPiG/78nVAS11fMx jAFUFil7WItDPAHkDZzrg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1681459657; x= 1681546057; bh=60PlD2MyZgNIk/JWFkkJ/HhQAbjvbcqYgeFeUzfxVX4=; b=R +DG39sOCMrIJALMPWneV2LJlc+CZkek9A1KDDHhvyY8Vb4hHVjqWCZA89Ld15obA +iDc3wP0EP8RQwCw3L4ezdn6O9s7t9OygoqXh+9zoTge023FOFu80GiK8XPWlZt3 TDPPrltz16kFBBTLAEKQjPitVfoITM5E5pcCR2aQCDa5FRbYao8772/aSYoCHIDE zp3kkRNmWFC5JE2C/WcuFNvVRVls9wIyTmtOF33T6g4Sa6/frE5lI7UQGtLceKya e0bRxluXMcnpwIfCEyHlUOPkSPFBHIaH8eCEWATFqAt/mrIXqXTK7Kf+R6awW/IO QZll/P+Quv0WoDBUa9toQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdekledgudeftdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvue dvvdegkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhi iigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflh ihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 14 Apr 2023 04:07:36 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang , Guenter Roeck Subject: [PATCH v2 7/7] MIPS: Limit MIPS_MT_SMP support by ISA reversion Date: Fri, 14 Apr 2023 09:07:01 +0100 Message-Id: <20230414080701.15503-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230414080701.15503-1-jiaxun.yang@flygoat.com> References: <20230414080701.15503-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org MIPS MT ASE is only available on ISA between Release 1 and Release 5. Add ISA level dependency to Kconfig to fix build. Reported-by: Guenter Roeck Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2374f859e001..a61f860771e2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2194,7 +2194,8 @@ config CPU_R4K_CACHE_TLB config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" default y - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select SYNC_R4K