From patchwork Fri Apr 14 17:43:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13211883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4A2FC77B72 for ; Fri, 14 Apr 2023 17:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbjDNRnI (ORCPT ); Fri, 14 Apr 2023 13:43:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjDNRnD (ORCPT ); Fri, 14 Apr 2023 13:43:03 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8867312A for ; Fri, 14 Apr 2023 10:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681494182; x=1713030182; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a7C49MWEOowkHndHiAvfyTS/b5YzFYEvQoUcqs7C/rY=; b=Co4H7jDV2s6fLU8/SQ4oMPLHp8vrRBAcecs2tGKunNaVLhvEWc0rmihl 3/Qpg1XOuAWPWht+qQGjbmI/1HeGUfN0XpvsgmEp4H5lBsDg0yFJWHtlb 6IR9IJclSd+ktjJw/5Z4X8OZEivkw/l00Uyq3nfXR1UzUB6LzPy1eHY8z 6dIgp1mUILs9zmsgsaO98gSDfXOwUKZ3J8DGSxsI9ikdvVFDZc42xTCDW eGaDGlqBoEC/dghxqyhu30I4Uvo+vE0VMune1Al2Rkj6TsQt7RiKHthn1 VfPFXgxlfenyW1X7JkaRjUJcsK/41PfH9W9OBEkXr/3BIUEWgPVbhlHtH w==; X-IronPort-AV: E=McAfee;i="6600,9927,10680"; a="407405491" X-IronPort-AV: E=Sophos;i="5.99,197,1677571200"; d="scan'208";a="407405491" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2023 10:43:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10680"; a="813967597" X-IronPort-AV: E=Sophos;i="5.99,197,1677571200"; d="scan'208";a="813967597" Received: from tpattadx-mobl1.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.122.87]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2023 10:43:01 -0700 Subject: [NDCTL PATCH 1/3] ndctl: Add QTG ID support for the root decoder From: Dave Jiang To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org Date: Fri, 14 Apr 2023 10:43:01 -0700 Message-ID: <168149418140.4013891.18368466862769013304.stgit@djiang5-mobl3> In-Reply-To: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> References: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add libcxl API to retrieve the QoS Throttling Group (QTG) ID for the root decoder. Also add support to display the QTG ID for the root decoder through the 'cxl list' command. Signed-off-by: Dave Jiang --- cxl/json.c | 10 ++++++++++ cxl/lib/libcxl.c | 11 +++++++++++ cxl/lib/libcxl.sym | 1 + cxl/lib/private.h | 1 + cxl/libcxl.h | 3 +++ 5 files changed, 26 insertions(+) diff --git a/cxl/json.c b/cxl/json.c index e87bdd49a776..8dd65f942c6a 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -760,6 +760,16 @@ struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, jobj); } + if (cxl_port_is_root(port)) { + int qtg_id = cxl_decoder_get_qtg_id(decoder); + + if (qtg_id != CXL_QTG_ID_NONE) { + jobj = json_object_new_int(qtg_id); + if (jobj) + json_object_object_add(jdecoder, "qtg_id", jobj); + } + } + json_object_set_userdata(jdecoder, decoder, NULL); return jdecoder; } diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 59e5bdbcc750..26985c9344b4 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -1879,6 +1879,12 @@ static void *add_cxl_decoder(void *parent, int id, const char *cxldecoder_base) else decoder->interleave_ways = strtoul(buf, NULL, 0); + sprintf(path, "%s/qtg_id", cxldecoder_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + decoder->qtg_id = CXL_QTG_ID_NONE; + else + decoder->qtg_id = atoi(buf); + switch (port->type) { case CXL_PORT_ENDPOINT: sprintf(path, "%s/dpa_resource", cxldecoder_base); @@ -2073,6 +2079,11 @@ CXL_EXPORT unsigned long long cxl_decoder_get_size(struct cxl_decoder *decoder) return decoder->size; } +CXL_EXPORT int cxl_decoder_get_qtg_id(struct cxl_decoder *decoder) +{ + return decoder->qtg_id; +} + CXL_EXPORT unsigned long long cxl_decoder_get_dpa_resource(struct cxl_decoder *decoder) { diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 1c6177c7dcae..d1c61f9252fe 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -248,4 +248,5 @@ global: cxl_region_get_mode; cxl_decoder_create_ram_region; cxl_region_get_daxctl_region; + cxl_decoder_get_qtg_id; } LIBCXL_4; diff --git a/cxl/lib/private.h b/cxl/lib/private.h index d648992b808d..ac6f111b5956 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -126,6 +126,7 @@ struct cxl_decoder { struct list_head targets; struct list_head regions; struct list_head stale_regions; + int qtg_id; }; enum cxl_decode_state { diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 54d9f10537dd..66ce4a021c62 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -135,6 +135,8 @@ struct cxl_dport *cxl_port_get_dport_by_memdev(struct cxl_port *port, for (dport = cxl_dport_get_first(port); dport != NULL; \ dport = cxl_dport_get_next(dport)) +#define CXL_QTG_ID_NONE -1 + struct cxl_decoder; struct cxl_decoder *cxl_decoder_get_first(struct cxl_port *port); struct cxl_decoder *cxl_decoder_get_next(struct cxl_decoder *decoder); @@ -146,6 +148,7 @@ unsigned long long cxl_decoder_get_dpa_resource(struct cxl_decoder *decoder); unsigned long long cxl_decoder_get_dpa_size(struct cxl_decoder *decoder); unsigned long long cxl_decoder_get_max_available_extent(struct cxl_decoder *decoder); +int cxl_decoder_get_qtg_id(struct cxl_decoder *decoder); enum cxl_decoder_mode { CXL_DECODER_MODE_NONE, From patchwork Fri Apr 14 17:43:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13211885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59787C77B71 for ; Fri, 14 Apr 2023 17:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229913AbjDNRnn (ORCPT ); Fri, 14 Apr 2023 13:43:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229752AbjDNRnJ (ORCPT ); Fri, 14 Apr 2023 13:43:09 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 903B912A for ; Fri, 14 Apr 2023 10:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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14 Apr 2023 10:43:07 -0700 Subject: [NDCTL PATCH 2/3] ndctl: Add QTG ID support for the memory device From: Dave Jiang To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org Date: Fri, 14 Apr 2023 10:43:07 -0700 Message-ID: <168149418730.4013891.3864941985901182081.stgit@djiang5-mobl3> In-Reply-To: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> References: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add libcxl API to retrieve the QoS Throttling Group (QTG) ID for the memory devices. Two API calls are added. One for 'ram' or 'volatile' mode and another for 'pmem' or 'persistent' mode. Support also added for displaying the QTG ID through the 'cxl list' command. Signed-off-by: Dave Jiang --- cxl/json.c | 12 +++++++++++- cxl/lib/libcxl.c | 20 ++++++++++++++++++++ cxl/lib/libcxl.sym | 2 ++ cxl/lib/private.h | 2 ++ cxl/libcxl.h | 2 ++ 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/cxl/json.c b/cxl/json.c index 8dd65f942c6a..9a508cf7950e 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -486,7 +486,7 @@ struct json_object *util_cxl_memdev_to_json(struct cxl_memdev *memdev, const char *devname = cxl_memdev_get_devname(memdev); struct json_object *jdev, *jobj; unsigned long long serial, size; - int numa_node; + int numa_node, qtg_id; jdev = json_object_new_object(); if (!jdev) @@ -501,6 +501,11 @@ struct json_object *util_cxl_memdev_to_json(struct cxl_memdev *memdev, jobj = util_json_object_size(size, flags); if (jobj) json_object_object_add(jdev, "pmem_size", jobj); + + qtg_id = cxl_memdev_get_pmem_qtg_id(memdev); + jobj = json_object_new_int(qtg_id); + if (jobj) + json_object_object_add(jdev, "qtg_id", jobj); } size = cxl_memdev_get_ram_size(memdev); @@ -508,6 +513,11 @@ struct json_object *util_cxl_memdev_to_json(struct cxl_memdev *memdev, jobj = util_json_object_size(size, flags); if (jobj) json_object_object_add(jdev, "ram_size", jobj); + + qtg_id = cxl_memdev_get_ram_qtg_id(memdev); + jobj = json_object_new_int(qtg_id); + if (jobj) + json_object_object_add(jdev, "qtg_id", jobj); } if (flags & UTIL_JSON_HEALTH) { diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 26985c9344b4..dca1683523a1 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -1210,6 +1210,16 @@ static void *add_cxl_memdev(void *parent, int id, const char *cxlmem_base) goto err_read; memdev->ram_size = strtoull(buf, NULL, 0); + sprintf(path, "%s/pmem/qtg_id", cxlmem_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + goto err_read; + memdev->pmem_qtg_id = atoi(buf); + + sprintf(path, "%s/ram/qtg_id", cxlmem_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + goto err_read; + memdev->ram_qtg_id = atoi(buf); + sprintf(path, "%s/payload_max", cxlmem_base); if (sysfs_read_attr(ctx, path, buf) < 0) goto err_read; @@ -1368,6 +1378,16 @@ CXL_EXPORT unsigned long long cxl_memdev_get_ram_size(struct cxl_memdev *memdev) return memdev->ram_size; } +CXL_EXPORT int cxl_memdev_get_pmem_qtg_id(struct cxl_memdev *memdev) +{ + return memdev->pmem_qtg_id; +} + +CXL_EXPORT int cxl_memdev_get_ram_qtg_id(struct cxl_memdev *memdev) +{ + return memdev->ram_qtg_id; +} + CXL_EXPORT const char *cxl_memdev_get_firmware_verison(struct cxl_memdev *memdev) { return memdev->firmware_version; diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index d1c61f9252fe..60ad16e33f30 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -249,4 +249,6 @@ global: cxl_decoder_create_ram_region; cxl_region_get_daxctl_region; cxl_decoder_get_qtg_id; + cxl_memdev_get_pmem_qtg_id; + cxl_memdev_get_ram_qtg_id; } LIBCXL_4; diff --git a/cxl/lib/private.h b/cxl/lib/private.h index ac6f111b5956..dfd77ff2a781 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -32,6 +32,8 @@ struct cxl_memdev { struct list_node list; unsigned long long pmem_size; unsigned long long ram_size; + int pmem_qtg_id; + int ram_qtg_id; int payload_max; size_t lsa_size; struct kmod_module *module; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 66ce4a021c62..c89806cbbd57 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -47,6 +47,8 @@ int cxl_memdev_get_minor(struct cxl_memdev *memdev); struct cxl_ctx *cxl_memdev_get_ctx(struct cxl_memdev *memdev); unsigned long long cxl_memdev_get_pmem_size(struct cxl_memdev *memdev); unsigned long long cxl_memdev_get_ram_size(struct cxl_memdev *memdev); +int cxl_memdev_get_pmem_qtg_id(struct cxl_memdev *memdev); +int cxl_memdev_get_ram_qtg_id(struct cxl_memdev *memdev); const char *cxl_memdev_get_firmware_verison(struct cxl_memdev *memdev); /* ABI spelling mistakes are forever */ From patchwork Fri Apr 14 17:43:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13211886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AFB0C77B73 for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10680"; a="347247082" X-IronPort-AV: E=Sophos;i="5.99,197,1677571200"; d="scan'208";a="347247082" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2023 10:43:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10680"; a="801281263" X-IronPort-AV: E=Sophos;i="5.99,197,1677571200"; d="scan'208";a="801281263" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.122.87]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2023 10:43:13 -0700 Subject: [NDCTL PATCH 3/3] ndctl: add QTG ID check for region creation From: Dave Jiang To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org Date: Fri, 14 Apr 2023 10:43:13 -0700 Message-ID: <168149419300.4013891.8422712235685320038.stgit@djiang5-mobl3> In-Reply-To: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> References: <168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The CFMWS provides a QTG ID. The kernel driver creates a root decoder that represents the CFMWS. A qtg_id attribute is exported via sysfs for the root decoder. A QTG id is retrieved via QTG ID _DSM from the ACPI0017 device for a CXL memory device. The input for the _DSM is the read and write latency and bandwidth for the path between the device and the CPU. The numbers are constructed by the kernel driver for the _DSM input. When a device is probed, the QTG ID is retrieved. This is useful for a hot-plugged CXL memory device that does not have regions created. Add a check for config check during region creation. Emit a warning if the QTG ID from the root decoder is different than the mem device QTG ID. User parameter options are provided to fail instead of just warning. Signed-off-by: Dave Jiang --- Documentation/cxl/cxl-create-region.txt | 9 +++++ cxl/region.c | 57 ++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/Documentation/cxl/cxl-create-region.txt b/Documentation/cxl/cxl-create-region.txt index f11a412bddfe..9ab2e0fee152 100644 --- a/Documentation/cxl/cxl-create-region.txt +++ b/Documentation/cxl/cxl-create-region.txt @@ -105,6 +105,15 @@ include::bus-option.txt[] supplied, the first cross-host bridge (if available), decoder that supports the largest interleave will be chosen. +-e:: +--strict:: + Enforce strict execution where any potential error will force failure. + For example, if QTG ID mismatches will cause failure. + +-q:: +--no-enforce-qtg:: + Parameter to bypass QTG ID mismatch failure. Will only emit warning. + include::human-option.txt[] include::debug-option.txt[] diff --git a/cxl/region.c b/cxl/region.c index 07ce4a319fd0..6f611799f39f 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -31,6 +31,8 @@ static struct region_params { bool force; bool human; bool debug; + bool strict; + bool no_qtg; } param = { .ways = INT_MAX, .granularity = INT_MAX, @@ -48,6 +50,8 @@ struct parsed_params { const char **argv; struct cxl_decoder *root_decoder; enum cxl_decoder_mode mode; + bool strict; + bool no_qtg; }; enum region_actions { @@ -80,7 +84,9 @@ OPT_STRING('U', "uuid", ¶m.uuid, \ "region uuid", "uuid for the new region (default: autogenerate)"), \ OPT_BOOLEAN('m', "memdevs", ¶m.memdevs, \ "non-option arguments are memdevs"), \ -OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats") +OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats"), \ +OPT_BOOLEAN('e', "strict", ¶m.strict, "strict execution enforcement"), \ +OPT_BOOLEAN('q', "no-enforce-qtg", ¶m.no_qtg, "no enforce of QTG ID") static const struct option create_options[] = { BASE_OPTIONS(), @@ -357,6 +363,9 @@ static int parse_create_options(struct cxl_ctx *ctx, int count, } } + p->strict = param.strict; + p->no_qtg = param.no_qtg; + return 0; } @@ -460,6 +469,50 @@ static void set_type_from_decoder(struct cxl_ctx *ctx, struct parsed_params *p) p->mode = CXL_DECODER_MODE_PMEM; } +static int create_region_validate_qtg_id(struct cxl_ctx *ctx, + struct parsed_params *p) +{ + int root_qtg_id, dev_qtg_id, i; + + root_qtg_id = cxl_decoder_get_qtg_id(p->root_decoder); + if (root_qtg_id == -1) + return 0; + + for (i = 0; i < p->ways; i++) { + struct json_object *jobj = + json_object_array_get_idx(p->memdevs, i); + struct cxl_memdev *memdev = json_object_get_userdata(jobj); + + if (p->mode == CXL_DECODER_MODE_RAM) + dev_qtg_id = cxl_memdev_get_ram_qtg_id(memdev); + else + dev_qtg_id = cxl_memdev_get_pmem_qtg_id(memdev); + + if (dev_qtg_id == -1) + return 0; + + if (root_qtg_id != dev_qtg_id) { + if (p->strict && !p->no_qtg) { + log_err(&rl, "%s QTG ID %d mismatch %s QTG ID %d\n", + cxl_decoder_get_devname(p->root_decoder), + root_qtg_id, + cxl_memdev_get_devname(memdev), + dev_qtg_id); + + return -ENXIO; + } else { + log_notice(&rl, "%s QTG ID %d mismatch %s QTG ID %d\n", + cxl_decoder_get_devname(p->root_decoder), + root_qtg_id, + cxl_memdev_get_devname(memdev), + dev_qtg_id); + } + } + } + + return 0; +} + static int create_region_validate_config(struct cxl_ctx *ctx, struct parsed_params *p) { @@ -500,6 +553,8 @@ found: return rc; collect_minsize(ctx, p); + create_region_validate_qtg_id(ctx, p); + return 0; }