From patchwork Tue Apr 18 22:04:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13216178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 812FBC6FD18 for ; Tue, 18 Apr 2023 22:06:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F074410E1AE; Tue, 18 Apr 2023 22:06:06 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id D412010E1FE for ; Tue, 18 Apr 2023 22:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681855565; x=1713391565; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=k3SQW8TVxQkWa3+pJqsZu6KfI/Imocqc3m3Lpkz0MG8=; b=AgS3lUOOGj6lC6Nc2lLY6B/Um4NeDbQhQFps5cT0LrlmIvHKyCyaEb4Y MLzZoKZI8XI7INjfVtaGoRkaS1+bsBq7gCQV710S8LuiQWdnV9tlpQ2Ju kLr8UTKrYlkcHvrzctm3GGbN2aWfpeS/76b4pQc+DnQthlE0TOSKiMtRe ex/RKcJKvRA5XLnf1KflBSegw7KtEP7gdpCXu6jMkj/4cin99Kit75YtS rZlNBc4T0+Jp99dAexD7GYoRHYdA0xLUfzt9T9is9bfT5h1EybfKuqjrF kDsN5xPpHHQ/JyoVRxIQm4ensd6tRUi4c/xmX6CA69UGWHneHD8sFUNjz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="334101440" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="334101440" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:06:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="684761345" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="684761345" Received: from invictus.jf.intel.com ([10.165.21.201]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:05:59 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Apr 2023 15:04:43 -0700 Message-Id: <20230418220446.2205509-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> References: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915: Use separate "DC off" power well for ADL-P and DG2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Although ADL-P and DG2 both use the same general power well setup, the DC5/DC6 requirements are slightly different which means each platform should have its own "DC off" power well. DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is active. However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be disabled when the PGC or PGD subwells are active; we should be able to remain in these DC states when PGB and general PG2 functionality is in use. v2: Use dc_of as power well name. Move xehpd power domain definitions near power well definition.(Imre) Bspec: 49193 Signed-off-by: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Imre Deak --- .../i915/display/intel_display_power_map.c | 41 +++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 6645eb1911d8..5906b62e79f1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1301,7 +1301,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, */ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, - XELPD_PW_2_POWER_DOMAINS, + XELPD_PW_C_POWER_DOMAINS, + XELPD_PW_D_POWER_DOMAINS, POWER_DOMAIN_PORT_DSI, POWER_DOMAIN_AUDIO_MMIO, POWER_DOMAIN_AUX_A, @@ -1310,14 +1311,18 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, POWER_DOMAIN_DC_OFF, POWER_DOMAIN_INIT); -static const struct i915_power_well_desc xelpd_power_wells_main[] = { +static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = { { .instances = &I915_PW_INSTANCES( I915_PW("DC_off", &xelpd_pwdoms_dc_off, .id = SKL_DISP_DC_OFF), ), .ops = &gen9_dc_off_power_well_ops, - }, { + } +}; + +static const struct i915_power_well_desc xelpd_power_wells_main[] = { + { .instances = &I915_PW_INSTANCES( I915_PW("PW_2", &xelpd_pwdoms_pw_2, .hsw.idx = ICL_PW_CTL_IDX_PW_2, @@ -1400,6 +1405,34 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = { static const struct i915_power_well_desc_list xelpd_power_wells[] = { I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), + I915_PW_DESCRIPTORS(xelpd_power_wells_main), +}; + +I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, + XELPD_PW_2_POWER_DOMAINS, + POWER_DOMAIN_PORT_DSI, + POWER_DOMAIN_AUDIO_MMIO, + POWER_DOMAIN_AUX_A, + POWER_DOMAIN_AUX_B, + POWER_DOMAIN_MODESET, + POWER_DOMAIN_DC_OFF, + POWER_DOMAIN_INIT); + +static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = { + { + .instances = &I915_PW_INSTANCES( + I915_PW("DC_off", &xehpd_pwdoms_dc_off, + .id = SKL_DISP_DC_OFF), + ), + .ops = &gen9_dc_off_power_well_ops, + } +}; + +static const struct i915_power_well_desc_list xehpd_power_wells[] = { + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xehpd_power_wells_dc_off), I915_PW_DESCRIPTORS(xelpd_power_wells_main), }; @@ -1624,6 +1657,8 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) if (DISPLAY_VER(i915) >= 14) return set_power_wells(power_domains, xelpdp_power_wells); + else if (IS_DG2(i915)) + return set_power_wells(power_domains, xehpd_power_wells); else if (DISPLAY_VER(i915) >= 13) return set_power_wells(power_domains, xelpd_power_wells); else if (IS_DG1(i915)) From patchwork Tue Apr 18 22:04:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13216179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 599E8C77B75 for ; Tue, 18 Apr 2023 22:06:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05A6110E1FE; Tue, 18 Apr 2023 22:06:07 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD12610E07B for ; Tue, 18 Apr 2023 22:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681855565; x=1713391565; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ons8xBClW240OsJqsEc6XRz4AzLqtWUQLa8ovoLCxcc=; b=Z0ZpNRNuoyOujJNLu040isY+mOqDXEB9DNuHa1Z20+ZaO6vUbwaW8kV1 RsFhlh4nmFZVlTZQgk9oyB9QXTsUJGr+3hNjy3fiPpSxhsUPnObXXhPdA UBikm82bUwqEqlq8MHoSAcyOBZQFfIM3AysrDCV1UKxos4rEX0W7URXAw VoHm1qqfL9V6dJvJ0s5Debnz7a++a5MBIPfPN64W/9EoPV9k2TqRlxg35 i91D1/BBwVEv4lT3Y3orn7Qxzf3+PHBBJ3IyRNek1peYXEvL2NAwC6u7h L4UEtVvZJSpcer7o3AYzuNRBeRVZDjlDHrwLQOdrrp7wqMo+fEdOkQPcg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="334101438" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="334101438" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:06:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="684761347" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="684761347" Received: from invictus.jf.intel.com ([10.165.21.201]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:05:59 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Apr 2023 15:04:44 -0700 Message-Id: <20230418220446.2205509-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> References: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915/mtl: Re-use ADL-P's "DC off" power well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper As with ADL-P, MTL's "DC off" power well should be a dependency of the PGC and PGD power wells, not the entire PG2 well. In fact, the DC5/DC6 requirements between the two platforms are the same, so the Xe_LPD "DC off" well definition can just be re-used for Xe_LPD+. Bspec: 49193 Signed-off-by: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Imre Deak --- .../drm/i915/display/intel_display_power_map.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 5906b62e79f1..100582f10590 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1456,15 +1456,6 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, XELPDP_PW_2_POWER_DOMAINS, POWER_DOMAIN_INIT); -I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off, - XELPDP_PW_2_POWER_DOMAINS, - POWER_DOMAIN_AUDIO_MMIO, - POWER_DOMAIN_MODESET, - POWER_DOMAIN_AUX_A, - POWER_DOMAIN_AUX_B, - POWER_DOMAIN_DC_OFF, - POWER_DOMAIN_INIT); - I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, POWER_DOMAIN_AUX_USBC1, POWER_DOMAIN_AUX_TBT1); @@ -1483,12 +1474,6 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, static const struct i915_power_well_desc xelpdp_power_wells_main[] = { { - .instances = &I915_PW_INSTANCES( - I915_PW("DC_off", &xelpdp_pwdoms_dc_off, - .id = SKL_DISP_DC_OFF), - ), - .ops = &gen9_dc_off_power_well_ops, - }, { .instances = &I915_PW_INSTANCES( I915_PW("PW_2", &xelpdp_pwdoms_pw_2, .hsw.idx = ICL_PW_CTL_IDX_PW_2, @@ -1545,6 +1530,7 @@ static const struct i915_power_well_desc xelpdp_power_wells_main[] = { static const struct i915_power_well_desc_list xelpdp_power_wells[] = { I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), I915_PW_DESCRIPTORS(xelpdp_power_wells_main), }; From patchwork Tue Apr 18 22:04:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13216177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E514C77B76 for ; Tue, 18 Apr 2023 22:06:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B039A10E07B; Tue, 18 Apr 2023 22:06:06 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8585210E1AE for ; Tue, 18 Apr 2023 22:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681855565; x=1713391565; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=bHRnNR0You1Crdm8kE51zXEoqYKC3SUaSfoNn79NMGA=; b=QpIODxRsUGdrTCJD1oxd7syRohubQx3MS9rQq9gpbC7E/EiS4LqAOM85 4hDnF5yCY7vXeStmeimmekzaOaQevpyW8FyUS+T3vIp7wLieHYW2qOmjz UMXC3YQbvV5wWHVl/4TbQJyIREXk6wick0F8qy2IjcnOlHaWubF2S9XSJ WhLTALfr43/PWgRbvTidSpAytIdTlkHGQ4v9kfi3anHrp7izbICj0c6i+ 5Ew5HqwxaBATWmFJybu5/DNMZ//04o9Nr8uAb4xc7Wvuj1t/DEYPDH/BR 3oRBQLzeoJgvm+nrMRFp3hRDGInVSoFtzs0FakvohKegZgMGlqTxb/FHV A==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="334101437" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="334101437" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:06:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="684761348" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="684761348" Received: from invictus.jf.intel.com ([10.165.21.201]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:05:59 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Apr 2023 15:04:45 -0700 Message-Id: <20230418220446.2205509-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> References: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Extend Wa_22011802037 to MTL A-step X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Madhumitha Tolakanahalli Pradeep Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch updates the if statement to apply the W/A to right platforms and extends it to MTL-M:A step. v1.1: Fix checkpatch warning. v2: Change the check to reflect the wa at other palces(Lucas) Cc: Lucas De Marchi Cc: Umesh Nerlige Ramappa Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Atwood --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 88e881b100cf..ee3e8352637f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1629,16 +1629,16 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) static void guc_engine_reset_prepare(struct intel_engine_cs *engine) { - if (!IS_GRAPHICS_VER(engine->i915, 11, 12)) - return; - - intel_engine_stop_cs(engine); - /* * Wa_22011802037: In addition to stopping the cs, we need * to wait for any pending mi force wakeups */ - intel_engine_wait_for_pending_mi_fw(engine); + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) || + (GRAPHICS_VER(engine->i915) >= 11 && + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) { + intel_engine_stop_cs(engine); + intel_engine_wait_for_pending_mi_fw(engine); + } } static void guc_reset_nop(struct intel_engine_cs *engine) From patchwork Tue Apr 18 22:04:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13216181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FADFC77B76 for ; Tue, 18 Apr 2023 22:06:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC36110E38C; Tue, 18 Apr 2023 22:06:07 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3FBE10E1AE for ; Tue, 18 Apr 2023 22:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681855565; x=1713391565; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=of4x/vNJv6FDQNbPAHMzoGAmHFFniPjtp6JKdiSmOOw=; b=C5duL4SWGXbcBX6viwACUhSn4Lcpdh4FJ2wILfBLA/JMQBaPhKoUQxgu td/V0YGO9gZXvAPaJE4+V5ijSiIXgOCqKtxe+GYmclGdsSorPNEIS3Zq8 LJnauo7VibOytSzMEyLjeEyUQr8g+OFxjAkE6m6M3O/rWTZ3Xt728igyZ D45dHZnR6k7bkfw3C8hZesA1sf65LT52iAFtZVvpJpkETQKw5Mg/kgnRe ptbmANIxJvNmxC0Mwi1VGUlm/iWiHhv/ToacJgd+Ih1lByzazjxnY248q +58v8Ut8gItcdfTVm4W9/CDys9HIQW9mETpnh0WHFK3A2QeGTYE2sMsVM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="334101441" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="334101441" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:06:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="684761349" X-IronPort-AV: E=Sophos;i="5.99,207,1677571200"; d="scan'208";a="684761349" Received: from invictus.jf.intel.com ([10.165.21.201]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 15:05:59 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Apr 2023 15:04:46 -0700 Message-Id: <20230418220446.2205509-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> References: <20230418220446.2205509-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl: WA to clear RDOP clock gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Haridhar Kalvala Workaround implementation to clear RDOP clock gating. Bspec: 33453 Signed-off-by: Haridhar Kalvala Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b925ef47304b..312eb8b5f949 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1703,6 +1703,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_18018781329 */ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + + /* Wa_14015795083 */ + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); } /*