From patchwork Wed Apr 19 14:41:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A60EC77B75 for ; Wed, 19 Apr 2023 14:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233298AbjDSOmC (ORCPT ); Wed, 19 Apr 2023 10:42:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233156AbjDSOmB (ORCPT ); Wed, 19 Apr 2023 10:42:01 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7A204498 for ; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id he11-20020a05600c540b00b003ef6d684102so1574565wmb.3 for ; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915317; x=1684507317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wjVkI26ktyzhtjOsKUbgQ/T3RC2e+nJ5jKr99N5QLxk=; b=AeZ5wZNOUYoYPs5fgNoP8PdwWIcNz4Z/e3ZezkcapR7aowdJKgC1qzudkN5BlBXNRI dvsMRSK+RjjjukorQ5FGHQ/nxHuIWTzMLeDaRyNTze7Mw1cgDimNjpUWTHZxx468qJ8p +HlqpUhaLh2QK5ocROi74En0/O2DuxlO3Yv947RUystfy6A9BtHP4gVqBA5KBslBf4D9 tNJ+ynn2NSpGUIw6agSyBfBTTReLOSo5hQiNAb38dyAp195SYbMc6JP2z/bxEYBOldeH 5e4kKFeEpXtuT+a+GQGJekQErc0IIouDbFt4BZR8kG7kVpz14DT6cbwv2Q6tcyUac0BL aSBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915317; x=1684507317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wjVkI26ktyzhtjOsKUbgQ/T3RC2e+nJ5jKr99N5QLxk=; b=AQvJCauFIir022l0pHTHceTe5lIEXrFLdQ5u9eZB2VJ0wskMvITZfZkxak9p/8ShJ1 icYURCbqGQBfXaSoto5b3FcrjIjz3mnRUVQFyXZqXUBnATyyToSCz9Tn/18UO2ZC6uMO JEJEOR2PwRo8EKG7U6yt2A4oBPzxyb88DUSALgKT4PcbuFKq7S1XjjPjv/35ucLQ9RIK fJ7JpyMU8RaCQltUvFhEXeGb7nZpX6AgpinJkFcdLAOqmHkyUI2g1VKq4XSsNW5lmLdx 6Y++9I5aIxEeJpu/s0NPrVnZlZBdixPte7HBexAinzrIh2tgmT4O9SWbV4V9sZTdSgwp qiBg== X-Gm-Message-State: AAQBX9de6i3b2nTGQ9c8y2InFyt+N+NPooh5CeDgIjGZsR2gufm1CiBc mPxqi8Wc2URtJYHlQjkSK3os X-Google-Smtp-Source: AKy350ZcNupwHGBZjEI280w1ioDt5z0GPVDCdkjsvwcMlHTWQs+YYZUMYCf0fMhNz23gUlPPug9FnA== X-Received: by 2002:a05:600c:29a:b0:3f1:812d:1da3 with SMTP id 26-20020a05600c029a00b003f1812d1da3mr1940451wmk.0.1681915317020; Wed, 19 Apr 2023 07:41:57 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:56 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:08 +0200 Subject: [PATCH 01/11] drm/msm/dpu: tweak msm8998 hw catalog values MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-1-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3140; i=avrac@freebox.fr; h=from:subject:message-id; bh=gB8ZsOHFL4x3EB7vXs6RfTwFIPJcSDxcT/siRq2GA3s=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2VddP7RU1bYLLmSl4kfr77zabyBkRunXdwq 411aLLBpT6JAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9lQAKCRBxA//ZuzQ0 q7qmD/4xx2UzzY0W4NeutA+GaKEnyyJOCkKSCp5jUU39iHLToHX6skayzh4bj2cOBt7IuQV3IgH MIbn9IgrxGTW/GfBVldzbonxWBanXM1IeX4ZTYXFWZJVlXuVkxi898FXJQOzK7+ZXbgx5C4O3tw cxayJxCxkYtgW0WR8ytc0+HvkzhoJbC83tnD/xhG0YTx+NwKmD6pNoLt65On7QbT0SnVJGGJ+jb 5rWpuBHh44X3519ybO4oJ4oq0zuONvtCgwEgCabZe/yXD5/OnOEAdJKiNKDxkLk2cX//5p5n5dr +oB9QxeYN4ukP0iXTkZDpdn+oNBeiHsf4m/yh6iyJEl3zKm9XeYPuhWFLlPxqSGbxuuRprX6AHk 21YtohQZyXdzFTFAgT6xc5t679yIrlVzOZWbrbOdCt2x7xgiokHqPs4gzzdZ81TxYsqI2etM+wk 2PyJOJ62QDbx6Q97OYaQ2xri0hPbaheYqGIjInLVYIoqwfA5+8sWPTWxBU1xAgxFo/ALvgCizdZ o4p18KSQXKSHpzp1MYanVWOTJ7x1DnfY4umwkjgcg7JVrrln1xJUyWgvxq7qcNv2cdeL5C4Ejxx YeF1EWh27ZjnL1cUvyH1PLw/Y6ftvbQZCOWFYeMSr028jkehmfYnAFtXyFu5hC3TpqQ6lL/2QQs GGqHs4YNJ94GSEw== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Match the values found in the downstream msm-4.4 kernel sde driver. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 +++++---------- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 2b3ae84057dfe..b07e8a9941f79 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -134,10 +134,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = { }; static const struct dpu_intf_cfg msm8998_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; static const struct dpu_perf_cfg msm8998_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 03f162af1a50b..8d5d782a43398 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -587,12 +587,12 @@ static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { { - .pps = 1088 * 1920 * 30, + .pps = 1920 * 1080 * 30, .ot_limit = 2, }, { - .pps = 1088 * 1920 * 60, - .ot_limit = 6, + .pps = 1920 * 1080 * 60, + .ot_limit = 4, }, { .pps = 3840 * 2160 * 30, @@ -705,10 +705,7 @@ static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { {.fl = 10, .lut = 0x1555b}, {.fl = 11, .lut = 0x5555b}, {.fl = 12, .lut = 0x15555b}, - {.fl = 13, .lut = 0x55555b}, - {.fl = 14, .lut = 0}, - {.fl = 1, .lut = 0x1b}, - {.fl = 0, .lut = 0} + {.fl = 0, .lut = 0x55555b} }; static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { @@ -730,9 +727,7 @@ static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { {.fl = 10, .lut = 0x1aaff}, {.fl = 11, .lut = 0x5aaff}, {.fl = 12, .lut = 0x15aaff}, - {.fl = 13, .lut = 0x55aaff}, - {.fl = 1, .lut = 0x1aaff}, - {.fl = 0, .lut = 0}, + {.fl = 0, .lut = 0x55aaff}, }; static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { From patchwork Wed Apr 19 14:41:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94431C6FD18 for ; Wed, 19 Apr 2023 14:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233424AbjDSOmF (ORCPT ); Wed, 19 Apr 2023 10:42:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233331AbjDSOmD (ORCPT ); Wed, 19 Apr 2023 10:42:03 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E64A744A7 for ; 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:57 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:09 +0200 Subject: [PATCH 02/11] drm/msm/dpu: use the actual lm maximum width instead of a hardcoded value MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-2-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1453; i=avrac@freebox.fr; h=from:subject:message-id; bh=F1W/wchYMCu2VjLqHH6U+LrWUMc7lJp207y9YaxngyM=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2YRHSjxXabDh0Gu+NKzHbr/LV2esVhNCjWe gUDIZ3V20WJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9mAAKCRBxA//ZuzQ0 q9tYD/9LxTx1cpzUZKY3M7CrNX2Jf6IGVMYxyJqcOvjHmPaMEElWxCjSZ2oY2ZbE+F1S6z5JPsq P9UgmupIvqwIEvcsVnhcvW1wXyfcPH8xyZ8kRhW4LQIfS3VW/ySRdNndBtPtjVVRFJzvOiZHDVd MWcdkols1Sb8bAPlDeuXffjYMWYkzgqcDzJk7Iq5FerkvkQt91s18X7Mht3pKgvlak4SdMYXKpc kE5ULRYhNvt8XbKAUPTDDLMZo4XrsGo+fua4M8AXfPp0du/QMqlP7SxL6NadQfsINl5RuQUlmyq 0lf64+UUU2Als0GNKEvEAmy4sv8iQBv0rru0jzDW5jlw/aarbONgpxYDcIcQHoesDAOTa4WA6dO OiDqWXskg/QCG7LYfo9JSg0S9ohG6dC+sE+bypkM+TqNLcobWOVObLs6dYOhMBGhxD0SW0HCLC5 hIjiQVeoupzgYXhjJeLJjEZtiwsTx0OPxXL67WzZ4Tfs7UzTOi0XVVqa4kl3K8xXp3Ybj3xCPPf Q+ToaLhrxKsyuA8VeXC2yCWM7d5o5tfG6oohLDoqeXB2Jd5nj8Oo8jWeoUDUfG+bGliN+CXIkF1 XM2LKRVo2Hl1KwyNWNHGUsnlUE7mPmB2QoZREpw7VhwsTDdvAWMpV3ZKTJkXkuH6Ir/ouEFm/oE 3txKrd1uS68t15g== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This avoids using two LMs instead of one when the display width is lower than the maximum supported value. For example on MSM8996/MSM8998, the actual maxwidth is 2560, so we would use two LMs for 1280x720 or 1920x1080 resolutions, while one is enough. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1dc5dbe585723..dd2914726c4f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -53,8 +53,6 @@ #define IDLE_SHORT_TIMEOUT 1 -#define MAX_HDISPLAY_SPLIT 1080 - /* timeout in frames waiting for frame done */ #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 @@ -568,10 +566,12 @@ static struct msm_display_topology dpu_encoder_get_topology( */ if (intf_count == 2) topology.num_lm = 2; - else if (!dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = 1; + else if (dpu_kms->catalog->caps->has_3d_merge && + dpu_kms->catalog->mixer_count > 0 && + mode->hdisplay > dpu_kms->catalog->mixer[0].sblk->maxwidth) + topology.num_lm = 2; else - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm = 1; if (crtc_state->ctm) topology.num_dspp = topology.num_lm; From patchwork Wed Apr 19 14:41:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1BE3C77B75 for ; Wed, 19 Apr 2023 14:42:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233431AbjDSOmG (ORCPT ); Wed, 19 Apr 2023 10:42:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233356AbjDSOmD (ORCPT ); Wed, 19 Apr 2023 10:42:03 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BA7444B7 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-2f4c431f69cso2077244f8f.0 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=836GTkcDRi2+2z0HJ4qWmHnCerN9xvuUtbFVbOWzfY0=; b=baHQi3d04LBNOBuAxmRa8A+HZi0CSATDXEXKALd54qg51/ZMXTqiy/deoAlkXb3Ns9 T+7hwNDw6PJ6AJioYgA3neZjGdb0E+DSnI4WFeL19+FqCrQ2TFEdzEpMqcf9Zuh0+Olb bR6FK5w/+QNuNiosi3B6uEqaev9iIsq+N7brfgCjDtj7AK2Q8QDjIPOGPmWzeiFwc1PL wBpJqQpYCc1V8qtcAfOEnji2mEh9INPZjNEhYmM/fB3Cix1AhN6yPCbxq7ApO1j04GFt rLJrMHNshKmCbGx/jQfiDwTnDNcHtLBcmqDnULs9eYjA6+JImyz4vaF+Mqnn7ApLKuOS qoog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=836GTkcDRi2+2z0HJ4qWmHnCerN9xvuUtbFVbOWzfY0=; b=V3jJfcOK/9WXZdfkBoKWM+Xom7uFU/Pc3h8ZZWQ0IyHTukAPp2OF6NY/LoinkQTXyU 860qu+70KQYgyo2vmMe+17kTj9+Akr+mNgr4QWwHZSL4kMpn3zTKNjxHT1Cp0Opb5OaR S4gHycsn8irTXLwTYiotIpmnAmjEkjfHhVQuZ9os4jpYlzGIBfdpUs1asbEXiOIBbtub eu07UDp50dPen5RxlYNyl6h8dOWP/XomI7+4hm1VDAftDIfHiEQIxl3P7E7AWfU6XqzI BI+KwJWo5SZ1I7iepkeMLmIR3gYCNx0OiQt9bVE4aE9xIiLk7HayhnTuat/Be5eXgN8/ YNhQ== X-Gm-Message-State: AAQBX9faI5Efoa2nIqYEAY+VO9XOvZqNCSfM+bnocizh4HPZiY2QN9Vn 5DdVGrjiSLgzOeM9XfRJOGnt X-Google-Smtp-Source: AKy350Z3Xuz9WufoZqxCoYxbq0Xd6W5KfFcqPnl3JWZpyOuA2xlpK+wbnSrbTuHAqTHqR57P3f6p4g== X-Received: by 2002:a05:6000:c8:b0:2f8:e652:dc04 with SMTP id q8-20020a05600000c800b002f8e652dc04mr4711567wrx.45.1681915317898; Wed, 19 Apr 2023 07:41:57 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:57 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:10 +0200 Subject: [PATCH 03/11] drm/msm/dpu: use hsync/vsync polarity set by the encoder MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-3-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2002; i=avrac@freebox.fr; h=from:subject:message-id; bh=xpOaiqpNNEOLuHJaoCWSS7YKv71vYiVAS0+zh3bWo5U=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2aYvMBvH6zGssGiiSjbchn7LFtzFExHjPPk Uu7xG862vKJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9mgAKCRBxA//ZuzQ0 qwsqD/42uGbh/PrZu04lyUsR5hVCa7Xmdo0LCCazacHEC/BYFFlGvWNkhc7PsrezO3YdP7YUkAV odihBbhCD/J0kexfj085S9cV1BHejLPWRGLDXOkPAaHolB8DRGM7GfBKbLkvaQE6di3lIA6lJDa M/27C2U9iKWSa8VxVhARC5feO5zeTnJJ2khmElSSMb+ycMbEX9a4N+nRvfKN9eSW65dqzzOWR15 Ti9QXnMq/8FsyVWim/cQvMa8pcZAd9bQvuiJveRI4qoUuil0WTmIFhrwGs+J5PSG0j85xi2LAhu UdgEhL4yD8b/DavQRt8bE8JCT8TlSkCv0hLJGBtmHhxKVHqLZVDpO7Xbq8JnX4hVAWQDEVFFOeb aU3vXMTGEpZ2/g11Bvn3aKpqdgeOXCeuvWHaBPK5K/gx3MuE/kRlhEhl30NFeQH6jyNbkNyy0xZ q9sGqtnNHTLzsWoxxgc16ztUfL9hpLW51GsWAR1vSqcNEfYNnZjBEeaFb5uFlouYRWNFZxuayDJ r4PfnBf6O1hgZ63ok55tnZAmvqXF7/mxr91e5diSyx4BTnlxuW0joKDZh11kkLcGacGdj431Tdw AxpGO6avO+otXYsvvZ0/H7YXwSJhlklY5/f+UMZSM6udGdxoqGVGdCpwjc3NKdsTtHizBlKtDvj 9F8RSxj5MR9u+LA== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Do not override the hsync/vsync polarity passed by the encoder when setting up intf timings. The same logic was used in both the encoder and intf code to set the DP and DSI polarities, so those interfaces are not impacted. However for HDMI, the polarities were overriden to static values based on the vertical resolution, instead of using the actual mode polarities. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 84ee2efa9c664..9f05417eb1213 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -104,7 +104,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, u32 active_h_start, active_h_end; u32 active_v_start, active_v_end; u32 active_hctl, display_hctl, hsync_ctl; - u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; + u32 polarity_ctl, den_polarity; u32 panel_format; u32 intf_cfg, intf_cfg2 = 0; u32 display_data_hctl = 0, active_data_hctl = 0; @@ -191,19 +191,9 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, } den_polarity = 0; - if (ctx->cap->type == INTF_HDMI) { - hsync_polarity = p->yres >= 720 ? 0 : 1; - vsync_polarity = p->yres >= 720 ? 0 : 1; - } else if (ctx->cap->type == INTF_DP) { - hsync_polarity = p->hsync_polarity; - vsync_polarity = p->vsync_polarity; - } else { - hsync_polarity = 0; - vsync_polarity = 0; - } polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ - (vsync_polarity << 1) | /* VSYNC Polarity */ - (hsync_polarity << 0); /* HSYNC Polarity */ + (p->vsync_polarity << 1) | /* VSYNC Polarity */ + (p->hsync_polarity << 0); /* HSYNC Polarity */ if (!DPU_FORMAT_IS_YUV(fmt)) panel_format = (fmt->bits[C0_G_Y] | From patchwork Wed Apr 19 14:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D650BC6FD18 for ; Wed, 19 Apr 2023 14:42:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233465AbjDSOmO (ORCPT ); Wed, 19 Apr 2023 10:42:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233378AbjDSOmE (ORCPT ); Wed, 19 Apr 2023 10:42:04 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C714046A1 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id d8-20020a05600c3ac800b003ee6e324b19so1556595wms.1 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gvyREH2toDbRX8jPDQqcQOz9n9jRJ61Ib08FCCvn3Ik=; b=fiEmjRI5sy66IY14yPYdCnD3Wng5CaWmy8/JWcrmhUpLJm++qPxhqYFuZBBwad2Bk1 fRC3PzylukzxUDXSaONiWypd1Qdz05sGYKefLuw6OlnX0ItB1uSbRHZ8BB9JEI+2f4tG ODTG+NUZEU6Bz49uGDl1rbfofa0a2OQPMnNxd0z56unCc1W9/2JHjUzvzMqYysrAmn2e LM8DuZQPfdNstgogGHSUQYrwhPTNUpWSVbCBuwrTjhnRPl/iUG/dltawjO0l42MNo37i irA1ZHZz+utK25dZM6ERc+rbyPl/k+FsCapqQdUoNmpPXQDwJMZc43wHrPLb2/Bemt4m 1iTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gvyREH2toDbRX8jPDQqcQOz9n9jRJ61Ib08FCCvn3Ik=; b=lr3T89843hqeWdns0v8i//N+duKS30aTv1TiLQiK0avxz5TZf1pFO0b+6z12e3NfJ3 acdDHE9ZzAJa+YoLamte9UyiEdx3q7X+XwsUtDZCSPEc9lIWSOWuqAsBmzxnC8VJ5Km7 8o+iI7oTF+h+es5SPOq6DQwy++cu4cAAKZqlKqNodUCsKmWdr5c7To6n2PJXmQvxGhQK 5n0pECpVKK2K46YnysnRFm9wWeeFiO7yoOJiFTJsAbWlGGettubKXmJ+Ui3ENWr1SD4P C08YUZY1xPx2+RqW82FxFrftDRCANE0UDaBK9Y8n51cEBj4mdytGiV3r0F+jrpRmIdQF b11w== X-Gm-Message-State: AAQBX9d2U3UGYU7QyQ3t5fOFOwAn6jv93ZmZ93/fePK4WnN5PN6K82gu gVCO9ncKkHtlwoOkocN8Wy3n X-Google-Smtp-Source: AKy350Y41eDbjV44lpKj/xlTrUrnQ2HFRVzK6oIGLJjemuk1KHFBsUN/7nExtMcIBIBSxZ+5N0s1qw== X-Received: by 2002:a1c:740d:0:b0:3f0:3d47:2cc5 with SMTP id p13-20020a1c740d000000b003f03d472cc5mr17091590wmc.10.1681915318268; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:11 +0200 Subject: [PATCH 04/11] drm/msm/dpu: allow using lm mixer base stage MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-4-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1074; i=avrac@freebox.fr; h=from:subject:message-id; bh=NbkvlB+Rp9R8nBIqIbNdud3AhKbbO3pB8C+IbGJ1/iw=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2cS8NGHA5wCfb2NpdA7+TL/3Juvg4voqljd dCN9998hUiJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9nAAKCRBxA//ZuzQ0 qzq2EAC8YPFyE4WUiu8BKSb1ZitW40OEsReZvh9sxbDZTP3qWZ+pC1T6aDRLrWtGd01II9zSvnZ 1e1WtK52yoxgFMMIs9m76wrqd+HyouhNxyA49sA+TJ54CNigIw70r1AjmJlKxS5t4D7JONHX8EN 8WcDnTOyTyjhOSuR7GMbNNQvMSoyIbLnBwDQi2JgPFIH74gUttelxpiXYp/o3BlfmCvu+jFUJ0m 6DvZ646BwFhHgi+WdDeR0xa1UHABA2DR5YfRKQEfsd37Utg/ljJuurZ+676ax7Q/f+x5nhrv6tQ 3MFCvmBJ0WPec4eyrvX/O5sqBeYoGrluaPJwBbwwerXAypw1clzFh5o90KY3sr1APTgKO8fNdWa dWf31VLcAWvEOm552brE5gYPZ3nmq151VbNilEz0wGK9BrzP6aiA3PvLX4iJpj9MxEwGlB13zuL efJ1ZwqB7FcJZB73j5f4OpckUi5z6ytaxwbNhEs/Ls8H59xlpsey2J2pvhfQIayi+nKxgF2mZLX nknVZm6xJQd8qjCKv31ErlindIv/OJMLYWB8CGTjLDSredGRtnPUyTHFPl192rjH4UydVVLvf3N BB9TxwJFD+a2TxomXyKgp7DOHsOjeQeReXiNxSuqzfxaFm2ti/HxPir504dyFomWRoUK2BxkKLW pB4JplwICLGWejQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The dpu backend already handles applying alpha to the base stage, so we can use it to render the bottom plane in all cases. This allows mixing one additional plane with the hardware mixer. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 14b5cfe306113..148921ed62f85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -881,7 +881,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->sspp = NULL; - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); From patchwork Wed Apr 19 14:41:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8868C77B73 for ; Wed, 19 Apr 2023 14:42:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233364AbjDSOmQ (ORCPT ); Wed, 19 Apr 2023 10:42:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233379AbjDSOmE (ORCPT ); Wed, 19 Apr 2023 10:42:04 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 437E040FE for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id v10so10607949wmn.5 for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IVSa3v9KsJg/92VqlTELAV8syGj4pvx3zjA8ESRGdaw=; b=uXSH5qJybjPTZGPMwftuPl8wsOD+ae7+MkZoy48K6gde/MsLM7C3IxMRkoquOgGwEj said5iJMtae7d0h7mjDwvaLZRyja7XLrcZli50caoBfCpROYKO9ZC4QM+sMACjxjFFuJ JQbmkCrnH1RDgN2umeuiRe3M9QmHcyYOZllCLg2a/vDt86gAcKsjivIo7GLZWGgETPNX 3U42L+bvrWt0mn7hyoKm/RkPCi9OKVmJ/ZGw3nR16KZI+1XMZcEDLaFf1TpTRNbciPur Hx+0rMkNmCBlcLgqNLUjbx2k6MUXPmHzdmYpAIJSDBt9liA3lxhiC2D4GXYSyWAiFM+5 MF8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IVSa3v9KsJg/92VqlTELAV8syGj4pvx3zjA8ESRGdaw=; b=SplE6eW3Z4OsmPCKs7rRE4g9k9btHA70oLcaCO0vhFA23fWiSd5Gf7HctEaasXACc9 cY0n0m1f0avf21KuBIUu9OBQCTHBOWGOiILAVZ1jSfUUbfGkUmtY3jiBuJP3I3/gHsxx vlmduaXfBQaaiBlJ+X3GfOWQXUTjbmSka2R4ISx/m5hI3qg9exnIEa7CUTcpin2IWpg2 6gaSKnezmS0v/Kd2lk7nP6zSCKu1UYAumeMsedhRG7zGB4nHjmSHAVJMMDMpXuawHWtu 1u+IqR4rYNQOlZGWbOi/EZ4fX0qBPi6YqUi5NVOoURrnNJ4Lap/a+bUg/Q9gu9qmNkm8 AZCg== X-Gm-Message-State: AAQBX9fNp8qDS+aXCwC6dqwsZgH7wr5FUfAgRAzIGF+pDRBHo55+wlQw AFuD67ZlRu2I4M/h+DvIhJpR X-Google-Smtp-Source: AKy350bGlmQmMtXg9CozuDIW9XuYDCQgxYNBmMpzExRWiBSBCFebEa48q9C8fW7LnLJHgnHzr4pg/w== X-Received: by 2002:a1c:ed07:0:b0:3ef:6eeb:c25a with SMTP id l7-20020a1ced07000000b003ef6eebc25amr16057062wmh.6.1681915318699; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:12 +0200 Subject: [PATCH 05/11] drm/msm/dpu: allow using all lm mixer stages MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-5-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1211; i=avrac@freebox.fr; h=from:subject:message-id; bh=CDBIvOWtwi9aZ7RRIDQqd7SRtuQgF7hezIg0kgVuXhA=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2dJRmjvyQIHMA35EzFtdfeQCWdKsmoqxMyC KhTYcFPJ+OJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9nQAKCRBxA//ZuzQ0 q0X5D/0aSHCjp0ig81KYbJRs3J6FjRqaFku3XF7PaHPJLMriUUmk19hVcxaYBNWKsKxBq3f3k1+ SJL2G79OCXfM30ongZgZ57t4BMp/lmOrnOguLlj+6n5RLVJ8KvkGHMVL7pA5o/1YEMP6k1SVH5B sFhAc/t99qssE0rjEtIZDSR96Bg2ZRUaWBjBK8ddEnghwXtojkv0Udb7cJywJ25X7T3IH8RpXln +fA6sGohtUZ+T/a6ieO6p4Kk3bFUVG2p8MVzCFlMjkjdoWqdNTj5rc6IwNL8UR9R7PZED4bID7G ZzsZUtTbj/h13CL7UmnG28jvU2jUsHX5VLJOmrh0RgfKG4Gq2CX0FgEF9ejE1ISmJTxwf4npwK5 nMYyAVPdje7ca2sAx56wDAfKglSSahk9L7r8NAOb0ArKKe2qN4ZJ/DzmE1tfmFRon+xPuxwYLpj c61NMrfMeOM8ykBLgOSOwzUvUhzcrAhBlMDq4C73aZA8QTKD2BRwaqyBVa4IJY2A1MfClyuWInq QoVbFCxb71ZE3VHuv3GIyLfNuAWr2JOMj0KLYsragK1vDks+eOOWgdrzPA9FXFEeF7i+g2kZjYl L5ZkcSgBt10Jacwq8m6jQSUuwI0Wh6mX+UNFVRQoLxnf/Nf4aJRkFCo6bPMSCbs+GirNvCuC2ou 7vnXujDg35QAmKQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The max_mixer_blendstages hw catalog property represents the number of planes that can be blended by the lm mixer, excluding the base stage, so adjust the check for the number of currently assigned planes accordingly. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 148921ed62f85..128ecdc145260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -882,9 +882,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->sspp = NULL; pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; - if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { - DPU_ERROR("> %d plane stages assigned\n", - pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + if (pstate->stage > DPU_STAGE_BASE + pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane mixer stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages); return -EINVAL; } From patchwork Wed Apr 19 14:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C73C77B7C for ; Wed, 19 Apr 2023 14:42:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233317AbjDSOmS (ORCPT ); Wed, 19 Apr 2023 10:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233406AbjDSOmE (ORCPT ); Wed, 19 Apr 2023 10:42:04 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64A54C20 for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id v3so4205020wml.0 for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915319; x=1684507319; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hkfWN99F4hBvx1XEfrJngIeLn15ofD5JlY1D197wDT8=; b=3Cxnjb3YswWA056HbGtIB6yadcSK4Yw3KDO0AMN47lIDDhRRgAWvheSzQq8kp0BwkS 2Nyc/uYul5Iv+c4Vbn9nFXOMVfRBohbbkWocAG3ZKtrNETAr4kStKiew2dhHkoeXzs6n bzcnOQt5hzd8m4iwwFPB4/orgBLtAHK+7O5n7QbqgrwmHWC3l7rkPq1mY9mwqiS6HBxG e2fgrzmdzmEffoQJIBtRek/UGiI0KqVKa87HhQJNF7bqzvlUg1jg1fGwcmwQYAzmUiGE KIIJDqCPxUwSRyC0bwipOmSllHVYHwHwVEGrxinDD/uJVSl5iD1zA/Xz68bpvzAxAfbq S+YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915319; x=1684507319; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hkfWN99F4hBvx1XEfrJngIeLn15ofD5JlY1D197wDT8=; b=kjkZSwfzgvS3ZZmPz6FXr0d92QojpSwDbIBTJQuFocMhytKLH17cVdLr9NgUzrQplq YY15k5jMhdAxu5zO4AK32nAUCiv/SNQKcQquPKgVHzDUXkORXCrscmpUsyAOEtvrPt0d 0IbPetz9ZutxJFZePetb1Dxb/mbjgBbprkm4xewWrAH5UpTYMRYazEIU0xOevlQnWJrS BLmIza7K6uRqMVW6XcTh35BWuEGmrswS5wlp6AKBUf8C32cAlE4TTRGRCrOQ6CfbDW4j I4sU+MoY8i/jUPqnrjpYJT1zllch7hd21SDxgHXkKKdR0NUlcEZHMZKGN27lOPznMN6A sSgg== X-Gm-Message-State: AAQBX9e9UPuxGfR2Tvz1dMQzmv8r0pRYdRUXK7IIFPbiNMaBlSDFeKNr /FKq32uXq8wqfgN94sXpg2jS X-Google-Smtp-Source: AKy350Z4XvreRKuse360cUN0YJiTS3FQn+PMeJOel2baif9x0ixM+kMjMz4P1+eNretMarvSA/00hQ== X-Received: by 2002:a7b:ce89:0:b0:3f0:68ce:5465 with SMTP id q9-20020a7bce89000000b003f068ce5465mr17171216wmj.7.1681915319103; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:13 +0200 Subject: [PATCH 06/11] drm/msm/dpu: support cursor sspp hw blocks MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-6-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4055; i=avrac@freebox.fr; h=from:subject:message-id; bh=JIN3wOAwRVDkVnPtsZfcQyHShaT43mZJjQaS4MuN1UU=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2izIHn4G021J6ANBFbFX+WtbijpqW9KvBFY pB2QJc9EzyJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9ogAKCRBxA//ZuzQ0 qx3jD/wP2/AD6Il7RXMRRrIsrRVYu3W++Ep5Yc+PFxyTi5+BnuCvuv8VakNG1e9ubJ6WWyT6d3b xnctAKrsGKFOMyC/7mGJ9+5CwR0EJ9Hn1DZVfZ3S0RZng8TxD5CUAHlSJifKfvZEh8PHlNoABuP 9LX2eXedY1HDcoYeLFKer1BD19/6V03G0E+HwgKWlUtHuI3sZlyWdB5lMBFdM6MbfApECvNXWBl vfYNv7JxAlf9KVBpc66UfCKuBwjakG19dvxDeodFnGVCHINs5yIW1+W/jUz85vadPUempbJWlwk bZHLkqbdtptrzTVYcGRJ8H+JRv4wCi4maG3l4Y407VPtYkTJJJyLhhZ6Ktgz1m5WHfOUI+wB1VT 0+EX9Jm+qyFY3MxTDmd2GJi8rElsK87p+D+/jLszbWnJrA64jmazciEODemu0wVL+MPqX9bNbPs wn0XE7GOtU7oFE8pvtZFoR3iPkfiYSj6tRy57NAMeD7xDbGZ46nOOdNhiml0pHqtpB8MeNyf3iz B+Hor7gxz7abwgQfN+S6FoKrBLWdnwzoa7TQU33PxQhc6A1tQwf5cm+z3cxLKR+MiKjhlDRcftN PHyhv3TtV9vcPpnXk1LHLSXHHlrWG4ySJTmft2kGccJXG3UlJfkV7DBhVnjkv8WWcZYTBJLuBgE x9mqsOvYDGc2YTQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Cursor SSPP must be assigned to the last mixer stage, so we assign an immutable zpos property with a value higher than primary/overlay planes, to ensure it will always be on top. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0e7a68714e9e1..6cce0f6cfcb01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -738,13 +738,22 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) for (i = 0; i < catalog->sspp_count; i++) { enum drm_plane_type type; - if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) - && cursor_planes_idx < max_crtc_count) - type = DRM_PLANE_TYPE_CURSOR; - else if (primary_planes_idx < max_crtc_count) + if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) { + if (cursor_planes_idx < max_crtc_count) { + type = DRM_PLANE_TYPE_CURSOR; + } else if (catalog->sspp[i].type == SSPP_TYPE_CURSOR) { + /* Cursor SSPP can only be used in the last + * mixer stage, so it doesn't make sense to + * assign two of those to the same CRTC */ + continue; + } else { + type = DRM_PLANE_TYPE_OVERLAY; + } + } else if (primary_planes_idx < max_crtc_count) { type = DRM_PLANE_TYPE_PRIMARY; - else + } else { type = DRM_PLANE_TYPE_OVERLAY; + } DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", type, catalog->sspp[i].features, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 128ecdc145260..5a7bb8543866c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -881,7 +881,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->sspp = NULL; - pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; + if (pipe_hw_caps->type == SSPP_TYPE_CURSOR) { + /* enforce cursor sspp to use the last mixer stage */ + pstate->stage = DPU_STAGE_BASE + + pdpu->catalog->caps->max_mixer_blendstages; + } else { + pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; + } + if (pstate->stage > DPU_STAGE_BASE + pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane mixer stages assigned\n", pdpu->catalog->caps->max_mixer_blendstages); @@ -1463,6 +1470,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); struct dpu_hw_sspp *pipe_hw; + const uint64_t *format_modifiers; uint32_t num_formats; uint32_t supported_rotations; int ret = -EINVAL; @@ -1489,15 +1497,27 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, format_list = pipe_hw->cap->sblk->format_list; num_formats = pipe_hw->cap->sblk->num_formats; + if (pipe_hw->cap->type == SSPP_TYPE_CURSOR) + format_modifiers = NULL; + else + format_modifiers = supported_format_modifiers; + ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, - supported_format_modifiers, type, NULL); + format_modifiers, type, NULL); if (ret) goto clean_plane; pdpu->catalog = kms->catalog; - ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); + if (pipe_hw->cap->type == SSPP_TYPE_CURSOR) { + /* cursor SSPP can only be used in the last mixer stage, + * enforce it by maxing out the cursor plane zpos */ + ret = drm_plane_create_zpos_immutable_property(plane, DPU_ZPOS_MAX); + } else { + ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX - 1); + } + if (ret) DPU_ERROR("failed to install zpos property, rc = %d\n", ret); From patchwork Wed Apr 19 14:41:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37F73C77B7C for ; Wed, 19 Apr 2023 14:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233410AbjDSOma (ORCPT ); Wed, 19 Apr 2023 10:42:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233423AbjDSOmF (ORCPT ); Wed, 19 Apr 2023 10:42:05 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1788C527A for ; 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:59 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:14 +0200 Subject: [PATCH 07/11] drm/msm/dpu: add sspp cursor blocks to msm8998 hw catalog MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-7-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3909; i=avrac@freebox.fr; h=from:subject:message-id; bh=ipqD9/zdMktG6jZ1bu4phPRN971JkBvc1JQ2BoirwDo=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2l9vG3IDNbhr+jhjy4oTIFGSW36RdaDadrV 86j61QWHFOJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9pQAKCRBxA//ZuzQ0 q8FhEACdwf8oEgYArrqf178JDo2Lso4yghQW7d+5aHzqw5icxRDKOQ+2nbEnyR6Y8hk2r0t+Y2F GhWBQpncaZL1tqDzAGnG2O8hxNG+J34LZlqaXdD51p+Ksmmd+Vyvji9TrYhsNdPLjRhLAjUV2gd NfHlUU06QerURwjrCJjiIVOlUzoUyWIMFQIakQtxpYB0LnBPS+WDASAYzT511FThnuf57ayLh9G Vs05zPmzHllDQ7TJpbF/UvoN/8yQh2k/1m+gs5EtDcia0HdcsZoZtLX9JtwA/Piw2hjOZ9eVDvA flcGI3183GRrfyeVKC+7AW9B8ttL6d7ou1c1wZPK4ZauMgvMUlW1PTRESP7UFLbPv0mWIIywgDu DwCd6WW+GsGUpOhCD3HGPRyIYjHTF53x2c6YQa09a/E/kW5CjpKaTjpNnENWTGEac2d0MoGJROT qOXZH75BWv2mNjQYAdoKNlt6vSlZy5+FKSZdfYrNKd5ZxS0rEnZLJCsjXAAJPGO+I/RhlpJ4X2o CK4ZEmPkOp2w8UKmBXGgo+/4UMQkQRfwYqfWvui3dVDFiobcS2PmTikKGXLz863AWN+bMNgRULl i1CsHl8O8INZjKgnDMQjKdAeWZcD8ihSTYqSxiaotCnkgUH5OLA9kHPD/pKRit4yWDNselmFtGk 5n4VAVHk4hbV6Ww== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that cursor sspp blocks can be used for cursor planes, enable them on msm8998. The dma sspp blocks that were assigned to cursor planes can now be used for overlay planes instead. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 34 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index b07e8a9941f79..7de393b0f91d7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -90,10 +90,14 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + SSPP_BLK("sspp_12", SSPP_CURSOR0, 0x34000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + msm8998_cursor_sblk_0, 2, SSPP_TYPE_CURSOR, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_13", SSPP_CURSOR1, 0x36000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + msm8998_cursor_sblk_1, 10, SSPP_TYPE_CURSOR, DPU_CLK_CTRL_CURSOR1), }; static const struct dpu_lm_cfg msm8998_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8d5d782a43398..f34fa704936bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -242,6 +242,22 @@ static const uint32_t wb2_formats[] = { DRM_FORMAT_XBGR4444, }; +static const uint32_t cursor_formats[] = { + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ABGR4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_BGRA4444, +}; + /************************************************************* * SSPP sub blocks config *************************************************************/ @@ -300,6 +316,19 @@ static const uint32_t wb2_formats[] = { .virt_num_formats = ARRAY_SIZE(plane_formats), \ } +#define _CURSOR_SBLK(num) \ + { \ + .maxdwnscale = SSPP_UNITY_SCALE, \ + .maxupscale = SSPP_UNITY_SCALE, \ + .smart_dma_priority = 0, \ + .src_blk = {.name = STRCAT("sspp_src_", num), \ + .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ + .format_list = cursor_formats, \ + .num_formats = ARRAY_SIZE(cursor_formats), \ + .virt_format_list = cursor_formats, \ + .virt_num_formats = ARRAY_SIZE(cursor_formats), \ + } + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = @@ -309,6 +338,11 @@ static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_0 = + _CURSOR_SBLK("12"); +static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_1 = + _CURSOR_SBLK("13"); + static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_maxheight = 1088, .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), From patchwork Wed Apr 19 14:41:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49B75C6FD18 for ; Wed, 19 Apr 2023 14:42:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233529AbjDSOm2 (ORCPT ); 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:59 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:15 +0200 Subject: [PATCH 08/11] drm/msm/dpu: fix cursor block register bit offset in msm8998 hw catalog MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-8-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1184; i=avrac@freebox.fr; h=from:subject:message-id; bh=1CThvjvUKSB2kgPiGI9aOtJO2XMAO12qU/LwO8wOVFQ=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2oUuxrZffTMgc2Prc/9Cgyh4CwUGixDoWFE tdJpMbmdG6JAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9qAAKCRBxA//ZuzQ0 qx3ID/sFH9PfKFzjd9oKmQi89pqSx7jCVGBpbWTrAHuhnQ6bIjfELDfr1V6GQo7xl/ef0gMR/u9 6v8qm4VGQHws43khIcFXvu+NrjE2uwVqhTGYZ2uItNg1fcnkqCKhvoDg/08SDI7ADvpD6ZmCi0j lHVJv9KFGa0AR4039iGE7R0NBQqcEei/HolSkxQxdZDjNbDF+Ls0lcMwcZsTufGLktpr5n/4fHL KFoeqUsi0p2CwfaC5ou4bFnwK3slgkrq9qeHqU+cef0CYqdJPWgPXKuMq57bvS54nm5u6c23mqc MLdkZ7pZ41nh9S/LMHbVg8NfvAQZaBPCFFbHrSrbFnvg9OPfU9st29P6aYmHEYneXaRgPEuWUq+ ind4eFdmm4boScVYenSJJLMctBlN8MckIi/k3SjXanJY5tz/bCkL/pJLhyDhKjxs4PDxx3b4ECw VRWIPmuYaUHhruk9rGgEbysNG6ZuKw3pOBnACN3ZjNSQLMn/VPfPCnoSKjZX/fprenyL5l8vyjg +IofBepTPZW5y2P/SXLQQ4GWUXFM3eoW6+KC35RX/A7ene7ilr9YQiwKDKlYsj/QG9t5NxSgzNk 1THb6wsKAFgBV0cISRJ8F39WFmhTpVvXJXu+AL6NDHRTbDBaV6+cI4h3dBnvO94eOs1bcmDBYRN nAKrWj89r9JRgig== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This matches the value for both fbdev and sde implementations in the downstream msm-4.4 repository. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 7de393b0f91d7..5ae1d41e3fa92 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -39,8 +39,8 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, }, }; From patchwork Wed Apr 19 14:41:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65DF0C77B75 for ; Wed, 19 Apr 2023 14:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233556AbjDSOme (ORCPT ); Wed, 19 Apr 2023 10:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233449AbjDSOmN (ORCPT ); Wed, 19 Apr 2023 10:42:13 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B95174228 for ; Wed, 19 Apr 2023 07:42:01 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id iw7-20020a05600c54c700b003f16fce55b5so1579692wmb.0 for ; Wed, 19 Apr 2023 07:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915320; x=1684507320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=skGYkFK59/ukAv0WKnmVB0D2Vf4WzLOkmRLP20Jah6Y=; b=S/SHCet7T6o1bzniNlVL7gE5UJCdDdK+tx35QCxV16Avx1ks+QhmoPpYR2iSn97x+8 fLji34fU/fXE0o9jI7a/N8JijPFVvqqy33aYjQH6LNCt+o9Vh5M+YN3Y8fwYvncGyt/k CvzAoGf3BF8d8zcZ9hSQalXdd+vEIQdtb5NX4XhU0KoH7+kq4jEmFjjT7DxbQeMPiyoD BhdopBmJJVZx9a8sn6P+g4em3ROBjSNsIpQ8MPCDoxkla+SchV8YnH6VR00JiVfzBL0v qCnngF6JauL//7bl8cIVDhEeqgtCeG2Sa0DG9focJRhG2jVIUOgYXOWQgCMuaC9lTYf4 hHVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915320; x=1684507320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=skGYkFK59/ukAv0WKnmVB0D2Vf4WzLOkmRLP20Jah6Y=; b=dNXqBtwKirTeILpWiORO6N5jWW/Gz8ENMRECgz8z/u/gb52yn50XnrxWDPe0/0Bw42 I1Yz2+EmpTqwyNH4W5BPVpwtPXvdzcgb1sZ5p9csSJ2Tv1JTY1pHiOLkBZeoEpXqJndL Cv7OcXu9sia/rFaamFW+80ZdSgdRMsGVI+UYiOfJh17VLmnbjqfqLvnt0g9ufZak2X/D TzHy2FDqczrXW/va7u8uJFuRtww6xbDWE4Qz3oLZYMlWbhIp9bJu5y11DUkBlLFZQ4T+ YTW6jRfnoImjiwPysUOL/tJIfttcpQTQo6LE9kGNHVbW52zRqb/3els0/5MAw+y1TrW/ p1tQ== X-Gm-Message-State: AAQBX9exy09Y/x/C8tF7AMdvm2JpyZyLGTzYHmkJN5mrrh5X5kVd8i+z 93f4VCZh393YNhp+PoQLcTW/ X-Google-Smtp-Source: AKy350YmaKK3EqTA0/QScooY92hdt3OuAEvnHBAhCJTAnTZTSLhDQXZTU2KFdA8T7mH+W4Fg2s5lLw== X-Received: by 2002:a7b:c8cd:0:b0:3f0:3a57:f01e with SMTP id f13-20020a7bc8cd000000b003f03a57f01emr16543670wml.4.1681915320333; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. 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MSM8998 hw cursor planes support 512x512 size, and other chips use DMA SSPPs. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 6cce0f6cfcb01..2dd19b7aca0f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1014,6 +1014,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms = to_dpu_kms(kms); dev = dpu_kms->dev; + dev->mode_config.cursor_width = 512; + dev->mode_config.cursor_height = 512; + rc = dpu_kms_global_obj_init(dpu_kms); if (rc) return rc; From patchwork Wed Apr 19 14:41:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 713A3C77B7C for ; Wed, 19 Apr 2023 14:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233423AbjDSOmh (ORCPT ); Wed, 19 Apr 2023 10:42:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233459AbjDSOmO (ORCPT ); Wed, 19 Apr 2023 10:42:14 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E4C54498 for ; Wed, 19 Apr 2023 07:42:02 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id v10so10608024wmn.5 for ; Wed, 19 Apr 2023 07:42:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915320; x=1684507320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fy+0cJCJMoy6q1lt77Xw630BaQNJm0bVoX1TCrs3OHc=; b=TzNkV/S3zFklfY2UCSUJJ8GaXQEK01Ig7lF3ptkDh7sr3gmXJ0YtaAtQE06vGXZaHX j/OVRey0YO0AksedTMCLzJTj85LrZ2G/vsgQaYgnFPrsmyitzLq3atec/uX4/Cv+ZPOS Rhu9fJQgcS58K/Wgv/w+GuXnwPuHG5MGJiJgBULg+t1oZWYef74qhBWDQvrXR9xippis lK7t1uqEDmGanbf8ABGrVfSqFgjbHqGfvC5O9R/906X3UYQ6SaEqvjY/JL4XsudvYZ0M qEGUUBcigDPecKfDHIjvy7AsPi9Fq/wAYwQfdsX3mN5WOWkBV4Qi1oxBAKGrMsPHXR96 BUlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915320; x=1684507320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fy+0cJCJMoy6q1lt77Xw630BaQNJm0bVoX1TCrs3OHc=; b=FyfNmcza2FXM1GL/Jd1W6lrmGYrka5ms8lc0BbZT1cGH+FToFWMED/CejQV0oph+73 8REOlB20OYoAZNdbG1102W3cso0WDnVuC8/Z49Vxag6BL0V1h4HM9fMIfxnXe4UvSVY1 rhIVN8QXFVVeghIcqFaF11iE+bKZ+iqIXKYj3eh6B2ot6YpQF3OJj/vcA+kbOs46EIk3 w1xaX7sxjACCaRJwkaiiugFcQe+b9syMQTFgFUD7jnq4/9d9aT1KHHOf24OXbf38qOVR 0mf6DBqOgSXKqU7ge0oVpvp3XnOAau7NSoi0khrMwDRL9yyjOseO+Tnmdt3dcybMazmp dEHA== X-Gm-Message-State: AAQBX9dUlbQjxjmhOeZZ0iZGZSpg8RYz7q7pNCyJclTV/rugagUQ3Kbc Z2lLBBOJeUKp7KodQZ64je65 X-Google-Smtp-Source: AKy350bb1NXI+uElCaT8lhQg1emtnFFKn0pOu68118BMLxyYhN1FaTa9Dxc9OVnIZR5V+JRxT0jpGw== X-Received: by 2002:a05:600c:329a:b0:3f1:7382:b59a with SMTP id t26-20020a05600c329a00b003f17382b59amr2551876wmp.15.1681915320689; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:42:00 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:17 +0200 Subject: [PATCH 10/11] drm/msm/dpu: tweak lm pairings in msm8998 hw catalog MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-10-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1837; i=avrac@freebox.fr; h=from:subject:message-id; bh=RJf9+pkwKnpAj0n2TU3Q6xrSZUQHiMRxoj2hVwg/D2M=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2tJVIeIaiPZf6H3y1PL945iCKPGqC5XoDbK VcSUvP5HoeJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9rQAKCRBxA//ZuzQ0 q3kWEACrjFf+j8o/Ef0fbuwzpaWOroIhsFLQ666cwtToMvHEcF84UQvLMywCIwuYoeuN8TBhQiY g01vQtCeGnPg6/d/ZN10aYjVVxhZuooBA8B2c0sbNDrM2YgjIpJEKrLmqgXlXXT5zQvYHhKb2NS 0hN1Odqd3m+C/oI9yrHWeZXMjE+ollCpLPwYxV56R6P2Dtzu51Vn5HGDzlVPFqvunCUvATTALei i/0BuGL90b7BrYpAhdCewFRtz6lWaV4UHmrpx+51BD9pw8pto1wdz8TTQczi5UWzns75ZRTXx7a LbAjWXCezkAOvfbjYh12wamJ2qde1Ea0WjzyjRZ3sHgPD6Q1SrMoePqs1prrNPxEK+g8DBTTPCj EnyCpixENCuF03h8cc2Tb+WqBxGTAghRF2IrUrq6pOxGZw8IZbLEGZyBH7Xk5BW0kK0k7CjCyzX bz8qW8P4deWATI9s2LCqzep56XCI8pZRtojfWoF4/88cecgiLZgEZfk7wmJSVXYE/DebFuSMIcN 3C5jhV251DaYkRhD7H+TM7/1BlUDDZlB4Yu+hYMTFfZ2RJx2ML4tJBwl6wEqjoirVf2wSreup3Q W1dTG4AqleGljnyPIb6L3EjZLo+PXcCsAuT4EmX2dFzuKc0p8ZayIIHzfyHY40eXrWhu1JedzFd I6VtSRypg1lRpJw== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change lm blocks pairs so that lm blocks with the same features are paired together: LM_0 and LM_1 with PP and DSPP LM_2 and LM_5 with PP LM_3 and LM_4 This matches the sdm845 configuration and allows using pp or dspp when 2 lm blocks are needed in the topology. In the previous config the reservation code could never find an lm pair without a matching feature set. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 5ae1d41e3fa92..90db622eff4fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -102,17 +102,17 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { static const struct dpu_lm_cfg msm8998_lm[] = { LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), + &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0), LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), + &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1), LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), + &msm8998_lm_sblk, PINGPONG_2, LM_5, 0), LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), + &msm8998_lm_sblk, PINGPONG_3, LM_2, 0), }; static const struct dpu_pingpong_cfg msm8998_pp[] = { From patchwork Wed Apr 19 14:41:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165CFC77B73 for ; Wed, 19 Apr 2023 14:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233570AbjDSOmf (ORCPT ); Wed, 19 Apr 2023 10:42:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232763AbjDSOmN (ORCPT ); Wed, 19 Apr 2023 10:42:13 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D25C6A4E for ; Wed, 19 Apr 2023 07:42:02 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id q5so17228436wmo.4 for ; Wed, 19 Apr 2023 07:42:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915321; x=1684507321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TNjgEw1XFUwnMr96e+2CQ6Lo6q2FDtNyKhqD3dmTUrE=; b=4LuBgs9yLJSinqw8HSRzEzngPmX5hzcqhMf7QTeuslRyOioxSoXH7W1tHLPFVxL8Dc LKPzpPKd7dgx+TNyX9PyRaBjvqPW0nmct4PZ7GltxoAb0fWMBgWEgvBl5vVBVuxGQFYv MJ6vDW/SShPCy0/rw1wLYMJiDyk5Hvf5QbaefGOwazZPNGr0ynmOWszW+eNNydmSaXGT xzllUv1g1NPH9oFVmm7w/81fjtbJfJd3lm7gT735eTSwdtHtsdwJmk8Qfra9H4une67D W8BbPPVyYV6YT2A/mFNcFiRECiJ1eO4/AV/hWJYIKltcABnR4VBLce1ghxewvHpjG9cw +iAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915321; x=1684507321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TNjgEw1XFUwnMr96e+2CQ6Lo6q2FDtNyKhqD3dmTUrE=; b=SpgxuHaVlLWWVhODIT1wI4dv0azIBFIpnLzAzydNAgrQpwV1CV2NnqqztWkWxpQrMS q19q0Qz7Vw8JVanGEGZCrBKHIroAHvgTHkvN86JNKiLnMiZHB/Jg6rLly5N7JbvRnlCH MBBBGLDsX73Mp4yqrGNZiy/KlEIT4IsbYEfoQsMrkbkMyGMi0Q+gmcE09nl1eSbgI0VU nCiC9a70rEVWvf9ZbKq50FsLvObclgjw9jI2bLcq1g5IXl1LPxUP/3G8RhHC18U5yspV VLsoBFWu15W4g1MS0gz4a9jmG5f6XG0XcqF4RER+wNfo8oKocxyy4Y/+JGcKIL5VxHKY lrPg== X-Gm-Message-State: AAQBX9eSQxlxoLbvbNluKRpHq01tbs3tjYZ6r/jp9GEIkMV+/h4u39r8 kJblSxBj8gcDaIJTOTlObt0M X-Google-Smtp-Source: AKy350YIZQJc5mHrOF4rjTE+t8DJKPx3mv8uZ6JW80wdo5VzHFNPb+JI8VMqvJYSCsJjOCkMBCPsCA== X-Received: by 2002:a7b:c7d4:0:b0:3ed:418a:ec06 with SMTP id z20-20020a7bc7d4000000b003ed418aec06mr15495212wmk.28.1681915321030; Wed, 19 Apr 2023 07:42:01 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:42:00 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:18 +0200 Subject: [PATCH 11/11] drm/msm/dpu: do not use mixer that supports dspp when not required MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-11-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=774; i=avrac@freebox.fr; h=from:subject:message-id; bh=eCHzSh6ygzKMrynLk5I85+wK8ZD9bT9L4MBgozHvN38=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2wtV1Bh/RNv/ZG/8M0oZScFy8jinYXpQd0Z l2D8Gf954aJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9sAAKCRBxA//ZuzQ0 q1UJD/46OiGy56oZou1FdqKU/7l7QduKNHg/kGvjVQ6ejPCZbi3rN1/KsuGcpsfBDYnC9kEplxb uvdYGoJX7RbyRfP0M3er/R6d7fMOk7+uwCXDmsyGn5VfJ7qpkCgEutRG5O4KWV1oeiMna21h5F+ DxVJuA2pBpUFw7JjL6fGQh1Sng8FWO8Uzcf391FHb3cK0xFZv0KXlAZAx4c6OpodRauIXYXkNd1 Jcu5WViknxy5Ftn5+rJxEstwF7C63jyhlPLrZhjTyKqiCWVfyFXjEWAjGFdr/TkXh5WAEjbhSSt mU7nNxVjPtdxR6ie2B698VBZj3If5GylQw0/7BVI1Lq5qUA8eqzENzlcX+r6s3G0Lliqr3Zzl6F Sb1WxTjhcgQTYWU2Lotuy1lRuydJoEpSDSBpTnF4/agODy2JryUMyueEMDsy45r/1JSHkLKGNWY Pxle7Moqu1T+SjaNR7FQcs0TaLpSNvLGdjSregG/hZjCAWYtx8IIfLuuMKYRUTNLJ8X7jpS3E4t if08fYjYLSdG8uEyrg8/r7C4/A8NbcuuGuppH+nYYs/fnrfZguQQ/b9w9ZqLB08fs+zi0Ofy6Q7 BWH5IzsYUYPdCf1/YN9bRJVoomXeRs5JSezRgMaF+ItDKS+kvI7o55nypbz0Ktlkt/IdxqkEhso yRJYDH3EDrznDuw== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This avoids using lm blocks that support DSPP when not needed, to keep those resources available. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f4dda88a73f7d..4b393d46c743f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -362,7 +362,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, *pp_idx = idx; if (!reqs->topology.num_dspp) - return true; + return !lm_cfg->dspp; idx = lm_cfg->dspp - DSPP_0; if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {