From patchwork Sun Apr 23 12:12:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13221289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93044C77B76 for ; Sun, 23 Apr 2023 12:13:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F292610E3A7; Sun, 23 Apr 2023 12:12:59 +0000 (UTC) Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by gabe.freedesktop.org (Postfix) with ESMTPS id ABF7D10E30B for ; Sun, 23 Apr 2023 12:12:55 +0000 (UTC) Received: by mail-io1-xd32.google.com with SMTP id ca18e2360f4ac-7606ce9bfdeso333910139f.0 for ; Sun, 23 Apr 2023 05:12:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682251974; x=1684843974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JTAw7F03HuAr0OI8IRjYA7Odta6kZ/yszj+u/BSAuPo=; b=REgwWBSRFUiIEK9qwudRmoDNqt33mzgWRpmSeTuO2i/B46etyi8vK2RjYE9C13aKph ZyKhanQ0+t1Z8fBqUULDvdIolx+0Fxu8moCOZsKPN5GgUj5g1viY7TQiMiwUA5v1Shwr 5tfFcNnPlsA+19dAYi5OAxfGbC53Oedw2SC09NpWcmDpQ4Vste76HhxFcxE9QVh4xNcp xl26AtEqF+gEmpzevyNYf2RE5yEx3g9g1RdErKJbwGG4tw86WWFFHyZfzm0wpdw0HhTS Otc5B5oJZ0pHrEVL7mOkHAVWvPhV4zL+UvE96ikTJo92Wnjw1sR3QGnl63CHt1w0M0DF TlXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682251974; x=1684843974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JTAw7F03HuAr0OI8IRjYA7Odta6kZ/yszj+u/BSAuPo=; b=Rli4i4U6xp2KWUdrN3ixKBQK1UxEuqW0aWgUrUSaZfRV9F3eLPjjMwRKjc1Fi5/Kdq 9+DZQAxKiA/8M1j/IiWx+6k8V7OHkn5T7cP3l1QlCSLfaIxygZ0f3cWYEIBm/HeM5Q/y gd6mfPsZQhsVPB1owmHbX1Wujqb2kHjZoMLwjvJ/G+j7IO1hMWlrquZfIs5JNskqVnpS U5DoVH7Rvw5DvSIxPVKdbh8m1LUjHRX0OVYNPz2jjjXtY8EAtmMi4t6jnXlo0YGbuEkg a81Wro63Dr1F68dHu2r0mRvrmIUsiOdj0cEOdTveetpkt2osjT4n1PJhbDJKq3VHya0A 6+6w== X-Gm-Message-State: AAQBX9cDLV6k4ygXATq5Zo0SNFAK8rxY/DqZhl7SRzGaZAnbxQFFWtnA YweJ5/ZnagMMRdNxERaKiT8gOwIXMpM= X-Google-Smtp-Source: AKy350b4IsmOmc2kdOlEa4VZcUd9HynWDxOz89lLecHxdvuNlqnpR4ecObEj/S+7bd3uBqX33WJ1vw== X-Received: by 2002:a6b:7617:0:b0:74d:771:6ed5 with SMTP id g23-20020a6b7617000000b0074d07716ed5mr3107823iom.21.1682251974106; Sun, 23 Apr 2023 05:12:54 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:b473:5d7c:4c2:75d7]) by smtp.gmail.com with ESMTPSA id u11-20020a02230b000000b00411a1373aa5sm1612155jau.155.2023.04.23.05.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 05:12:53 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V2 1/6] drm: bridge: samsung-dsim: fix blanking packet size calculation Date: Sun, 23 Apr 2023 07:12:27 -0500 Message-Id: <20230423121232.1345909-2-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423121232.1345909-1-aford173@gmail.com> References: <20230423121232.1345909-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Robert Foss , Jonas Karlman , Laurent Pinchart , aford@beaconembedded.com, Jernej Skrabec , Frieder Schrempf , Jagan Teki , Andrzej Hajda , m.szyprowski@samsung.com, dario.binacchi@amarulasolutions.com, Adam Ford , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Lucas Stach Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0a402a85787..2be3b58624c3 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8; + int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; + int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; + int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + + /* remove packet overhead when possible */ + hfp = max(hfp - 6, 0); + hbp = max(hbp - 6, 0); + hsa = max(hsa - 6, 0); + + dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", + hfp, hbp, hsa); + reg = DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); - reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA(hsa); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | From patchwork Sun Apr 23 12:12:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13221290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3BC3C77B76 for ; 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Sun, 23 Apr 2023 05:12:55 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V2 2/6] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Date: Sun, 23 Apr 2023 07:12:28 -0500 Message-Id: <20230423121232.1345909-3-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423121232.1345909-1-aford173@gmail.com> References: <20230423121232.1345909-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Robert Foss , Jonas Karlman , Laurent Pinchart , aford@beaconembedded.com, Jernej Skrabec , linux-kernel@vger.kernel.org, Jagan Teki , Andrzej Hajda , m.szyprowski@samsung.com, dario.binacchi@amarulasolutions.com, Adam Ford Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support") Signed-off-by: Adam Ford Reviewed-by: Lucas Stach --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 2be3b58624c3..adb9c13c5f7f 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -405,6 +405,9 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .m_min = 41, + .m_max = 125, + .vco_min = 500, }; static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { @@ -418,6 +421,9 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .m_min = 41, + .m_max = 125, + .vco_min = 500, }; static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { @@ -429,6 +435,9 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .m_min = 41, + .m_max = 125, + .vco_min = 500, }; static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { @@ -441,6 +450,9 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { .num_bits_resol = 12, .pll_p_offset = 13, .reg_values = exynos5433_reg_values, + .m_min = 41, + .m_max = 125, + .vco_min = 500, }; static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { @@ -453,6 +465,9 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .num_bits_resol = 12, .pll_p_offset = 13, .reg_values = exynos5422_reg_values, + .m_min = 41, + .m_max = 125, + .vco_min = 500, }; static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { @@ -469,6 +484,9 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { */ .pll_p_offset = 14, .reg_values = imx8mm_dsim_reg_values, + .m_min = 64, + .m_max = 1023, + .vco_min = 1050, }; static const struct samsung_dsim_driver_data * @@ -547,12 +565,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, tmp = (u64)fout * (_p << _s); do_div(tmp, fin); _m = tmp; - if (_m < 41 || _m > 125) + if (_m < driver_data->m_min || _m > driver_data->m_max) continue; tmp = (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < driver_data->vco_min * MHZ || tmp > driver_data->max_freq * MHZ) continue; diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index ba5484de2b30..a088d84579bc 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -59,6 +59,9 @@ struct samsung_dsim_driver_data { unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + u16 m_min; + u16 m_max; + u64 vco_min; }; struct samsung_dsim_host_ops { From patchwork Sun Apr 23 12:12:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13221291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DD9DC77B73 for ; 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Sun, 23 Apr 2023 05:12:56 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V2 3/6] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically Date: Sun, 23 Apr 2023 07:12:29 -0500 Message-Id: <20230423121232.1345909-4-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423121232.1345909-1-aford173@gmail.com> References: <20230423121232.1345909-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Robert Foss , Jonas Karlman , Laurent Pinchart , aford@beaconembedded.com, Jernej Skrabec , linux-kernel@vger.kernel.org, Jagan Teki , Andrzej Hajda , m.szyprowski@samsung.com, dario.binacchi@amarulasolutions.com, Adam Ford Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Signed-off-by: Adam Ford --- drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index adb9c13c5f7f..5b6e7825b92f 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1726,12 +1726,20 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) { struct device *dev = dsi->dev; struct device_node *node = dev->of_node; + struct clk *pll_clk; int ret; ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate); - if (ret < 0) - return ret; + + /* If it doesn't exist, read it from the clock instead of failing */ + if (ret < 0) { + pll_clk = devm_clk_get(dev, "sclk_mipi"); + if (!IS_ERR(pll_clk)) + dsi->pll_clk_rate = clk_get_rate(pll_clk); + else + return PTR_ERR(pll_clk); + } ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", &dsi->burst_clk_rate); From patchwork Sun Apr 23 12:12:30 2023 Content-Type: text/plain; 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Sun, 23 Apr 2023 05:12:58 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:b473:5d7c:4c2:75d7]) by smtp.gmail.com with ESMTPSA id u11-20020a02230b000000b00411a1373aa5sm1612155jau.155.2023.04.23.05.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 05:12:58 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V2 4/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Date: Sun, 23 Apr 2023 07:12:30 -0500 Message-Id: <20230423121232.1345909-5-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423121232.1345909-1-aford173@gmail.com> References: <20230423121232.1345909-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Robert Foss , Jonas Karlman , Laurent Pinchart , aford@beaconembedded.com, Jernej Skrabec , linux-kernel@vger.kernel.org, Jagan Teki , Andrzej Hajda , m.szyprowski@samsung.com, dario.binacchi@amarulasolutions.com, Adam Ford Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. Add an additional variable to the driver data to enable this feature to prevent breaking boards that don't support it. The phy_mipi_dphy_get_default_config function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the pixel clock rate. Signed-off-by: Adam Ford --- drivers/gpu/drm/bridge/samsung-dsim.c | 79 +++++++++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 5b6e7825b92f..f165483d5044 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -18,9 +18,7 @@ #include #include #include - #include