From patchwork Thu Jan 31 16:15:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790871 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FBC613B4 for ; Thu, 31 Jan 2019 16:15:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A1223133D for ; Thu, 31 Jan 2019 16:15:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D5F03134C; Thu, 31 Jan 2019 16:15:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F7CF3133D for ; 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bh=ebZoX02BIUVl/c7RPJ/TiAnts4tU9d7VKoLF6wM4x2Q=; b=KZu92Hi1MgMl+8MDZ+BBjbg9PhK7FTWBbARnkHcKwsq4ZrC0ImSy5S/n9E69IuR7Z9OH0g57RQcOVP5GDGvsZzbAVvVp9NtDiXcQCpL1X0TAB755lwheN4BJ/FOB1O0G4E17k167tS8WgfvxNsXnii4NWtAuSeodmBpC/v0B91o= Received: from BN6PR11MB1842.namprd11.prod.outlook.com (10.175.98.146) by BN6PR11MB1874.namprd11.prod.outlook.com (10.175.101.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1580.17; Thu, 31 Jan 2019 16:15:29 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Thu, 31 Jan 2019 16:15:29 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 01/10] spi: atmel-quadspi: cache MR value to avoid a write access Thread-Topic: [PATCH v2 01/10] spi: atmel-quadspi: cache MR value to avoid a write access Thread-Index: AQHUuYAu+viSD5s94E+u9UEZBRyorg== Date: Thu, 31 Jan 2019 16:15:28 +0000 Message-ID: <20190131161515.21605-2-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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SMM is set in exec_op() and not at probe time, to let room for future regular SPI support. Signed-off-by: Tudor Ambarus --- v2: cache MR value instead of moving the write access at probe drivers/spi/atmel-quadspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index ddc712410812..fe05aee5d845 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -155,6 +155,7 @@ struct atmel_qspi { struct clk *clk; struct platform_device *pdev; u32 pending; + u32 mr; struct completion cmd_completion; }; @@ -238,7 +239,9 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) icr = QSPI_ICR_INST(op->cmd.opcode); ifr = QSPI_IFR_INSTEN; - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); + /* Set the QSPI controller in Serial Memory Mode */ + if (!(aq->mr & QSPI_MR_SMM)) + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); mode = find_mode(op); if (mode < 0) From patchwork Thu Jan 31 16:15:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790893 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77CFA13B4 for ; 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Thu, 31 Jan 2019 16:15:31 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Thu, 31 Jan 2019 16:15:31 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 02/10] spi: atmel-quadspi: order header files inclusion alphabetically Thread-Topic: [PATCH v2 02/10] spi: atmel-quadspi: order header files inclusion alphabetically Thread-Index: AQHUuYAw8ZDPknGqbUSbsvPqrU2nUg== Date: Thu, 31 Jan 2019 16:15:31 +0000 Message-ID: <20190131161515.21605-3-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon --- v2: collect R-b drivers/spi/atmel-quadspi.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index fe05aee5d845..c986daa895a1 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -22,16 +22,15 @@ * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. */ -#include #include -#include -#include #include #include #include -#include - #include +#include +#include +#include +#include #include /* QSPI register offsets */ From patchwork Thu Jan 31 16:15:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCF6E13B4 for ; Thu, 31 Jan 2019 16:16:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BFAE131354 for ; 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Thu, 31 Jan 2019 16:15:33 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 03/10] spi: atmel-quadspi: drop wrappers for iomem accesses Thread-Topic: [PATCH v2 03/10] spi: atmel-quadspi: drop wrappers for iomem accesses Thread-Index: AQHUuYAx9b//q0v6hUW7FfCSTVlftQ== Date: Thu, 31 Jan 2019 16:15:33 +0000 Message-ID: <20190131161515.21605-4-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;BN6PR11MB0004;6:Xi5KOmEPRYP2JHAaoM3UXQRYTM4/MIZHV4OzjmhEsNpWzVNQBMcTW4lZAiDuaZrWln1/WEC2NiedJcZKrXnh5H4i3kuAxwafXF3ID+WDz47KbIg6faASbpkh58jwrZN+Es7DENhHrwK31QD/8E147Ssdq/FX8+1cl3eyK+sC9jxPFOhZQ6t8OY95YyFK2GdZvHcRK464BLnQM1CxPegWTzXySmd04B2vi5cO1ZmSAbG7w/DFmUIokOLQvR4EJNRjKrt/Idfby6p1sSHtqzHaOoeYHosRY4x1Oacc6HK8oceS7q7eFPSfYqVRoUltpHM5c/+eNzy9N0qNornL7hU7kPApWdzGi0IxLFKOQN57Vao6TCmE6gCUbKtZDpb+w9JtcJndqwXNKseOKpWcRRMn0cDBYtTLCehtR6BbfbZOa0eLulMvUcQvyJyrX8YYD3viXnLNrCEgAshuUC8zGj3vTw==;5:NwYdzYsvRjyXpOjkRq+8sHCqFdQlwkZcxRYaOlmCRsUaU/jHoQ1TrJ/v8QBD9yl1kUwQ1YbO8SNLu0BJmWWhqYCBbyzPQW2PzpeYoF0UKh3E67CZHnQURQr7rGDomR6hcB394bz1Lv5XAO8prdfjsYGkdu+XiDDfg/+QVlzKMteRGRwCqdn61DJ/qlfivDxWN6hSg3m+on6efntmp9MEXg==;7:hxG85/W6NjrSiZY7DyL/9AJk7pxlNO7DwZ4ivY/gF3KT5EBy66rIRQ6nO4nq3gO+9rzMEXtOErnaD7r33y9t8AXowQ9Z2abvNyuuwN7XJewjy4fEHBJQGcPSyWeTFdgQOWzofb92l+sgRZBfC4sSyA== x-ms-office365-filtering-correlation-id: 0f5a08fd-b883-4e9c-6958-08d6879753ce x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600110)(711020)(4605077)(2017052603328)(7153060)(7193020);SRVR:BN6PR11MB0004; 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Drop them. Signed-off-by: Tudor Ambarus --- v2: new patch drivers/spi/atmel-quadspi.c | 47 +++++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index c986daa895a1..3a7648ea07e8 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -175,17 +175,6 @@ static const struct qspi_mode sama5d2_qspi_modes[] = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, }; -/* Register access functions */ -static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg) -{ - return readl_relaxed(aq->regs + reg); -} - -static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value) -{ - writel_relaxed(value, aq->regs + reg); -} - static inline bool is_compatible(const struct spi_mem_op *op, const struct qspi_mode *mode) { @@ -229,6 +218,7 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem, static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); + void __iomem *base = aq->regs; int mode; u32 dummy_cycles = 0; u32 iar, icr, ifr, sr; @@ -240,7 +230,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) /* Set the QSPI controller in Serial Memory Mode */ if (!(aq->mr & QSPI_MR_SMM)) - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); + writel_relaxed(QSPI_MR_SMM, base + QSPI_MR); mode = find_mode(op); if (mode < 0) @@ -298,17 +288,17 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; /* Clear pending interrupts */ - (void)qspi_readl(aq, QSPI_SR); + (void)readl_relaxed(base + QSPI_SR); /* Set QSPI Instruction Frame registers */ - qspi_writel(aq, QSPI_IAR, iar); - qspi_writel(aq, QSPI_ICR, icr); - qspi_writel(aq, QSPI_IFR, ifr); + writel_relaxed(iar, base + QSPI_IAR); + writel_relaxed(icr, base + QSPI_ICR); + writel_relaxed(ifr, base + QSPI_IFR); /* Skip to the final steps if there is no data */ if (op->data.nbytes) { /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ - (void)qspi_readl(aq, QSPI_IFR); + (void)readl_relaxed(base + QSPI_IFR); /* Send/Receive data */ if (op->data.dir == SPI_MEM_DATA_IN) @@ -319,22 +309,22 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) op->data.buf.out, op->data.nbytes); /* Release the chip-select */ - qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); + writel_relaxed(QSPI_CR_LASTXFER, base + QSPI_CR); } /* Poll INSTRuction End status */ - sr = qspi_readl(aq, QSPI_SR); + sr = readl_relaxed(base + QSPI_SR); if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) return err; /* Wait for INSTRuction End interrupt */ reinit_completion(&aq->cmd_completion); aq->pending = sr & QSPI_SR_CMD_COMPLETED; - qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED); + writel_relaxed(QSPI_SR_CMD_COMPLETED, base + QSPI_IER); if (!wait_for_completion_timeout(&aq->cmd_completion, msecs_to_jiffies(1000))) err = -ETIMEDOUT; - qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED); + writel_relaxed(QSPI_SR_CMD_COMPLETED, base + QSPI_IDR); return err; } @@ -373,18 +363,20 @@ static int atmel_qspi_setup(struct spi_device *spi) scbr--; scr = QSPI_SCR_SCBR(scbr); - qspi_writel(aq, QSPI_SCR, scr); + writel_relaxed(scr, aq->regs + QSPI_SCR); return 0; } static int atmel_qspi_init(struct atmel_qspi *aq) { + void __iomem *base = aq->regs; + /* Reset the QSPI controller */ - qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); + writel_relaxed(QSPI_CR_SWRST, base + QSPI_CR); /* Enable the QSPI controller */ - qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); + writel_relaxed(QSPI_CR_QSPIEN, base + QSPI_CR); return 0; } @@ -392,10 +384,11 @@ static int atmel_qspi_init(struct atmel_qspi *aq) static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) { struct atmel_qspi *aq = (struct atmel_qspi *)dev_id; + void __iomem *base = aq->regs; u32 status, mask, pending; - status = qspi_readl(aq, QSPI_SR); - mask = qspi_readl(aq, QSPI_IMR); + status = readl_relaxed(base + QSPI_SR); + mask = readl_relaxed(base + QSPI_IMR); pending = status & mask; if (!pending) @@ -501,7 +494,7 @@ static int atmel_qspi_remove(struct platform_device *pdev) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); spi_unregister_controller(ctrl); - qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS); + writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR); clk_disable_unprepare(aq->clk); return 0; } From patchwork Thu Jan 31 16:15:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790889 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E113C746 for ; Thu, 31 Jan 2019 16:16:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D52FB31354 for ; Thu, 31 Jan 2019 16:16:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C90E631358; Thu, 31 Jan 2019 16:16:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 58E1231354 for ; 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Signed-off-by: Tudor Ambarus --- v2: update after the removing of iomem access wrappers drivers/spi/atmel-quadspi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 3a7648ea07e8..4105ded68f44 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -158,14 +158,14 @@ struct atmel_qspi { struct completion cmd_completion; }; -struct qspi_mode { +struct atmel_qspi_mode { u8 cmd_buswidth; u8 addr_buswidth; u8 data_buswidth; u32 config; }; -static const struct qspi_mode sama5d2_qspi_modes[] = { +static const struct atmel_qspi_mode sama5d2_qspi_modes[] = { { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, @@ -175,8 +175,8 @@ static const struct qspi_mode sama5d2_qspi_modes[] = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, }; -static inline bool is_compatible(const struct spi_mem_op *op, - const struct qspi_mode *mode) +static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, + const struct atmel_qspi_mode *mode) { if (op->cmd.buswidth != mode->cmd_buswidth) return false; @@ -190,12 +190,12 @@ static inline bool is_compatible(const struct spi_mem_op *op, return true; } -static int find_mode(const struct spi_mem_op *op) +static int atmel_qspi_find_mode(const struct spi_mem_op *op) { u32 i; for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++) - if (is_compatible(op, &sama5d2_qspi_modes[i])) + if (atmel_qspi_is_compatible(op, &sama5d2_qspi_modes[i])) return i; return -1; @@ -204,7 +204,7 @@ static int find_mode(const struct spi_mem_op *op) static bool atmel_qspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (find_mode(op) < 0) + if (atmel_qspi_find_mode(op) < 0) return false; /* special case not supported by hardware */ @@ -232,7 +232,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (!(aq->mr & QSPI_MR_SMM)) writel_relaxed(QSPI_MR_SMM, base + QSPI_MR); - mode = find_mode(op); + mode = atmel_qspi_find_mode(op); if (mode < 0) return -ENOTSUPP; From patchwork Thu Jan 31 16:15:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790887 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 149B1746 for ; Thu, 31 Jan 2019 16:16:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0971431354 for ; Thu, 31 Jan 2019 16:16:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F209031358; Thu, 31 Jan 2019 16:16:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90E1D31354 for ; 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Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon --- v2: collect R-b drivers/spi/atmel-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 4105ded68f44..2db935488270 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -383,7 +383,7 @@ static int atmel_qspi_init(struct atmel_qspi *aq) static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) { - struct atmel_qspi *aq = (struct atmel_qspi *)dev_id; + struct atmel_qspi *aq = dev_id; void __iomem *base = aq->regs; u32 status, mask, pending; From patchwork Thu Jan 31 16:15:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790881 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8E786746 for ; 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Propagate the error in atmel_qspi_exec_op(). Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon --- v2: collect R-b drivers/spi/atmel-quadspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 2db935488270..1f7cf5d2953a 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -198,7 +198,7 @@ static int atmel_qspi_find_mode(const struct spi_mem_op *op) if (atmel_qspi_is_compatible(op, &sama5d2_qspi_modes[i])) return i; - return -1; + return -ENOTSUPP; } static bool atmel_qspi_supports_op(struct spi_mem *mem, @@ -234,7 +234,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) mode = atmel_qspi_find_mode(op); if (mode < 0) - return -ENOTSUPP; + return mode; ifr |= sama5d2_qspi_modes[mode].config; From patchwork Thu Jan 31 16:15:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790883 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C98F184E for ; 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Thu, 31 Jan 2019 16:15:44 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Thu, 31 Jan 2019 16:15:44 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 07/10] spi: atmel-quadspi: switch to SPDX license identifiers Thread-Topic: [PATCH v2 07/10] spi: atmel-quadspi: switch to SPDX license identifiers Thread-Index: AQHUuYA3//fOXr8GpkeybxtYbePJ3g== Date: Thu, 31 Jan 2019 16:15:43 +0000 Message-ID: <20190131161515.21605-8-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon --- v2: collect R-b drivers/spi/atmel-quadspi.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 1f7cf5d2953a..d3e76acf8517 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Driver for Atmel QSPI Controller * @@ -7,18 +8,6 @@ * Author: Cyrille Pitchen * Author: Piotr Bugalski * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - * * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. */ From patchwork Thu Jan 31 16:15:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B3B313B4 for ; Thu, 31 Jan 2019 16:16:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 301EC3134E for ; Thu, 31 Jan 2019 16:16:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21A2531357; Thu, 31 Jan 2019 16:16:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B464F3134E for ; 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bh=pYISt+mUq8a2y/52ynnDii37D8+VlIQlpqZskupf4Es=; b=Ff6jWJyuRg4VjWUPX7arYnKPGY4P8H7H1PrWpIqR90BvFKqlssNSZ2tFdP205p/lUQgzR2k8X4OVaNCu82Cn/cE8uEX79thMF3F5YX2Gof5Md0iVTUKMgHGLytmkgaYy/qnON02zt1HKC1Zf9ibte60FivonNoZC9jL1okEIOqQ= Received: from BN6PR11MB1842.namprd11.prod.outlook.com (10.175.98.146) by BN6PR11MB1315.namprd11.prod.outlook.com (10.173.32.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1580.16; Thu, 31 Jan 2019 16:15:46 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Thu, 31 Jan 2019 16:15:46 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 08/10] dt-bindings: spi: atmel-quadspi: update example to new clock binding Thread-Topic: [PATCH v2 08/10] dt-bindings: spi: atmel-quadspi: update example to new clock binding Thread-Index: AQHUuYA4pheU0uoMGEKsRDfKD/gBUQ== Date: Thu, 31 Jan 2019 16:15:46 +0000 Message-ID: <20190131161515.21605-9-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; From patchwork Thu Jan 31 16:15:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10790875 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50DBF746 for ; Thu, 31 Jan 2019 16:15:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 435F33134E for ; Thu, 31 Jan 2019 16:15:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3710D31354; Thu, 31 Jan 2019 16:15:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBF803134E for ; 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bh=aHTEbk25x9Flb/D9oAqFzjCnfnPfDNCVNyoxiVHJRFY=; b=kmjXea1iXNcDPQhH3r1wIthJbWPZqUf5y5r6vzaoFRuY0z2CY6vC+L3Xar9LZorhJ3R9nAvr/I+U3q0AoxZObvGdAPb6VRxi7xAsnlbLauvnyPRW107jDclXKoJHMfIR2K4Z0mAR/C5wTAhwUMvwLpT+JM8drdWok46I2KURK8k= Received: from BN6PR11MB1842.namprd11.prod.outlook.com (10.175.98.146) by BN6PR11MB1315.namprd11.prod.outlook.com (10.173.32.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1580.16; Thu, 31 Jan 2019 16:15:49 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Thu, 31 Jan 2019 16:15:48 +0000 From: To: , , , , , , CC: , , , , , Subject: [PATCH v2 09/10] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Thread-Topic: [PATCH v2 09/10] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Thread-Index: AQHUuYA6/sbMtxDVkEiSqq8xQrDUkg== Date: Thu, 31 Jan 2019 16:15:48 +0000 Message-ID: <20190131161515.21605-10-tudor.ambarus@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> In-Reply-To: <20190131161515.21605-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR02CA0046.eurprd02.prod.outlook.com (2603:10a6:802:14::17) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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Both are mandatory. Signed-off-by: Tudor Ambarus --- v2: - make "pclk" mandatory even for sama5d2. Unnamed clk will be supported in the driver. - drop unneeded example Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt index e9dae6264d89..f949f9197636 100644 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -1,14 +1,22 @@ * Atmel Quad Serial Peripheral Interface (QSPI) Required properties: -- compatible: Should be "atmel,sama5d2-qspi". +- compatible: Should be one of the following: + - "atmel,sama5d2-qspi" + - "microchip,sam9x60-qspi" - reg: Should contain the locations and lengths of the base registers and the mapped memory. - reg-names: Should contain the resource reg names: - qspi_base: configuration register address space - qspi_mmap: memory mapped address space - interrupts: Should contain the interrupt for the device. -- clocks: The phandle of the clock needed by the QSPI controller. +- clocks: - "atmel,sama5d2-qspi": the phandle of the clock needed by the + QSPI controller. + - "microchip,sam9x60-qspi": should reference the peripheral + and system QSPI clocks. +- clock-names: Should contain: + - "pclk" for the peripheral clock + - "qspick" for the system clock, when available (sam9x60) - #address-cells: Should be <1>. - #size-cells: Should be <0>. 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Both are mandatory. It uses dedicated register for Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus --- v2: - rework clock handling - reorder setting of register values in set_cfg() calls -> move functions that can fail in the upper part of the function body. drivers/spi/atmel-quadspi.c | 296 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 239 insertions(+), 57 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index d3e76acf8517..80c934f3e479 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -35,7 +36,9 @@ #define QSPI_IAR 0x0030 /* Instruction Address Register */ #define QSPI_ICR 0x0034 /* Instruction Code Register */ +#define QSPI_WICR 0x0034 /* Write Instruction Code Register */ #define QSPI_IFR 0x0038 /* Instruction Frame Register */ +#define QSPI_RICR 0x003C /* Read Instruction Code Register */ #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ #define QSPI_SKR 0x0044 /* Scrambling Key Register */ @@ -88,7 +91,7 @@ #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) -/* Bitfields in QSPI_ICR (Instruction Code Register) */ +/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ #define QSPI_ICR_INST_MASK GENMASK(7, 0) #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) #define QSPI_ICR_OPT_MASK GENMASK(23, 16) @@ -113,6 +116,8 @@ #define QSPI_IFR_OPTL_4BIT (2 << 8) #define QSPI_IFR_OPTL_8BIT (3 << 8) #define QSPI_IFR_ADDRL BIT(10) +#define QSPI_IFR_TFRTYP_TRSFR_MEM BIT(12) +#define QSPI_IFR_TFRTYP_TRSFR_REG (0 << 12) #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) @@ -121,6 +126,8 @@ #define QSPI_IFR_CRM BIT(14) #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) +#define QSPI_IFR_APBTFRTYP_WRITE (0 << 24) +#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ #define QSPI_SMR_SCREN BIT(0) @@ -137,16 +144,37 @@ #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) +/* Describes register values. */ +struct atmel_qspi_cfg { + u32 icr; + u32 iar; + u32 ifr; +}; + +struct atmel_qspi_caps; + struct atmel_qspi { void __iomem *regs; void __iomem *mem; struct clk *clk; + struct clk *qspick; struct platform_device *pdev; + const struct atmel_qspi_caps *caps; u32 pending; u32 mr; struct completion cmd_completion; }; +struct atmel_qspi_ops { + int (*set_qspi_cfg)(void __iomem *regs, const struct spi_mem_op *op, + struct atmel_qspi_cfg *cfg); +}; + +struct atmel_qspi_caps { + const struct atmel_qspi_ops *ops; + bool has_qspick; +}; + struct atmel_qspi_mode { u8 cmd_buswidth; u8 addr_buswidth; @@ -204,28 +232,36 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem, return true; } -static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +static int atmel_qspi_set_mode(struct atmel_qspi_cfg *cfg, + const struct spi_mem_op *op) { - struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); - void __iomem *base = aq->regs; - int mode; - u32 dummy_cycles = 0; - u32 iar, icr, ifr, sr; - int err = 0; + int mode = atmel_qspi_find_mode(op); - iar = 0; - icr = QSPI_ICR_INST(op->cmd.opcode); - ifr = QSPI_IFR_INSTEN; - - /* Set the QSPI controller in Serial Memory Mode */ - if (!(aq->mr & QSPI_MR_SMM)) - writel_relaxed(QSPI_MR_SMM, base + QSPI_MR); - - mode = atmel_qspi_find_mode(op); if (mode < 0) return mode; + cfg->ifr = sama5d2_qspi_modes[mode].config; + return 0; +} - ifr |= sama5d2_qspi_modes[mode].config; +/* + * atmel_qspi_set_address_mode() - set address mode. + * @cfg: contains register values + * @op: describes a SPI memory operation + * + * The controller allows 24 and 32-bit addressing while NAND-flash requires + * 16-bit long. Handling 8-bit long addresses is done using the option field. + * For the 16-bit addresses, the workaround depends of the number of requested + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and + * sent with the first dummy byte. Otherwise opcode is disabled and the first + * byte of the address contains the command opcode (works only if the opcode and + * address use the same buswidth). The limitation is when the 16-bit address is + * used without enough dummy cycles and the opcode is using a different buswidth + * than the address. + */ +static int atmel_qspi_set_address_mode(struct atmel_qspi_cfg *cfg, + const struct spi_mem_op *op) +{ + u32 dummy_cycles = 0; if (op->dummy.buswidth && op->dummy.nbytes) dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; @@ -235,28 +271,28 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) case 0: break; case 1: - ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; - icr |= QSPI_ICR_OPT(op->addr.val & 0xff); + cfg->ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; + cfg->icr = QSPI_ICR_OPT(op->addr.val & 0xff); break; case 2: if (dummy_cycles < 8 / op->addr.buswidth) { - ifr &= ~QSPI_IFR_INSTEN; - ifr |= QSPI_IFR_ADDREN; - iar = (op->cmd.opcode << 16) | - (op->addr.val & 0xffff); + cfg->ifr &= ~QSPI_IFR_INSTEN; + cfg->ifr |= QSPI_IFR_ADDREN; + cfg->iar = (op->cmd.opcode << 16) | + (op->addr.val & 0xffff); } else { - ifr |= QSPI_IFR_ADDREN; - iar = (op->addr.val << 8) & 0xffffff; + cfg->ifr |= QSPI_IFR_ADDREN; + cfg->iar = (op->addr.val << 8) & 0xffffff; dummy_cycles -= 8 / op->addr.buswidth; } break; case 3: - ifr |= QSPI_IFR_ADDREN; - iar = op->addr.val & 0xffffff; + cfg->ifr |= QSPI_IFR_ADDREN; + cfg->iar = op->addr.val & 0xffffff; break; case 4: - ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; - iar = op->addr.val & 0x7ffffff; + cfg->ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; + cfg->iar = op->addr.val & 0x7ffffff; break; default: return -ENOTSUPP; @@ -265,24 +301,106 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) /* Set number of dummy cycles */ if (dummy_cycles) - ifr |= QSPI_IFR_NBDUM(dummy_cycles); + cfg->ifr |= QSPI_IFR_NBDUM(dummy_cycles); + + return 0; +} + +static int atmel_sama5d2_qspi_set_cfg(void __iomem *base, + const struct spi_mem_op *op, + struct atmel_qspi_cfg *cfg) +{ + int ret = atmel_qspi_set_mode(cfg, op); + + if (ret) + return ret; + + ret = atmel_qspi_set_address_mode(cfg, op); + if (ret) + return ret; + + cfg->ifr |= QSPI_IFR_INSTEN; + cfg->icr |= QSPI_ICR_INST(op->cmd.opcode); /* Set data enable */ if (op->data.nbytes) - ifr |= QSPI_IFR_DATAEN; + cfg->ifr |= QSPI_IFR_DATAEN; if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) - ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; else - ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; + + /* Clear pending interrupts */ + (void)readl_relaxed(base + QSPI_SR); + + /* Set QSPI Instruction Frame registers */ + writel_relaxed(cfg->iar, base + QSPI_IAR); + writel_relaxed(cfg->icr, base + QSPI_ICR); + writel_relaxed(cfg->ifr, base + QSPI_IFR); + + return 0; +} + +static int atmel_sam9x60_qspi_set_cfg(void __iomem *base, + const struct spi_mem_op *op, + struct atmel_qspi_cfg *cfg) +{ + int ret = atmel_qspi_set_mode(cfg, op); + + if (ret) + return ret; + + ret = atmel_qspi_set_address_mode(cfg, op); + if (ret) + return ret; + + cfg->ifr |= QSPI_IFR_INSTEN; + cfg->icr |= QSPI_ICR_INST(op->cmd.opcode); + + /* Set data enable */ + if (op->data.nbytes) + cfg->ifr |= QSPI_IFR_DATAEN; + + if (!op->addr.nbytes) { + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_REG; + if (op->data.dir == SPI_MEM_DATA_OUT) + cfg->ifr |= QSPI_IFR_APBTFRTYP_WRITE; + else + cfg->ifr |= QSPI_IFR_APBTFRTYP_READ; + } else { + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_MEM; + } /* Clear pending interrupts */ (void)readl_relaxed(base + QSPI_SR); /* Set QSPI Instruction Frame registers */ - writel_relaxed(iar, base + QSPI_IAR); - writel_relaxed(icr, base + QSPI_ICR); - writel_relaxed(ifr, base + QSPI_IFR); + writel_relaxed(cfg->iar, base + QSPI_IAR); + if (op->data.dir == SPI_MEM_DATA_OUT) + writel_relaxed(cfg->icr, base + QSPI_ICR); + else + writel_relaxed(cfg->icr, base + QSPI_RICR); + writel_relaxed(cfg->ifr, base + QSPI_IFR); + + return 0; +} + +static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); + void __iomem *base = aq->regs; + struct atmel_qspi_cfg cfg = {0}; + u32 sr; + int err; + + /* Set the QSPI controller in Serial Memory Mode */ + if (!(aq->mr & QSPI_MR_SMM)) + writel_relaxed(QSPI_MR_SMM, base + QSPI_MR); + + err = aq->caps->ops->set_qspi_cfg(base, op, &cfg); + if (err) + return err; /* Skip to the final steps if there is no data */ if (op->data.nbytes) { @@ -291,11 +409,11 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) /* Send/Receive data */ if (op->data.dir == SPI_MEM_DATA_IN) - _memcpy_fromio(op->data.buf.in, - aq->mem + iar, op->data.nbytes); + _memcpy_fromio(op->data.buf.in, aq->mem + cfg.iar, + op->data.nbytes); else - _memcpy_toio(aq->mem + iar, - op->data.buf.out, op->data.nbytes); + _memcpy_toio(aq->mem + cfg.iar, op->data.buf.out, + op->data.nbytes); /* Release the chip-select */ writel_relaxed(QSPI_CR_LASTXFER, base + QSPI_CR); @@ -395,9 +513,22 @@ static int atmel_qspi_probe(struct platform_device *pdev) struct spi_controller *ctrl; struct atmel_qspi *aq; struct resource *res; + const struct atmel_qspi_caps *caps; + struct device *dev = &pdev->dev; int irq, err = 0; - ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq)); + caps = of_device_get_match_data(dev); + if (!caps) { + dev_err(dev, "Could not retrieve QSPI caps\n"); + return -EINVAL; + } + + if (!caps->ops->set_qspi_cfg) { + dev_err(dev, "Could not retrieve QSPI ops\n"); + return -EINVAL; + } + + ctrl = spi_alloc_master(dev, sizeof(*aq)); if (!ctrl) return -ENOMEM; @@ -413,29 +544,33 @@ static int atmel_qspi_probe(struct platform_device *pdev) init_completion(&aq->cmd_completion); aq->pdev = pdev; + aq->caps = caps; /* Map the registers */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); - aq->regs = devm_ioremap_resource(&pdev->dev, res); + aq->regs = devm_ioremap_resource(dev, res); if (IS_ERR(aq->regs)) { - dev_err(&pdev->dev, "missing registers\n"); + dev_err(dev, "missing registers\n"); err = PTR_ERR(aq->regs); goto exit; } /* Map the AHB memory */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap"); - aq->mem = devm_ioremap_resource(&pdev->dev, res); + aq->mem = devm_ioremap_resource(dev, res); if (IS_ERR(aq->mem)) { - dev_err(&pdev->dev, "missing AHB memory\n"); + dev_err(dev, "missing AHB memory\n"); err = PTR_ERR(aq->mem); goto exit; } /* Get the peripheral clock */ - aq->clk = devm_clk_get(&pdev->dev, NULL); + aq->clk = devm_clk_get(dev, "pclk"); + if (IS_ERR(aq->clk)) + aq->clk = devm_clk_get(dev, NULL); + if (IS_ERR(aq->clk)) { - dev_err(&pdev->dev, "missing peripheral clock\n"); + dev_err(dev, "missing peripheral clock\n"); err = PTR_ERR(aq->clk); goto exit; } @@ -443,32 +578,52 @@ static int atmel_qspi_probe(struct platform_device *pdev) /* Enable the peripheral clock */ err = clk_prepare_enable(aq->clk); if (err) { - dev_err(&pdev->dev, "failed to enable the peripheral clock\n"); + dev_err(dev, "failed to enable the peripheral clock\n"); goto exit; } + if (caps->has_qspick) { + /* Get the QSPI system clock */ + aq->qspick = devm_clk_get(dev, "qspick"); + if (IS_ERR(aq->qspick)) { + dev_err(dev, "missing system clock\n"); + err = PTR_ERR(aq->qspick); + goto disable_clk; + } + + /* Enable the QSPI system clock */ + err = clk_prepare_enable(aq->qspick); + if (err) { + dev_err(dev, + "failed to enable the QSPI system clock\n"); + goto disable_clk; + } + } + /* Request the IRQ */ irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_err(&pdev->dev, "missing IRQ\n"); + dev_err(dev, "missing IRQ\n"); err = irq; - goto disable_clk; + goto disable_qspick; } - err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, - 0, dev_name(&pdev->dev), aq); + err = devm_request_irq(dev, irq, atmel_qspi_interrupt, 0, + dev_name(dev), aq); if (err) - goto disable_clk; + goto disable_qspick; err = atmel_qspi_init(aq); if (err) - goto disable_clk; + goto disable_qspick; err = spi_register_controller(ctrl); if (err) - goto disable_clk; + goto disable_qspick; return 0; +disable_qspick: + clk_disable_unprepare(aq->qspick); disable_clk: clk_disable_unprepare(aq->clk); exit: @@ -484,6 +639,7 @@ static int atmel_qspi_remove(struct platform_device *pdev) spi_unregister_controller(ctrl); writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR); + clk_disable_unprepare(aq->qspick); clk_disable_unprepare(aq->clk); return 0; } @@ -492,6 +648,7 @@ static int __maybe_unused atmel_qspi_suspend(struct device *dev) { struct atmel_qspi *aq = dev_get_drvdata(dev); + clk_disable_unprepare(aq->qspick); clk_disable_unprepare(aq->clk); return 0; @@ -502,6 +659,7 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev) struct atmel_qspi *aq = dev_get_drvdata(dev); clk_prepare_enable(aq->clk); + clk_prepare_enable(aq->qspick); return atmel_qspi_init(aq); } @@ -509,8 +667,32 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend, atmel_qspi_resume); +static const struct atmel_qspi_ops atmel_sama5d2_qspi_ops = { + .set_qspi_cfg = atmel_sama5d2_qspi_set_cfg, +}; + +static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = { + .ops = &atmel_sama5d2_qspi_ops, +}; + +static const struct atmel_qspi_ops atmel_sam9x60_qspi_ops = { + .set_qspi_cfg = atmel_sam9x60_qspi_set_cfg, +}; + +static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = { + .ops = &atmel_sam9x60_qspi_ops, + .has_qspick = true, +}; + static const struct of_device_id atmel_qspi_dt_ids[] = { - { .compatible = "atmel,sama5d2-qspi" }, + { + .compatible = "atmel,sama5d2-qspi", + .data = &atmel_sama5d2_qspi_caps, + }, + { + .compatible = "microchip,sam9x60-qspi", + .data = &atmel_sam9x60_qspi_caps, + }, { /* sentinel */ } };