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Mon, 1 May 2023 18:03:15 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:15 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 01/20] iommu: Add IOMMU_DOMAIN_PLATFORM Date: Mon, 1 May 2023 15:02:45 -0300 Message-Id: <1-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BL0PR03CA0011.namprd03.prod.outlook.com (2603:10b6:208:2d::24) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: 2deba80c-bad4-427c-8e08-08db4a6e51d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hsRvXcj2FmGpHgEod8sLHwd7evkuKvn1U/BjFBJGkE8iuokcpTNJZ2D3c7ebPOAFgNJWCO0VN7j92/PVuoLnd8mjzhkLrBak9f0PYde+h9C/dfU/PsdGtCLfN8ydBRhnUyYG4lxbn4IijVodxxjfE4lT5Mav8YlpffL9arkkrXYAWU4aVl2oTCV2NX6dNfDTP2Wlt/WJDxNDvCLhe83KcuhScO+DZFjARv4L1c7tDLAIsWORKeUajhpx+oM11CUb2pgUUin6XPRDKxa6ezwrISl6lwXjtLl7tfUPB/9HEXEclJePtZLh3RP012n6IEX1suU/7tscwPUWKXMkCDnROIwDProm1MdGZBB88e9hgAwTR/NgXP+pKW2ZkLNs28MuMRvgd9NJmgeBxzeZsf2iC5XhNhzCTKHbclW5LYb9W8YjjXHwKEIrO7lDB3s81cXnhZy/c72bl2W+KjYsQn2tQmA6mHRu4vFP1hBj4ctrjOBSc65PdNGexCG92M6MQZPdo3Luoq83g0bmR3mYbU/6A/+KwVgIc+MwebHMHtkyjGfx6WirMhCTmzozIppEIoKmyRe2iYAUhlCpj7YqqINOsA/9MrYioI+YiNOi6dvZFZS4Y8/dc+/doQ7uYKyFOiF7mfQJWOY5KUYHXrakdO6qoEjtIfqSwLjtMTZQgfkieUL00iwEfMLZ46Cbx8UypsZjrlMR4GBY8QpCgyCxSopBUcLN6i06oYOvZE3gevyRHW3c3gtKkEigstBj62imezvA/T1KOfTD8jROwreBy/H3x5E8eHcvKrdvM1Z+phzlqTP5rRmCIhvNv16VHPNbP7Qm3XR82xfLLL+2QSegf03LRyyu7qioRvnvtEBlBto4f8vrE4fpa8peOpYCioja/PsiYCwc1IHfakH1E5AEvyN5oyoF8LNTpCcXrIx+kp29jU58e0xHepg9pWmGOR79BwgaIOMajySylsZ76sjiwbiwK76ZrIRBfu60F8sQYqeDmPynOY166Tgq3VsAw2GPMdcmalQQq+2WqumTC/LapRUpdIGmU+peZoHbmO0HT1ZOgXzVXw5OYxvs+BP7Uw9VBsIcTi856Uhyr3NbfwKLBlK+XEsDl3/ngKczx7mXJHqJ+OZbPsBFtBT5sQeEoqeo8CbRc7Uw2kuiDrseqoOLQwyr6m5FrC1Capa7ZGVE3GYWgNI3rXTOe5UYFXl/V3TZmVXiO2S0Cak6sDHgFecvzUmZJD/iM3tzXYOLW4PlOo3DkHK4dD4lYvO6uCecXRsu8ZSfwcWfE4Zqjy385JrvQnYdezckNun3si1fevYj8FI7yR/hwnYJxR+DM5TMA4ULO6KwlH+8T7KuQHVc2eLSbJSh9XC0VCWd5iAiLQ516TQHjyn4OYUdt4Tx66JTfoRc5Jo6tcqXZ3H5T8duIVbg+jg/GbxTigtQB+vyPMAPqkZiROtA5Ev39Sj/nDvJzKLNJI3Nu1Xoh7QdIyzs2bkpJ5rQPssu7SEQSVESKRon8ZV/TZw6k/4Ui4qMpJ75h9kKsvtqN1OL7VZdO6rauN7fDhgkeDKwXkW/vpx6OK9/3Dt/C1fHPO1JD710dSl0G8BuqsIr X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2deba80c-bad4-427c-8e08-08db4a6e51d4 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:08.4638 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IGj5Vuy26RiGIwYPEL0vSW0MBrawwOVgheyvBr2aPrzTpqZRUXB6tdM5G/9BwLFc X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is an opaque domain type that is an escape hatch for tegra-gart and fsl_pamu that we can't figure out how to convert into actual BLOCKING or IDENTITY domains. It is designed to preserve the original ops->detach_dev() semantic that these drivers were built around. The PLATFORM domain will be set as the default domain and attached as normal during probe. The drivers will ignore the initial attach from a NULL domain to the PLATFORM domain. After this, the PLATFORM domain's attach_dev will be called whenever we detach from an UNMANAGED domain (eg for VFIO). This is the same time the original design would have called op->detach_dev(). Add an ops->default_domain member so drivers can trivially opt into this mode. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 14 +++++++++++++- include/linux/iommu.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 532383e4e90f05..ba7f38630665b5 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1640,6 +1640,17 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) lockdep_assert_held(&group->mutex); + /* + * Allow legacy drivers to specify the domain that will be the default + * domain. This should always be either an IDENTITY or PLATFORM domain. + * Do not use in new drivers. + */ + if (bus->iommu_ops->default_domain) { + if (req_type) + return ERR_PTR(-EINVAL); + return bus->iommu_ops->default_domain; + } + if (req_type) return __iommu_group_alloc_default_domain(bus, group, req_type); @@ -1945,7 +1956,8 @@ void iommu_domain_free(struct iommu_domain *domain) if (domain->type == IOMMU_DOMAIN_SVA) mmdrop(domain->mm); iommu_put_dma_cookie(domain); - domain->ops->free(domain); + if (domain->ops->free) + domain->ops->free(domain); } EXPORT_SYMBOL_GPL(iommu_domain_free); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 7dbdd13d7ce046..ddcad3597c177b 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -64,6 +64,7 @@ struct iommu_domain_geometry { #define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */ #define __IOMMU_DOMAIN_SVA (1U << 4) /* Shared process address space */ +#define __IOMMU_DOMAIN_PLATFORM (1U << 5) /* * This are the possible domain-types @@ -80,6 +81,8 @@ struct iommu_domain_geometry { * invalidation. * IOMMU_DOMAIN_SVA - DMA addresses are shared process addresses * represented by mm_struct's. + * IOMMU_DOMAIN_PLATFORM - Legacy domain for drivers that do their own + * dma_api stuff. Do not use in new drivers. */ #define IOMMU_DOMAIN_BLOCKED (0U) #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) @@ -90,6 +93,7 @@ struct iommu_domain_geometry { __IOMMU_DOMAIN_DMA_API | \ __IOMMU_DOMAIN_DMA_FQ) #define IOMMU_DOMAIN_SVA (__IOMMU_DOMAIN_SVA) +#define IOMMU_DOMAIN_PLATFORM (__IOMMU_DOMAIN_PLATFORM) struct iommu_domain { unsigned type; @@ -248,6 +252,7 @@ struct iommu_iotlb_gather { * will be blocked by the hardware. * @pgsize_bitmap: bitmap of all possible supported page sizes * @owner: Driver module providing these ops + * @default_domain: If not NULL this will always be set as the default domain. */ struct iommu_ops { bool (*capable)(struct device *dev, enum iommu_cap); @@ -281,6 +286,7 @@ struct iommu_ops { const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; struct module *owner; + struct iommu_domain *default_domain; }; /** From patchwork Mon May 1 18:02:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFB7C7EE31 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ujo4DNsnYHrGigEPt1pHNgGfqsbXsO7WJ7p1uD1DH12jn97ZFjA9rfEwQM17UmSTPrtHuS/X9+FND1K9fMUmOHqW5LSVcs/kENu463itrVUpqjknDQUGvuzkDtQIGLlSmmbUgco0EjcViXXaauI3smv14WsPEvpcxIWpJuuwriHfpTEGc+Wf3wv1UARO8jCignUes30XrIiS9qtE+LmzxhLn9sLOn82A7+gGKyHbJsOO2f7y46MI5HPeVIELrywNtUDTURA2viebpbqwgpgTrRFKzjhetUgwXJlPbBfykG7Kcgu0gkAvb/yzC28t7cA6A0VzYMXji/AnOpeiu4Vj195HefxN1aKi2p6mAG+fZ1/QV0LfIhVSF9eIR5rjohIpaeuTJZZwCMone5yxpB1p1JZH94Me/k45H/Msy+r+N6pnXxTlEdwLU444EO0nFPm9SVyfFR2fa+jkGTfHrN/+Q4PvdzWOU4b8TZz+HxbKQuN1+Qa1Zq2uZPaY8cwrwLCbuZDJHGUeMxLAXg7Thm4BLuvL2LDNtxI1zb62vRwq6Y7eHeKtZY1T0s1P3AQcj1KQmm+MPdfaJS8VHUj2SM2DVuidggDkA6fBqICjBweifIpfzooVAmHOkr6V5zNbFImrPZaj1S9+Gn5pDnET3T1R8x4Ic7ED3udE/bQMMAFE59Riwe8w1+5wpPVxhOubKMTXu5OfjS37s0xOuGm6eYL56z0NSQc2Tru6ChFul0ojYliRApj/Bub66ADEV82JWmgDMsKUPfl50QOLlVagHrQjRac3jWSNkp9iBcEbNwXnuWxeXQape5mxDVK/Azl1WUfsGpzriDIWjtvXlPNpNZ2bG6vTFEbHgn3QMytJiBADDp59IkUONkjtWXcWViiLmTsk/GDvVqVZyK3rSrh92e9rcOj+g4FeJUPbVpJQ39c4Q6/SD7dFpVvBmPBvfmkY0Se40rBvkFtvWxRIkHeqtmckI4030psr6qtM+ipcOf8UVarzp9CmuOi4T9TrIa/Jvhov1f9avng6DQsk7PSPIrESQnY6meNdPyWkoYgKVOoczJ4iCx6KCNV50ex9qrk7Zocn3DarnaqiFPhXdRLEpt9kEcDrrdT8R5pBK961PxZagbTIXGm3bi9ayWa3/8vjtFowxcIUEbKxxWoiglnyQLCB6uVkJSsQ5NuvvlPI58sG8Kk/MQb2Io24h0zUtcTTuiBbTRn42LvPjCgwA2ppH8kKK71nAj8ABICw7L0PMVrcHLLDSKduIJmZFZhXQhUp7upghWvUlPRQBnVHPWxj/XqjSDjFFQiVjfyKWtSJAeLrav7r8B3llldGP2m2IOj9kZNHe+5p2A4d1HlSpd2S1/Au0qI9J1fPN1Qp5RM/ilxOd9G2ssDH7RTFQAqe4Lytn06O6cDCjZ2bA5wGqqvcQcxFgwvx8ISTrajPgHehFDOtpfkyCt4UMY4dJaJh3u4rdCCmgQAGfA/HJMCbeuoxxhNYh6FAk5PuSA3wuskRwBZicdvXnKHq68AgplXPcQjV1WedN9v0MB/VKSZ4VnKBjWbBa6tAkEdddKZetLD2XHjGNFofuhOwY+kgDf3U/5SL4p/W X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55fe19df-7941-4375-3a31-08db4a6e506a X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.1525 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jXtYuIMnNeXpU4o16wbYtFcNL0OpBXoVjqFNoLdyLbHsZzhMtKv1ysOxlbZwH/I2 X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org tegra-gart seems to be kind of wonky since from the start its 'detach_dev' op doesn't actually touch hardware. It is supposed to empty the GART of all translations loaded into it. Call this weirdness PLATFORM which keeps the basic original ops->detach_dev() semantic alive without needing much special core code support. I'm guessing it really ends up in a BLOCKING configuration, but without any forced cleanup it is unsafe. Signed-off-by: Jason Gunthorpe Signed-off-by: Robin Murphy --- drivers/iommu/tegra-gart.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index a482ff838b5331..09865889ff2480 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -124,11 +124,27 @@ static int gart_iommu_attach_dev(struct iommu_domain *domain, return ret; } -static void gart_iommu_set_platform_dma(struct device *dev) +/* + * FIXME: This weird function that doesn't touch the HW, but it is supposed to + * zap any current translation from the HW. + * + * Preserve whatever this was doing in 2011 as basically the same in the + * new API. The IOMMU_DOMAIN_PLATFORM's attach_dev function is called at almost + * the same times as the old detach_dev. + * + * I suspect the reality is that the UNMANAGED domain is never actually detached + * in real systems, or it is only detached once eveything is already unmapped, + * so this could get by this way. + */ +static int gart_iommu_platform_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct gart_device *gart = gart_handle; + if (domain == identity_domain || !domain) + return 0; + spin_lock(&gart->dom_lock); if (dev_iommu_priv_get(dev) == domain) { @@ -139,8 +155,18 @@ static void gart_iommu_set_platform_dma(struct device *dev) } spin_unlock(&gart->dom_lock); + return 0; } +static struct iommu_domain_ops gart_iommu_platform_ops = { + .attach_dev = gart_iommu_platform_attach, +}; + +static struct iommu_domain gart_iommu_platform_domain = { + .type = IOMMU_DOMAIN_PLATFORM, + .ops = &gart_iommu_platform_ops, +}; + static struct iommu_domain *gart_iommu_domain_alloc(unsigned type) { struct iommu_domain *domain; @@ -267,10 +293,10 @@ static void gart_iommu_sync(struct iommu_domain *domain, } static const struct iommu_ops gart_iommu_ops = { + .default_domain = &gart_iommu_platform_domain, .domain_alloc = gart_iommu_domain_alloc, .probe_device = gart_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = gart_iommu_set_platform_dma, .pgsize_bitmap = GART_IOMMU_PGSIZES, .of_xlate = gart_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Mon May 1 18:02:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 911F6C88C8C for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: e/jPfL8RYF0ErXm3y+HcWRPqJl/lvU4/+k75s4Uj9v02yjGolT4xGBqV+FsOq1jn/OlHqS/RLv0K6bX9T0awyyhBuoAF5Q59aG0L5vS9TsIHIUSiGCrBSaxQD/ziHM8lcoefbXy5+oXWAGuinSHe1TIVf9On0pgNBe5LhOfYJPhrDbFXFpi5F9BIVONv5iKFdZJkQnLffYOWvkuZo2lJhZRX8VhsebvU4mkYMmsFbmunhvVlVd4zHo1BjTZIKmZzVA2nwpOtd8PmUdGB4IZ6Qef+PQsM0t6hXfYsoiCXuWYbWzy+9ujcpAhObZT8DGlKab6cQH96HyNjo0J1JYFTFZFrwmopZnM4TySfxC/M/fVt+yc7X/hA7juuIjdGX021BBNO3sZTaCpPikgzsD0PL02jJ7A9jGkejdOJCoe6OxVPx/U0LXD0P1PfzJ4X1SYmSATvDQemj49zgtYtPgbqfmoQmEN+rSAH5L08Edy9j6SzCD3nfsT0osklaH/HNWeONcPKBjgZw0J5M5aX/WCfKRUEfpC0pKwtt215ImOq5x3XfsuiukEPMGYSw3hP5ZoJb/ca8jbxqMK44KARwW6mhECaWal6Bqiqs94GEOcFb6UpSYYupooBmNgQCqPYNrZcZODhXK5edwexNOuOPNPpY/XjKb/bId7k3tN20YwA3asWXcWIzsT5XKavuZP6POFDV5T+9tvF7gBsfuEwkMVbTeb2jR11PTHxTY6Bbwuz2HVsfrg48mu2v1BpUQJOcgrqhDr1pG90j6oEOViaRpAnHDshXVF03oKXGcIKHCUQZhmNYtQRmkHu7io6lYgXM8prOk56Mrp8/wMrytoGnp8rq/Vj9CUhGylXKREbSEmoeOOMbPyv99CO29paYnmfboyTFokyRtTE/jjgUyIhhWuLpitGIa0RxxkrS/xtThpi//K8WHfgjvi1rYI32hhz6xLDo1I9kJk9vNxwjCbd3ycHAiD7C7vS/qX824KmeUcaCxyhjMpFgsCKn1324D6Lxa26jdWxUkUwS6hJ1lHYsYof7BdBvd7/PwdkLP2TS4VP0KOfe4/BFzRxAsnQ8Q1duI5IsSHmisQZh7s+WNbcR3LfNisuVtRVK9UGd2vk9ebEz+f+QXR0OGOHWuUUQ6JIsXeT8i8KPhvzf0JR1ABvKZ7UQLrt6ycgU+bBD4cimVmL/B2XTKskaATqGHFGLtsZmjc+E0lTW+PTynYx+aqoj3D9RGzIXi22UqWVoi4ouLQ1y+tL0u5J+OpeWmZd4f9KObYN2RqsPuo2RNEkDVwLjZ4oObssCgZegzm0BXlkxoMFIetZISqrFdsHI1Rwphm6tCoWxipJAysKu3GL2cQ25LKa7/26YYOCofHA8UOxB7RzsHNi+YFhRqTE0mWYk9gEFkS0giC5s7YBPM+3uj3mhLGir3LVWEthLmYjoJCsupYKlG2KLJsZwe7lDH6LzgY5nC3rLbVvfV7pwMcMl+PCD5WejTGQiclCXwC6zSQPY8FyKuZqrw31fWLpGTShQqKltbx731mu+GHTxHHYfW7P3vCRbLQumd387/WmnMUABkpgYizG9ktfEnDopU7d2R3VburU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3313699-3c9b-470b-6714-08db4a6e5100 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:07.0626 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iOGqNzpnX6uMN5jqWHADGQu8v4D1o3wPLBanlFr2QHDcgOSPJAt4BHfCxDgiTljZ X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is temporary until the S390 dma-iommu.c conversion is merged. s390 is actually moving the dma_ops over to platform control. Signed-off-by: Jason Gunthorpe Reviewed-by: Niklas Schnelle --- drivers/iommu/s390-iommu.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/s390-iommu.c b/drivers/iommu/s390-iommu.c index fbf59a8db29b11..f0c867c57a5b9b 100644 --- a/drivers/iommu/s390-iommu.c +++ b/drivers/iommu/s390-iommu.c @@ -142,14 +142,31 @@ static int s390_iommu_attach_device(struct iommu_domain *domain, return 0; } -static void s390_iommu_set_platform_dma(struct device *dev) +/* + * Switch control over the IOMMU to S390's internal dma_api ops + */ +static int s390_iommu_platform_attach(struct iommu_domain *platform_domain, + struct device *dev) { struct zpci_dev *zdev = to_zpci_dev(dev); + if (!zdev->s390_domain) + return 0; + __s390_iommu_detach_device(zdev); zpci_dma_init_device(zdev); + return 0; } +static struct iommu_domain_ops s390_iommu_platform_ops = { + .attach_dev = s390_iommu_platform_attach, +}; + +static struct iommu_domain s390_iommu_platform_domain = { + .type = IOMMU_DOMAIN_PLATFORM, + .ops = &s390_iommu_platform_ops, +}; + static void s390_iommu_get_resv_regions(struct device *dev, struct list_head *list) { @@ -428,12 +445,12 @@ void zpci_destroy_iommu(struct zpci_dev *zdev) } static const struct iommu_ops s390_iommu_ops = { + .default_domain = &s390_iommu_platform_domain, .capable = s390_iommu_capable, .domain_alloc = s390_domain_alloc, .probe_device = s390_iommu_probe_device, .release_device = s390_iommu_release_device, .device_group = generic_device_group, - .set_platform_dma_ops = s390_iommu_set_platform_dma, .pgsize_bitmap = SZ_4K, .get_resv_regions = s390_iommu_get_resv_regions, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Mon May 1 18:02:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E003C8300C for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: U6MLybbVwidRwLF4iY4srRhmG+VvsymO40k27xpXtgXXKc5heHQma235dMLlYdn4QHI9icSBT7xmrsmXjc1vq2UGIzZoK0zwoSehbE4iIpUhQy06gOuTNy/6BdvzD0KsaR6uDnnTaBqvQOuS4q2vlk6aBoP7dOPsk59dVCQPRm2wsTwkoULIf1WAOTvttAZ0lE4zO6mTHtQbU+oMyDO/6ni6tml3a578tXVK09jpoEkm3RdwLCsBkHqwYhDozqYiefFwzbLRSgIqiCxJC7YmPsI6nscSo76hzftjiLOGlIn1+dq0EfIoGQqVQZa6LizVGj/yuxXv9376oP01iLDMRN5RHVpwpGFzCi8blsRiMvEHM3w/Zs9G5gPpO8wGn6FlUqN5ag5VKLY/lEndLm7Nj0EKOZv+SNWr9ZvyLPDtQd0SDTdUZqOx/aBegAqK4uzPk1+eE0FYlxeI3b9GlOmexGYcg2lh53XegXz89LDAZxOz+g24yYmfuyUZyowdfPepBr8eiODU+sIe8MQdH6Hio+lFzXvtGpxTdtbnzUUfa/P/odc92xx0zYUgarqudSNdQgT0YokphiZdHico5TVD+UGpOvQLxZHZ22XMSgixdlBDyXzKvOe3VJ/SNYI2kodQDJwjD65axCjtJP6aFBloSL87YZflSFLthH2Z2DNYhleXaJ8oHg0FmEjrDznJix/uSbMXeLXTNJQUxvKKGfkOyCISY8ZL0ANFik9CRlqTZ5SMQILZJHWXzOllQPpmOuao2SEHfbZAsQP6BaBFsNKEpplmYX05gKKZgsL5DahZJf4p6yfxDzFvxAZc8IVqo5KutEYMMRiw5F87Lmy6Fozc2UUI2B+UvRouCpQNAf8w01B20GpbYbvYlprSKMBK3QIDLCWi7FGkdG+dtoJ8JgqJRAxUmIbeVaM1EKznmmeTsuJGS1rrbHotu/7AVN5Ahufv1RnpNqrT28db4rdcWiq4M2h/WpgE42xUDWjxC8umeuBJkzkL57s6zD9oMu54ZhrmSUtWwwvbovjTJIyU1q5TfzbP203S0V6j30Yj+AViNAjjG1zSUheXxjWBqlI2TZaaJ3+kssaeSkNDqaMcTH6bmWtcvMGMJZH/j31w1Rg3/Z+r79pS/lNzQwjrZ2oK280UFQvo2FfmQwG7pWx6RtnNUoA/R2BnMMiEBfgOo9zEWBP33/PLkQ5wLaVx+jJ2w5eG8VZqSIdxUekIvTPBwA+t5lKMCptywc1J7uFS0bKEPyxDGJzlbS0J4Iiex1m3EJQsKI8eXqwKBtascZBkp1rp81X0HQS/7H0xH2j6DiRm86SMo5ZpyCecv5LNz+ScXm0RBTwrkroTGtY6N1fUTfhQpRQuhRFmNQQaH7WJ6nqJP4doXK2VoAEmwOQE3ABXllFSRn79gzEWJ7qhj1SF/4tcEiKguH5YYHISwthx0pMTZEUQ3D1GwmfJdyPoBoYMWupp+UvfvKIK5qqpveBIkXEHRD0nDoHIbeG/JPYNtM3eq7fGlN7db6EczRT1auObkRH5gc0SilSTeeSUCcr5HIvqy0bsYrQCzb03osqxho8OUhV+W9uxbyDh6ZVKVwpWWtu6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: adcf4832-1e31-4019-ae4d-08db4a6e507f X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.2178 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nOZU18h5DevEHzXoxIDF3M/kz4s4QPYAvvpzw36MPtpHEMWnlk63Eia1JQGQWkWv X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It is not clear what this is actually doing, most likely this is IDENTITY behavior, but I think there is a chance it is BLOCKING given how the PAMU stuff is oddly used. Signed-off-by: Jason Gunthorpe --- drivers/iommu/fsl_pamu_domain.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index bce37229709965..4c65f1adfe7511 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -283,15 +283,28 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain, return ret; } -static void fsl_pamu_set_platform_dma(struct device *dev) +/* + * FIXME: This seems to turn off the iommu HW but it is not obvious what state + * it leaves the HW in. This is probably really a BLOCKING or IDENTITY domain. + * For now this ensures that the old detach_dev behavior functions about the + * same as it always did, and we turn off the IOMMU whenever the UNMANAGED + * domain is detached. + */ +static int fsl_pamu_platform_attach(struct iommu_domain *platform_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct fsl_dma_domain *dma_domain = to_fsl_dma_domain(domain); + struct fsl_dma_domain *dma_domain; const u32 *prop; int len; struct pci_dev *pdev = NULL; struct pci_controller *pci_ctl; + if (domain == platform_domain || !domain) + return 0; + + dma_domain = to_fsl_dma_domain(domain); + /* * Use LIODN of the PCI controller while detaching a * PCI device. @@ -312,8 +325,18 @@ static void fsl_pamu_set_platform_dma(struct device *dev) detach_device(dev, dma_domain); else pr_debug("missing fsl,liodn property at %pOF\n", dev->of_node); + return 0; } +static struct iommu_domain_ops fsl_pamu_platform_ops = { + .attach_dev = fsl_pamu_platform_attach, +}; + +static struct iommu_domain fsl_pamu_platform_domain = { + .type = IOMMU_DOMAIN_PLATFORM, + .ops = &fsl_pamu_platform_ops, +}; + /* Set the domain stash attribute */ int fsl_pamu_configure_l1_stash(struct iommu_domain *domain, u32 cpu) { @@ -448,11 +471,11 @@ static struct iommu_device *fsl_pamu_probe_device(struct device *dev) } static const struct iommu_ops fsl_pamu_ops = { + .default_domain = &fsl_pamu_platform_domain, .capable = fsl_pamu_capable, .domain_alloc = fsl_pamu_domain_alloc, .probe_device = fsl_pamu_probe_device, .device_group = fsl_pamu_device_group, - .set_platform_dma_ops = fsl_pamu_set_platform_dma, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = fsl_pamu_attach_device, .iova_to_phys = fsl_pamu_iova_to_phys, From patchwork Mon May 1 18:02:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FB05C7EE26 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Y2FBskTv9l9HICdtPjSM7LD5Mke7AJeWYgtsigrlSIcp0LDXavA6svuY8RlgkwgOfEmEgSeb5CYrF9FV9N0ZqEHxWQ6QDIVrN0bDnf6jJMJ9sfLrtm217Dzu5nQRD5Dn2xzshg898cFF0Oa9N5+OL/9BRSYQFcYZOBlAlawAAelqvIo+ErwxRInEZVtktPbCrUQvDTa1J4j+NIHRv85bGK99+ZOkGDLoJOq8azrXcgNOfwtStZeV6Y0yfDrUPcYs35qTniuiY5Y+qkolWC/j44cZsrR1MsYwrOW+t+gn6SezPP9hXv6+KaBDKt/f8Sr4MoWaUNYOT9bDGKpfR+7cCV3xc04wYAWvHQxquN3mtVFpVqHxiROnnI3yWowTt0sxknYB9fXrW7HGxOv91vEcZABNfRWEzkBPZxhw7QFMaOVmUlG8T/Qfm8HfWC0CT0ylgFsA4lANOz/xR/W6ODYvtxh+eNctnfQ+gKwF8enmU6F+Oh4BTf8Rs5pRQ6iP62T0Ho0XxG1MDyS+RVkScSicNodSER+rm4LwkVPHK/PmaqsHOsVrnWGwHbTsMjprz/eo+jif1gXjMOFDw0MkTQb6WPak+lDOjfM54yQgFXrqSCbx/utrUVb2RyLFCieL0tg8or4LVI0UH2BfbBVNttqbgN5Su9NFRzULAgVRQNvc3Q2hYCiPvyJH4LtbXEMwHPrir4eGBaD/obhRk3T0UgWhBZb9RZg0TUtK1RP0d8kFcuUuq6E/3W+HEoVzk/tcauDlcyAGLvDmnbPKyEHd78zn1hz+YahM0AfOZFVdijYOHHsy6WivivfOfUKfU/TVOxqOwYipaHtamf7V0DDXf3z9mdPA9d0J+3WSSERJDoIfCHWdh4URBmh/vw6OxjHjzYIsdL2JVq6jz8JOksDU+dw6fifttedeLOO8W5ZxXDcDZo44WHl+Vrve5nRKK2FLBkhpd7dSUI6iKO9bmyqazZ92N/5o4PbJFo9E0Sms8Jq39X7VzEMAlrPIPR6HfCUuAx5TssK7VTosmf/JF9nXfyhRyJE6yq9dSRE7/Paf8bhbCyJFIvYxcnDhoGgAuX8GHG2RaO1TAOAx1UgQ0wIfQwB4T+wLi8kcio8EHnswi/3QzXDPLETkMq+tX1vfnoGjiZm1u0vytbJV+utXHO+Z6YnrlHkqTjy9df+zuYU9a+xLHG85enAD2hbQC9uH3Zqi0A4fiYC/6bQ/ce+tW2fa+h4sUYp8GVRTJwSXN0d+qkygYGpDvcgZJnI6yg0xGIwglZwSSCLfd9LMZ+2waf6xT1BWmUNhKFtLqLjlPIVHYaShAGmfy68H6puy07sr3xwDMj4PkSSfQQdlMWpHOWyB+sRUISzFNmLw5DXOyehKcKCHQILMBajI2LA8JjNg87rijj4R4SYwgXVcOwq501J/DXfaFiR9CgtU4fHgHqYmkCDrG96nCdOHBJAVtzeKpz3VAcq/IAIw/tTQbZEHHzHEE4axSe6B7z105yHX0FA6Rb7oOr4J9/08QOH04qJVpAdhzZrFIE1ralEy7kFhAUbDgGOtkarP4LJlA5ozRAmjOi98dlltecSxVY7/KasLKbhzrm6H X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: bff25f15-ab48-4979-66d2-08db4a6e5033 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:05.7808 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DlAHCrj5CKYxsNaomLa5xqT+yDeg/WUK9mmL3PgNFAYF2Xt2sbzgTAyDaW0+C07P X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Even though dma-iommu.c and CONFIG_ARM_DMA_USE_IOMMU do approximately the same stuff, the way they relate to the IOMMU core is quiet different. dma-iommu.c expects the core code to setup an UNMANAGED domain (of type IOMMU_DOMAIN_DMA) and then configures itself to use that domain. This becomes the default_domain for the group. ARM_DMA_USE_IOMMU does not use the default_domain, instead it directly allocates an UNMANAGED domain and operates it just like an external driver. In this case group->default_domain is NULL. Allow iommu drivers to specify a global static identity_domain and, if present, automatically use this domain as the default_domain when in ARM_DMA_USE_IOMMU mode. This allows drivers that implemented default_domain == NULL as an IDENTITY translation to trivially get a properly labeled non-NULL default_domain on ARM32 configs. With this arrangment when ARM_DMA_USE_IOMMU wants to disconnect from the device the normal detach_domain flow will restore the IDENTITY domain as the default domain. Overall this makes attach_dev() of the IDENTITY domain called in the same places as detach_dev(). This effectively migrates these drivers to default_domain mode. For drivers that support ARM64 they will gain support for the IDENTITY translation mode for the dma_api and behave in a uniform way. Drivers use this by setting ops->identity_domain to a static singleton iommu_domain that implements the identity attach. If the core detects ARM_DMA_USE_IOMMU mode then it automatically attaches the IDENTITY domain during probe. If the driver does not want to support dma_api with translation then it always sets default_domain to the identity domain and even if IOMMU_DMA is turned on it will not allow it to be used. This allows removing the set_platform_dma_ops() from every remaining driver. Add the core support and convert rockchip to use it. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 13 +++++++++++++ drivers/iommu/rockchip-iommu.c | 19 +------------------ include/linux/iommu.h | 3 +++ 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index ba7f38630665b5..8b9af774de68f1 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1654,6 +1654,16 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) if (req_type) return __iommu_group_alloc_default_domain(bus, group, req_type); + /* + * ARM32 drivers supporting CONFIG_ARM_DMA_USE_IOMMU can declare an + * identity_domain and it becomes their default domain. Later on + * ARM_DMA_USE_IOMMU will install its UNMANAGED domain. + */ + if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) && + bus->iommu_ops->identity_domain) + return __iommu_group_alloc_default_domain( + bus, group, IOMMU_DOMAIN_IDENTITY); + /* The driver gave no guidance on what type to use, try the default */ dom = __iommu_group_alloc_default_domain(bus, group, iommu_def_domain_type); if (dom) @@ -1923,6 +1933,9 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, if (bus == NULL || bus->iommu_ops == NULL) return NULL; + if (type == IOMMU_DOMAIN_IDENTITY && bus->iommu_ops->identity_domain) + return bus->iommu_ops->identity_domain; + domain = bus->iommu_ops->domain_alloc(type); if (!domain) return NULL; diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index ea5a3088bb7e8a..9e1296a856ac4c 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1017,13 +1017,8 @@ static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, return 0; } -static void rk_iommu_identity_free(struct iommu_domain *domain) -{ -} - static struct iommu_domain_ops rk_identity_ops = { .attach_dev = rk_iommu_identity_attach, - .free = rk_iommu_identity_free, }; static struct iommu_domain rk_identity_domain = { @@ -1031,13 +1026,6 @@ static struct iommu_domain rk_identity_domain = { .ops = &rk_identity_ops, }; -#ifdef CONFIG_ARM -static void rk_iommu_set_platform_dma(struct device *dev) -{ - WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev)); -} -#endif - static int rk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { @@ -1087,9 +1075,6 @@ static struct iommu_domain *rk_iommu_domain_alloc(unsigned type) { struct rk_iommu_domain *rk_domain; - if (type == IOMMU_DOMAIN_IDENTITY) - return &rk_identity_domain; - if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) return NULL; @@ -1214,13 +1199,11 @@ static int rk_iommu_of_xlate(struct device *dev, } static const struct iommu_ops rk_iommu_ops = { + .identity_domain = &rk_identity_domain, .domain_alloc = rk_iommu_domain_alloc, .probe_device = rk_iommu_probe_device, .release_device = rk_iommu_release_device, .device_group = rk_iommu_device_group, -#ifdef CONFIG_ARM - .set_platform_dma_ops = rk_iommu_set_platform_dma, -#endif .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, .of_xlate = rk_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ddcad3597c177b..427490b5736d40 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -253,6 +253,8 @@ struct iommu_iotlb_gather { * @pgsize_bitmap: bitmap of all possible supported page sizes * @owner: Driver module providing these ops * @default_domain: If not NULL this will always be set as the default domain. + * @identity_domain: An always available, always attachable identity + * translation. */ struct iommu_ops { bool (*capable)(struct device *dev, enum iommu_cap); @@ -287,6 +289,7 @@ struct iommu_ops { unsigned long pgsize_bitmap; struct module *owner; struct iommu_domain *default_domain; + struct iommu_domain *identity_domain; }; /** From patchwork Mon May 1 18:02:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37DA3C7EE26 for ; Mon, 1 May 2023 18:03:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232511AbjEASDL (ORCPT ); Mon, 1 May 2023 14:03:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232473AbjEASDJ (ORCPT ); Mon, 1 May 2023 14:03:09 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2050.outbound.protection.outlook.com [40.107.94.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F8D710F9; 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Mon, 1 May 2023 18:03:06 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:05 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 06/20] iommu/exynos: Implement an IDENTITY domain Date: Mon, 1 May 2023 15:02:50 -0300 Message-Id: <6-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR06CA0023.namprd06.prod.outlook.com (2603:10b6:208:23d::28) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: 4615b5b2-cb88-4ae9-7bc7-08db4a6e5027 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7ZUXCtwX/2iBuJ0V+BAJxISHlfwsdWMnhI5UA78r+RIDtN5cmMckqSfQqhfiqvSF9RXvv4e8M/0vLvpTgmB2soX7LTrbYQXftFj+ytCW0NvOm9QGOhEhEcEdrQylWFCd+U+BM1UGYnRXCb06pDGAL/P3Kb+1Ty8o8ICT2cwMz826nDnoc1inXuU/bQhA4N0CX/OfqlglBBCbD/aBvKUXOHsT9wVZl1NgR5/B+AYOpca9vfNZepYnXM/G2K3atwXgYZPG1kVaOti4Vi0ezMnDmVwK+6e2HPtOeYzQMTnnf986ZQHrT0lw7H6i9CKZaMFHOLozjdKEHjdHfX0V5RGpovw0Ff5PKhlcJ00L8T+OwyM0BiAwzJY1/E0PFzqyRHFDgsOTAGKGQQPrlnrU5RINEmLlxVgd+NAQO/LJYMgmx6Ng1QbLN6Wl24Csl2FNDqdBsc+KLcctGLR7V47/Bafyo7OvtZxIqKXuhVyftExYGHIAyg8/VZ6a/pvqJUp/AW/U4c26zCw7FGB5hySIorqHkf/oQwiqXoXbENMcVem+dYLGlVRBxg76KCo+hOvV2rv0yrn7eBexi73ZK2r9qNL2Z034+NMk6IklCBLRb80QiQf3vCabU5CtqXf7v5FHWb14MfmQuo99luguJbFAB528nkm4xorRThPWpRbKO83t3o7tF+GP0pwG03FE232GK65Q15SKGEKeNaWZkuMbkxG7USzpVRU0B8L/0BvIvU2dtgLxiObn70tSw/nfTGefIwf59UkpfDIpACypaDjqHvfqh+tsZ+6hkYJZJgOxBJHJXDFzh/1Nty8KLmbFdL0jzixyQ5Gb2V+dhwRhk4BAUBhvbfYUkXkMLkhxaITg4SqIvTGSKXUK1XXI406z47yPjmwBQq+i8ksBF7Bi8AWkxAUcqz/+2qDvQBzmZoErwhMdwew1g79Gwvj6wBjSCATP9eLik00FwDWEHhz2qLF2VaBqnrpalOxpjzmfFpV5GLozhLpj/8CBwoWm2l7tINDArMg8tkEc8s3lMHhWise0/901jcRb6Dau1eRJ+mJ7aZLzTYb2vnadjlsI+5BHZkI5c+WTLUCKuckprjfTmg5zJjKXPA12i3k7tz+93dEOFyHQnGqjb+4WXgL3heoapUtg6sxPHKsOFZ9uOAKsGRBl6sHS/XJNuuokeI8gMidTdT9HCk7uMxaQJFydx6mASvgGyOL47rO5D0wbXF0zZaa7qCwCWCI5YvHPb8XefblRXEvf8o/216yoAqwiHrtpwjgcdMGJUng7Rm7fjUiyHmpI0FHkO8Hh9QU19nPzQy5spvOciQRLnm6QtddFL1Hb3psVogVNkErCoearoqVnkZli6mGZ8AfyVX4OZ6ZuKbXHYSKyy/+y93qNSBBlQ1cs3RxeOj/nzNMimhYBhX42Z7LlBj/hueMaKUKJI+n8WwQmydbrZ7BD868gu9f6UVjQCkCqVt6r8J/LRhsM5fBse1xjctnuG98F1ulRk4aarwOT6SN66HWcCpzubQ5p5uHuTRl4aSitGt8fI6RyKxRhw7wkZYuCSsCEPPHs4sDH5ztCovBC143CMnxZseTF5XoKjPAnD5pQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4615b5b2-cb88-4ae9-7bc7-08db4a6e5027 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:05.6881 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xLpIQerFkLDXEfBUcT+yR/O4njgalSuMAVHAw1eHK7iUSIu+rS1+ktjP6t28u1cn X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What exynos calls exynos_iommu_detach_device is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/exynos-iommu.c | 64 ++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c275fe71c4db32..6ff7901103948a 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -24,6 +24,7 @@ typedef u32 sysmmu_iova_t; typedef u32 sysmmu_pte_t; +static struct iommu_domain exynos_identity_domain; /* We do not consider super section mapping (16MB) */ #define SECT_ORDER 20 @@ -829,7 +830,7 @@ static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); - if (data->domain) { + if (&data->domain->domain != &exynos_identity_domain) { dev_dbg(data->sysmmu, "saving state\n"); __sysmmu_disable(data); } @@ -847,7 +848,7 @@ static int __maybe_unused exynos_sysmmu_resume(struct device *dev) struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); - if (data->domain) { + if (&data->domain->domain != &exynos_identity_domain) { dev_dbg(data->sysmmu, "restoring state\n"); __sysmmu_enable(data); } @@ -980,17 +981,22 @@ static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) kfree(domain); } -static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, - struct device *dev) +static int exynos_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { - struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - phys_addr_t pagetable = virt_to_phys(domain->pgtable); + struct exynos_iommu_domain *domain; + phys_addr_t pagetable; struct sysmmu_drvdata *data, *next; unsigned long flags; - if (!has_sysmmu(dev) || owner->domain != iommu_domain) - return; + if (!owner) + return -ENODEV; + if (owner->domain == identity_domain) + return 0; + + domain = to_exynos_domain(owner->domain); + pagetable = virt_to_phys(domain->pgtable); mutex_lock(&owner->rpm_lock); @@ -1009,15 +1015,25 @@ static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, list_del_init(&data->domain_node); spin_unlock(&data->lock); } - owner->domain = NULL; + owner->domain = identity_domain; spin_unlock_irqrestore(&domain->lock, flags); mutex_unlock(&owner->rpm_lock); dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, &pagetable); + return 0; } +static struct iommu_domain_ops exynos_identity_ops = { + .attach_dev = exynos_iommu_identity_attach, +}; + +static struct iommu_domain exynos_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &exynos_identity_ops, +}; + static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, struct device *dev) { @@ -1026,12 +1042,11 @@ static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, struct sysmmu_drvdata *data; phys_addr_t pagetable = virt_to_phys(domain->pgtable); unsigned long flags; + int err; - if (!has_sysmmu(dev)) - return -ENODEV; - - if (owner->domain) - exynos_iommu_detach_device(owner->domain, dev); + err = exynos_iommu_identity_attach(&exynos_identity_domain, dev); + if (err) + return err; mutex_lock(&owner->rpm_lock); @@ -1407,26 +1422,12 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) return &data->iommu; } -static void exynos_iommu_set_platform_dma(struct device *dev) -{ - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - - if (owner->domain) { - struct iommu_group *group = iommu_group_get(dev); - - if (group) { - exynos_iommu_detach_device(owner->domain, dev); - iommu_group_put(group); - } - } -} - static void exynos_iommu_release_device(struct device *dev) { struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data; - exynos_iommu_set_platform_dma(dev); + WARN_ON(exynos_iommu_identity_attach(&exynos_identity_domain, dev)); list_for_each_entry(data, &owner->controllers, owner_node) device_link_del(data->link); @@ -1457,6 +1458,7 @@ static int exynos_iommu_of_xlate(struct device *dev, INIT_LIST_HEAD(&owner->controllers); mutex_init(&owner->rpm_lock); + owner->domain = &exynos_identity_domain; dev_iommu_priv_set(dev, owner); } @@ -1471,11 +1473,9 @@ static int exynos_iommu_of_xlate(struct device *dev, } static const struct iommu_ops exynos_iommu_ops = { + .identity_domain = &exynos_identity_domain, .domain_alloc = exynos_iommu_domain_alloc, .device_group = generic_device_group, -#ifdef CONFIG_ARM - .set_platform_dma_ops = exynos_iommu_set_platform_dma, -#endif .probe_device = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, From patchwork Mon May 1 18:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B1A3C7EE2C for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AD3aoS0JNdc0owfrl6ClZh+3NiSP4vTJbYQqj/mfEmBfMox9OtNd+RZVCmN2GehGbqBRt/CbqUwtoV3jDQ4bF+0+MdIQ6Leyj64U6FUL+l+DWD7tdfSwm35Eo20SGQ1QpNxHJYuG+7UIeazivRb9/DWWUzcVcOEQJ8b7J6Gs7BRjrU7uj68o0cuel1F3uSO+mirMdIdEmv7EyVFgKXxuUASpke/W6itUuavYy6HfxCoZ4lr3Wq9QwIbPIJgh0GUO9SuUZvrJhHnWCAdMFKTBCNNpLktibebdFJLsc1CCXBpiZ+4AKrwjyzHUZ3HcCNDAWMxg5QU2CRh7mq1DE2BqmFUybNldbhYulr8Pvs7gPd4wb05xa2J5gBrZwZOBSSH6KKZ4pSCPw0gJx4RrmV9KunEwktuY4BHiyE96dr1hf/s7GuE/gM729ywVn4JT+p5xQTQOte+M0oakqLY/tT8ndmG8K8+6ZmAs91gGLsM9pPyW3t4CTZcXAFgT3stGyuH7jvAMQlfuGkyC6yao81LzcJgjpQu+RLsPPvE8IsZFKoeaPvJmmz8YHN3rSIn9YYb7w63t39SiZRPVBUf5HH7msLmCnX1yimaHfzYga6wPGNRH3MKiThc3lbBLo4pD3IgdEXxzS1f6Z17KC5xy98uf7rccC42flHKNEVreZ7aS8qO6e4ksXl6PUVcTMJDj3pOoEPR5QQkqcw4ndj9qfDldJXlUPwqH+dzakw2xM/CQIpWXHWLUlMB0ytFdTm5vLnVaWwIdbOddbvaYzlwq67sqhJ4HGZmdB4ktjgWST2xqIefZt4Cf//ahi2V43H2fhmBXHnIYL6s2Mg7l5ykWQ+s5eqYJ1UQJH23QLfsDBjkfVVGcGpYYzYawamBVmgs8lJpvxNIEMIx4FpJlBdreQXDbMtfCW8BeHerHcnYibqIpb5xPCuq0XSGehLaPzaRQF/53dkag7kVKUGi+0CDi7WZ/vLIL6UCEAPrT2chNofPebucKJ2v+xd9fBuDVoAc5GQzd+NcIeIktrjLhsutDr+IJRn0RhvXrMzqKjaD/JhRRPBIWpSD+uX3mFwsXmw2UpOSarf71l+7A6Zpfl8NUE5fJ3qP3fAmnSgfQpktB2IPDNf/Hlf+pBV9N31HxbvK/F7EJmzUhmF1niQKhP4fjWFzhbQHDhrgYIVqdea42Js8EF+niNzhm/tGp0LZdiVfYxsRP4Tu+0CU6B8UimBUfYlN6pkjE1k7LI8Uk9OrSJTE2cMbARCqVBggLHQOk4Ph7ZjeSYWzAC1+/zlq3QI6Mb/BK59pMbb7ZZ3VjzrEapqCtLd3Q3bSwBv08lNra7G75NE2Bih993THY1mXwg8GPwCFg5RAu0lCP+e4brO3gYONL98WY91fHJloJO95gVLV52wse2m2pmOmDfQICaPoI5zG8K33SZHlfaoQfGOqrCEBXBfg8VeZHCC53xE6mIytxJYgUXRNGOQ9+tR4zdAGDlDNg5DXERHQrLIqkNomaU7XDN8FIdnkenctwIeCSvuKJZXYtWI9K76zK6ibcSQ/OBfSrhRkpLu8n8mcdUCaXvss1fvpzoBwx/uFGqgbjRGC5IlKJ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01a95472-c511-40b8-c911-08db4a6e5035 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:05.7623 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: D73iNRCgZHLfufA6CWjU3R3w34/+U7G6PDS/JTyXOJ36b9dK/77NiFQaUwEm59QX X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What tegra-smmu does during tegra_smmu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/tegra-smmu.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1cbf063ccf147a..153ea0b5de8db4 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -511,23 +511,39 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, return err; } -static void tegra_smmu_set_platform_dma(struct device *dev) +static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu_as *as = to_smmu_as(domain); - struct tegra_smmu *smmu = as->smmu; + struct tegra_smmu_as *as; + struct tegra_smmu *smmu; unsigned int index; if (!fwspec) - return; + return -ENODEV; + if (domain == identity_domain || !domain) + return 0; + + as = to_smmu_as(domain); + smmu = as->smmu; for (index = 0; index < fwspec->num_ids; index++) { tegra_smmu_disable(smmu, fwspec->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } + return 0; } +static struct iommu_domain_ops tegra_smmu_identity_ops = { + .attach_dev = tegra_smmu_identity_attach, +}; + +static struct iommu_domain tegra_smmu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &tegra_smmu_identity_ops, +}; + static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, u32 value) { @@ -963,10 +979,10 @@ static int tegra_smmu_of_xlate(struct device *dev, } static const struct iommu_ops tegra_smmu_ops = { + .identity_domain = &tegra_smmu_identity_domain, .domain_alloc = tegra_smmu_domain_alloc, .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, - .set_platform_dma_ops = tegra_smmu_set_platform_dma, .of_xlate = tegra_smmu_of_xlate, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Mon May 1 18:02:52 2023 Content-Type: text/plain; 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This is needed for some device quirk. The correct way to do this is to support IDENTITY domains and use ops->def_domain_type() to return IOMMU_DOMAIN_IDENTITY for only the quirky devices. Add support for IOMMU_DOMAIN_DMA and force IOMMU_DOMAIN_IDENTITY mode for everything so no behavior changes. Signed-off-by: Jason Gunthorpe --- drivers/iommu/tegra-smmu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 153ea0b5de8db4..7c301a732db2c0 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -276,7 +276,7 @@ static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) { struct tegra_smmu_as *as; - if (type != IOMMU_DOMAIN_UNMANAGED) + if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) return NULL; as = kzalloc(sizeof(*as), GFP_KERNEL); @@ -979,6 +979,12 @@ static int tegra_smmu_of_xlate(struct device *dev, } static const struct iommu_ops tegra_smmu_ops = { + /* + * FIXME: For now we want to run all translation in IDENTITY mode, + * better would be to have a def_domain_type op do this for just the + * quirky device. + */ + .default_domain = &tegra_smmu_identity_domain, .identity_domain = &tegra_smmu_identity_domain, .domain_alloc = tegra_smmu_domain_alloc, .probe_device = tegra_smmu_probe_device, From patchwork Mon May 1 18:02:53 2023 Content-Type: text/plain; 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Mon, 1 May 2023 18:03:12 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:12 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 09/20] iommu/omap: Implement an IDENTITY domain Date: Mon, 1 May 2023 15:02:53 -0300 Message-Id: <9-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BL0PR03CA0002.namprd03.prod.outlook.com (2603:10b6:208:2d::15) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: ad9c7fd9-57bc-4c69-16ad-08db4a6e5111 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0OxQkhjMER0GI8R+xrs4r9TGwez+N2ImFM6XhLVnC+SNLtLQszp7hxLRqSCSU8I5b5VtJeNSQFfDAoJWAqTXEg/71mAmiAj65yj0ekDpIsmuayzHTavGiFtf73rA61l9atiNjnkARt3tzvXGNUpj7wDMhjD7A/UHQYLpc5ZttQvDEAsT1q4ek3ZsyAPCE79bbrFnyGObxg8hQ92WyfH4NzkReqiU3ZNkCwbsF8qkUuflX+WHD+uWsT01rQyPn+IcIeHm42RBKUNsZWNKEB8CfUFv1gGmD87nXvJ8BsarwpZOsCiDMDmgmGpYJrCm2goGSLE4MjnG6ZutAKIs5bUZmoHgKBtqYzyzXxR7Lka057anUOxil41yaOKFHAH0405SMFgx4NdPKT4w5sVrdVGB9C2MMdsTTWqUpSgHow24+H20OO+rX1X/Nodb0QTd9PLR3cNVFSJaKJhA4cxPKpqC+/x4LFYWTpeRMsuiPyHnVLhAhiT+vn/mFzRwzjcZWzd09XFjLnxU3YL1+S96l8H4G4Xec3m7DIQ6UCBnc0Y6eNuEbUvelr23cVelMUeLiagfCiKlb0skb1Jus8I6cs6c2dFLVam5yw4ELt35gJp5KT+iNpjzBiOE5RwQ4Dw0F9GZV+4pINsZIvFLaf77gEUVg/dKAoOcxoZFp1ZO3eXu8Z8K8ETqf+Sdd+XUIrllL0iB2vncImrUuwSKHm9Zjmh6kW1FNu+78BCNAf7kYEmmXxebQ2yTtJbYwpEDpod8Y65oW1cmL99UNlaj4/U61R263eNj0etCTRG/VGNDR5lBf0F5MAfIl8BHgi96Vnnp1OmZSO+as2cKaP80w3Bl6gtEafQNSSlWQ8tLh/YpLtDMuNNVDNWgc5QdVn9djLuFgUya1ap8ZyEkAAFjiUiGYgX8U0um86577enBCodRknWBLIDsB+mEBgenyerMRg+Vn+UZQ2oXJtm7yHX5i48mzpSzdJr5gKHNZyQe38Wourrnt4xfhjOM+Untu92vFLg0Mk94HtcM3dpIBX0udFxcLKqj+Gqyus5aOzTZEIL2HLr63cY2++INavvbFgP6sqkA5BHlE3QmfcncE48YFUKIGxwKaF9dXr8e0iQwm5CmMfSv+c3nK4izAwMSJ4BRvfeOyiF51ueYN/FuuTTPJ8e75N/WtVVIcPoWkRDB/0AE5dLZWCvJH9tcJWTZPuVzRtL3e/ETZEYaYuiOIQuDK8LDTFQhNlB2yVIhBB1vVz7UmgM+yCMEL53OALwQnh5I2eHyDij9pQcoayoFeYdEaIC3j+loNoHLI+vKVo2BEj6DZCNGtVQGt5M56UTNeYfi8zHFUviS0YjJY6t9eAHeOLMQvkZNKJExXyRh61Fjryn8dar+7bSBzcRJRQUFxk7XHRU0y86wC1ITXg7N4lPolB6OlJ2PylQDY3dTJzVbCgbdXO/h2ZKSsTefhwXIzXRM3phIqE89NVv8Cc3vOhdhQIeUYhPeCRTbEJRjFhFvTxb9MmnKyU7aqIO+vWCZoqd7in2Y3FAHqXdUrK6KCsRqQLjsPDdCeG7AvLPsqQuLtnHzfrdYrCdE5OJJuCf4d0W2x3ZbKDXh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ad9c7fd9-57bc-4c69-16ad-08db4a6e5111 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:07.2131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bsvS5XFLLaxuDyv6zvIk0PbV9Vgv6wrZE8pc2GNi4iEAG+vkqekq291Stzt0/V2f X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev, From patchwork Mon May 1 18:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78FD1C7EE31 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FQNmff7oegrYmGhtZQDxqlJN98giwvvrsHR/6nIJ6+8F3YUJyUkiGCGYvxBmpVzYfLCKDLjL6n7ZQiQcOA336OCUTJWTJBtSXWXAH3az3A/h7ZoKrp/4IA2RIlwC/eOfPuRHnHLXH13tOe/R4LBRMFr/gwavY7r3Jsq5QZV6BKh/tZR1xPu8A1GRnyfne6BvkMzSrH6TrG+5PcaalcpQQyaohDpwrgdMDl6kkT07JpAuFlg+IGYoV9SYUwdLSjsmWRpO/QP6ntvkjJYZZIKya5+KYcMsScf+qAufPY/3PLzR7uxSRICT+BshbrGUhfhNXuMwwb8EbYI+xn4aBSV5vgGqjt4dIbilz10eBsXS2iZSu4WT6zaLuvwI/4OqDMjsyl/MFRvcS9m5Pu2InYkhPbEC08ZFWAW7ZKu0sMHci9u4+kzBOq23ruwweOTaIqH30UdeSKotWoSN5yIu1yoBgrMDhfXiZdRCOXY8lY3nDWTkZ5k/TYVABI6hrndRj+9y8tbb0cGoPk3av6KtcvVFAZArvk7nxT/A3xEKpDYmWOf7mG+eRjd4vGLvsuZWvFfqPHZTe0yYt3azynJUsczFo4OaQ5LHAylZPWFnfhjcNZTkrBAZBe3VV7cBboViv3eHdzbddapaNVW+3qpIYbcoC9l2ZD0YdzH7kPoFyl0KQKgVl0iQqSV8XHh5hr6HENAQbh1v4H2XN3oa73K5344bOuiTY4NeWez2RZkcG44ngQ25r+mxTr+sEypeNlTCN0CcG/K5YwNDI5m1h/QWFSSkQ2BbT7IFfOYkuBAO35TLtTugf+5wmP+XhuJehQkWV/m7rBymm3WlaXDRBOg0GWspTKUMdyTseG4/nggpdGXTCuKfHIRKUau6241EgfGqhT9FMkKCJtVqqZiYvsD3VIjgeQi3qAa74jVs/CoNMqUdp0YQVpVJzCnN2YrxvAyWuBzJRClgG6IUC7Xx39AZtQJgJjygmx7HO1vYTvV7/o1FLWvarjOgqe9C9VXV9N+Yv529uQYEV+2wBwUkxOLdsEgOa+QuPgWPimJtGkoXQertwMpV30V7eTiHWD5Levw5KNBuY0Qk3wFTooRzWrR+Ts2JpZEQ3rrHLEPy0N4LQd6DpJMlLFKUtCtGY+LutwhEmTiztiad3LUOJlby0o3vz74JuNJ5xdbZF/3N9iz+M3R2eEBsXPbpkIjJ1VwStroulCaQvcTe9SU8n6Vy+4d+SUQmfPvFmXA1g3gukwnS2LVBxUgde2BkBhbtUCc/deFsjaoU8MkoWfA9m/j3zyAS7mmMtkzdJSbBV+rokiBSxzeDmb0Dool1Cx16lecUYUCeIuaGX3Yif98H4GESvlhMlmS+42zYK3it3GQhwzXKYVqwYrm7QliQKJmO2X3qNQrElwrvB4N0WPnAqxWFlS8u/iqekzgqva5aWpV/wjKjdJHXo0leKkuz70Q8/OMieJe86rtk8Bc5g2L1yKoY+ibFv/1Mnw70CnEl1qP0x3tqWLuw5B1NkySxFC8jJzMLYjScWWnmB6ix1dQzzs75nRYLoqczz6Hpaol0S0ccomGR2H2Dk9egzlXZRT5geQw9VbpeSvF4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0776e807-fdf6-4860-90eb-08db4a6e51b5 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:08.2523 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vmnF2sshWowAAokRi4Z10m6zbZaDdeicdqlEndGwSksZN1HnQbIn5+05WvDRyRxr X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What msm does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + + if (domain == identity_domain || !domain) + return 0; + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Mon May 1 18:02:55 2023 Content-Type: text/plain; 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Mon, 1 May 2023 18:03:08 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:08 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 11/20] iommu/mtk_iommu_v1: Implement an IDENTITY domain Date: Mon, 1 May 2023 15:02:55 -0300 Message-Id: <11-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR06CA0003.namprd06.prod.outlook.com (2603:10b6:208:23d::8) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: 68106567-da74-44df-e6ee-08db4a6e5099 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uRFDvNR8y/PieFFIPKBztZRI2Dr+RtDnfPNy4KwiFbPyJRDY3BgPKSAG0JEzJvberGczuRc/12cfTXSYMaEJPuZ4JQG8vuOU/6+7AmobsLgNcxJY38TWpGi87XfU8NxmO8+pXtkuM8g+LggR7ks7hPjH7E8eUm/xA+53QD8EvhksGjkNlq1M6p4BV/9T/araExVGRflmJNh5j1854JR5/31MnAGS3auFfHrStIp6UKffRUu/ZL7xhiAMA1wcD2sx7fhqiye+EUoV3/8Vp6L/Sk2PvXmi4Eh6jQ9U/fct68M3z4hywtTYCy0yOCCF1Ro2844uJ+ZICsaB5cYc9+29VfPGRls3pozOnDuiEnvIvAdytVJlSwpCYpQp13YidwJSCHAC3lgWNu5aWV7/Hn3KkWsTNY5sxchCn+BiBIACWIqGA+V2yHmrgx/WO7YkKc77UllVlmct7R17eva5roVcIARPGERSqvdgRZsqhoNP8mQkNjlE+iXw2sm3goa0yXrS0a2l9n8sjPX9j2z2bRrgE6ry6ZKfu+3Uc3FZFNXhRGmWaNf22wRZ3Jl+473iEVPtcNaaglMZ55T/UKKBDdPSquz+hr9t9H0gDW/2XDtfsq7SveXxs3ESSQWpgLQzTqjy6KPu6bhzZuKFHnG4fkkhW44giK8U2vj1RFdeqbl3T7cp44evM2dd9WyVhSI7UO3O29GqjVtCWsNxu9In5BCc+BRQmbYlrXRpZDpxP+Z5MmbrKuiE2AHzrGCektQMGmLejYWwldxy3MSoquIR8XODJNPvNDQNwlL5qlW+fjNChXrY5TJI5Y5miYHvH65DLG297gva+bMj2WxbEOgVJJJpXdqpLAfwgZlG4ivBpdGzd9UTBDMEd+fOyNbH0u4DgoSYrN8AZgdZZDzLNYkavrzIWsDKkKfRvLfaQoq0b1kf68LhwA0/Si6PtKAcEvbDnGhB5ghm84P/U9Tpld28Yv86ZCpdg1ouUlbmwZBu8ph2cvCqLR0Sf0vgYOQBVLyoe4RgX0jxP26+qEIMTl5vHi8kBGcVgqVO1uQEjbESQ1uwlHeCwOftX8frVfN28/8HTEzUT3IZio0Q06KhwOawM1TuEZaOq0g7NYAF/yO8QKz/v+y5E5Bx0PXGMF/NXJauRvDaYCU95gYZztI+y1X8b4bL0jA7NE0rNhQl4nZ7Thz72bMqLFNsdUBh0NrJAPWkXUXrb0MpEk2nbXowGqAHSWrjKxS/ymchnDZDNSWlJGC/N9BU4G52Z6M2K/O7RMu9pU1zPQrETJCuItQtdxsOhxLoyytQ7PboMd4AiswB8kLVLpRWbzMvty/2VS/1DZGdmRCL0nILBdGJnGqZufX+Fkdr1mNb/XBTREiTAX/dgBJQgC8zrYxFRYl2yjRI2/CPeE86PCOZXq46maxgm6xmB+dKubhWxZD4IHlS1lDcWix275WaLzcpWlnmbJchnyj+Q5C0rxd4oqaEn16JIrg6Zc5j35chYdSady0/okHXgzmvXExwyVkkaNDXhIFDK4R8ZM5xoN71NIB0H1qxaH+mQpDnUouxQJ20pUsQDXzvY0xEVti/Nymkv0BhBF93GdFVjfIU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 68106567-da74-44df-e6ee-08db4a6e5099 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.4239 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JpPVw/Hgm008N4FfTXbQRQg3nHbgrpCqOdEwTJX2pBndTeoKmrW+PUGFHZFH2zeB X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What mtk does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Remove the mtk_iommu_v1_def_domain_type() hack, commit 8bbe13f52cb7 ("iommu/mediatek-v1: Add def_domain_type") explains this was needed to allow probe_finalize() to be called, but now the IDENTITY domain will do the same job. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu_v1.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index 8a0a5e5d049f4a..7c0c1d50df5f75 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -319,13 +319,24 @@ static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device return 0; } -static void mtk_iommu_v1_set_platform_dma(struct device *dev) +static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); mtk_iommu_v1_config(data, dev, false); + return 0; } +static struct iommu_domain_ops mtk_iommu_v1_identity_ops = { + .attach_dev = mtk_iommu_v1_identity_attach, +}; + +static struct iommu_domain mtk_iommu_v1_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &mtk_iommu_v1_identity_ops, +}; + static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -441,11 +452,6 @@ static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_arg return 0; } -static int mtk_iommu_v1_def_domain_type(struct device *dev) -{ - return IOMMU_DOMAIN_UNMANAGED; -} - static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) { struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); @@ -578,14 +584,13 @@ static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) } static const struct iommu_ops mtk_iommu_v1_ops = { + .identity_domain = &mtk_iommu_v1_identity_domain, .domain_alloc = mtk_iommu_v1_domain_alloc, .probe_device = mtk_iommu_v1_probe_device, .probe_finalize = mtk_iommu_v1_probe_finalize, .release_device = mtk_iommu_v1_release_device, - .def_domain_type = mtk_iommu_v1_def_domain_type, .device_group = generic_device_group, .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE, - .set_platform_dma_ops = mtk_iommu_v1_set_platform_dma, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = mtk_iommu_v1_attach_device, From patchwork Mon May 1 18:02:56 2023 Content-Type: text/plain; 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Mon, 1 May 2023 18:03:09 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:09 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 12/20] iommu: Remove ops->set_platform_dma_ops() Date: Mon, 1 May 2023 15:02:56 -0300 Message-Id: <12-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR18CA0004.namprd18.prod.outlook.com (2603:10b6:208:23c::9) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: 0330491c-24e7-4606-f8c7-08db4a6e50ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4WwY7KW3VyQPEyTxePSl5gzejCoVliLqzFD35fJIcrakZKmJslTAqyKYfzD9PXrJ1BRNUqc38GaeHaLMuZ6t2CTJh5prnUkPxbQTm1+FSynzWDrUwDSE4Cf3x0iqHVXiHIwStmR26Y+m+uWMdsx1RYbTejxpuf83HRHRvEWzgaszxXYxduHw5m88oIi+k6J2qTBdnFNJKko5C40BVk5udddruJi7B8o2EtVaAD/L9xDizFSA2do7vcL3wmgp4L9dr+f0XlatcgVnYlsVwMD9esCoFsPwE4CwsdkmFL9Ev25AVx2JDKtjQ88toCVS/v+RBkOCcdb9TiTkMXOruf4SOyMyozERnxNy3JV6by6t5y8lBp2tVdXEqX3xc9jV5U4gV7tln0+Zlculqs607wRAdN19oAA11SwoK8egM+3JXQhryv4APZ3ztgMtKI+e/nOiNYHqL2QMB3RmHQG9vcHEBiJ+6TbWIHZjD4mr2Y3+R9NMTyhDoZVXNXRvND/InMYB2R6fhPvLkrwEhYXhErDy6M5w9+k0BS2eM1RiNFdLGb4an3ObIeUvido/HWe/W/imdfndMXho/23q++YHoKY3R1M0OigvXLwIiiWz0fTm4BpTFJibmhzJW9DKH6CYRUPlnsvXAuKApB7HAA9MtkPA+nYEyvD40YzdvCaGX2hkoqtw7zycpITyk4kXrzHKk68sNwlqokVkT0Flh5jBWTErQtQQz/G8zxRcnHwzHe6dDz/0iXCn+fGskkOT5Zabr/J7l1cOL4kpKADuPgNx80Ftv8hT3D9A8McEwZP7oCepG4D5gCh4V69l5dd03AhnmanRZZSnGjnKeNgb2sIlr/KVzWoB2dxnxkaByyNDF7UzA39Ld/v7PuviNkgRPqxDBhwrnZUKAHsMvGQpiv6mnM0W0IDWw6Y97EcFcF7LVKLgssGxmES/MmNc24d4+9+cphpYXK3l2tefnObdBV3P2M8bQxmE837uMJ9xmkNcNf1HTqbuCyGFGbSeqsJLu6lyMIG2tdvkE8cunqm/CYqEctzMDOX+S47fNxc1GiUOJAXlvpoH/w5Tp+/SmpEUMLqzeND60w7qD6Z9DQvGhcXIvnkll+e4Wea7sDJ0MQW2eSeBXG+nl7MEvt9Bq9PBWtzA4Tkwq2Ruw9m8w5qqUCrPyh8uBdrsXwPSfbS47e+WRW1Mor1OZQrfNCj2BCpj0nqANQpTxHvgUnaKLKP0UR3CN8moFzcSva413yUtx/F6ZHV4c64Yluwy/KDuAgCdTtDAHZcRXZexP4Mm3GrS6fKD5DXxTMz+QGYlQ2flx0A3N7ha22qFd/7l0kjExs0TnOhmYYHypkqVxkasRAMxPJvdSlr2NILOL09x+YHukYcHIcmriKfUTvjFCrceKayaH2FFro53p8l3l2FnQitoudC4Vcofku5sZ8ja7MT71do6vVPPioAN1mF7unFtIx/cwLw9oHiAAu59p/dpyLnlEJ+P53x24/9SlHrTHjBeHlelyqS5yUEpO5JN4KqmfckMNgxAHC859IDkbR8wfrvTWAlkCApnfKyiMTf8l+mABI6rrdwzHSRqO/HID6PvSggK6DIUepJR X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0330491c-24e7-4606-f8c7-08db4a6e50ac X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.5986 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SqJTt/RS2dCX0CvQsUhv2AQwRJuN5JzXnvMITii6Q2w3m2c76Vh4+3Q4Koi4hKCz X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All drivers are now using IDENTITY or PLATFORM domains for what this did, we can remove it now. It is no longer possible to attach to a NULL domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 30 +++++------------------------- include/linux/iommu.h | 4 ---- 2 files changed, 5 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 8b9af774de68f1..fb646765a87f47 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2192,21 +2192,8 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, if (group->domain == new_domain) return 0; - /* - * New drivers should support default domains, so set_platform_dma() - * op will never be called. Otherwise the NULL domain represents some - * platform specific behavior. - */ - if (!new_domain) { - for_each_group_device(group, gdev) { - const struct iommu_ops *ops = dev_iommu_ops(gdev->dev); - - if (!WARN_ON(!ops->set_platform_dma_ops)) - ops->set_platform_dma_ops(gdev->dev); - } - group->domain = NULL; - return 0; - } + if (WARN_ON(!new_domain)) + return -EINVAL; /* * Changing the domain is done by calling attach_dev() on the new @@ -2242,19 +2229,15 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, */ last_gdev = gdev; for_each_group_device(group, gdev) { - const struct iommu_ops *ops = dev_iommu_ops(gdev->dev); - /* - * If set_platform_dma_ops is not present a NULL domain can - * happen only for first probe, in which case we leave - * group->domain as NULL and let release clean everything up. + * A NULL domain can happen only for first probe, in which case + * we leave group->domain as NULL and let release clean + * everything up. */ if (group->domain) WARN_ON(__iommu_device_set_domain( group, gdev->dev, group->domain, IOMMU_SET_DOMAIN_MUST_SUCCEED)); - else if (ops->set_platform_dma_ops) - ops->set_platform_dma_ops(gdev->dev); if (gdev == last_gdev) break; } @@ -2868,9 +2851,6 @@ static int iommu_setup_default_domain(struct iommu_group *group, /* * There are still some drivers which don't support default domains, so * we ignore the failure and leave group->default_domain NULL. - * - * We assume that the iommu driver starts up the device in - * 'set_platform_dma_ops' mode if it does not support default domains. */ dom = iommu_group_alloc_default_domain(group, req_type); if (!dom) { diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 427490b5736d40..f6a28ab78e607e 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -231,9 +231,6 @@ struct iommu_iotlb_gather { * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU * group and attached to the groups domain - * @set_platform_dma_ops: Returning control back to the platform DMA ops. This op - * is to support old IOMMU drivers, new drivers should use - * default domains, and the common IOMMU DMA ops. * @device_group: find iommu group for a particular device * @get_resv_regions: Request list of reserved regions for a device * @of_xlate: add OF master IDs to iommu grouping @@ -265,7 +262,6 @@ struct iommu_ops { struct iommu_device *(*probe_device)(struct device *dev); void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); - void (*set_platform_dma_ops)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); /* Request/Free a list of reserved regions for a device */ From patchwork Mon May 1 18:02:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87275C7EE25 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /vsla8e1UwW1PBtoIivR+37vOso/6C4i42cHj6Ns8b3XFRtdaSy7x31OsbTRxV4XDI/vb+SDATLb1bzFniUWX6cQ6k2eFM1IFdL4FovHyKQT17m2jX6jyLUl4myfbG7jj43joCdp1y8scKwS/DobOdaqancyWCxVr8Z6Yxe4SDQd3LNvLAXL0eihNZ663IFvY8s6gAW+37B1LINeMU/jrGmnq2Xjy0HSbwcpsON+ZreGfehMUkpBV2cfUyFBrV5Hj07XJz07CHHuYgX2BLFBo6/BTK1m0OOcuSaulQ487quMDk/Abl+jUZ5bv3+CykoujIb3v5D8aSudi6Uu5H2XyBUDAhfYSKD5Kg39NQzimhDyzJOEh/6htJ65PuCewQo6Nu3yEb8TodzpXhhynnKEQnSbFfMZHNL9SlHAn3Er8OWnueM0ywIURIEICI4foIHd6BjebQXL0H2umTfFzlOkkqhNHYO20R3aljBJ9LSSiMTe8+8wCTWNy5SqZ4DvrNYtRKZJ98HdppPLZJhvlmXDIccoHVaSvuezwJPp9D33xfbpvpP2/00O0qURyxevaKlMQhHudH8jFOg1xAVVD3ovpyOMACYyx8MrohqgYMhpm8pEbVAca4cO7htGU59KMX03ZlgTLX/CN5RsHq+kVDAJJ1vnmsgUkaONqTuNOicHPwjiX988Kwk54QNIw3DhzpYk2v6qPSa20Q0gXi+sWsoHW1w88Z2/GtTQ611vapBti6oXS1Vj9LkLSqIkcYXja321GZOkIDWGzKEubFNr/AEMPRGbtEIoA+ptqVx7TJQlmA1w6qh1j8OtGtzgFOZNPLofMjtTE8FmKDx8aX+6r5MQ6sKKD3Dn+Vne06DsnwSr0+T80hiUXNrA61q7Gmp85VY1kWNi2An5cgSzIFB/uKpAGsvlWITmlshK+mqROWHbKAqiFdKMlJst7T9hTNSxHfVZPQ57z1PxYbPMTqK+D89Eibu1K6X1C4tKwln3Is0qy5/+y16yrIUG6McWPW4yJqEiy2L4FBY4SVFImxP4f8mUJLUpF45VZZPajsPR5+ij4YdIbcPuBeR+UnE6pcWzGbe0LmnBxV1i7C2k0E61eyA/f/hHz5fsjHOliSZcJV3e10muAkS8NHOyrib3NqROm05CtO2srvCkbzBYp7bRJVscLZS4EXcwVyM8BvFPRffEF+TL0kyTiXEWBYNFg/B4UAIb6ZiNzmFn60AWfTJDpsGBg3MqeknHKQeA5rs55zwU6c+Zl+op/Iw9yue0Je7DjstdH1dQQ+CAQlfDSovObJRi6vUpkW3GW10IFeuhbOdk4PssrGg0y7xN+pKWh2vQAhSnu9YE3xDSq91AK2NEJ5idEDzNdVyMhxSTVb0cxetnmAN7A5xGaAcDKX3RgdYzPqr5Y+LbBwcu+Ag1XSQevZyx6vctEebkv5Kqd/ZM2XYr90jQyt2ZzQrE6xRTt4mBso0pNQdQJljPA1htkQuJCOSI8HvN+FH9PGE4o/8PTHfM2DbcABDYXkrSReoMWVHiSrOYEw4eS2fJUCbnXavOXUg1fLWdtvn95DhRSfkxCI6pi9maFi8yLYIaycY8Pf+mKqNv X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5bfd9e18-b39c-4da5-3731-08db4a6e5089 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.3199 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DVKATbYQwt3+IRzWa91UrikQMlWqcRcUoGrGJ33wsZFdHsndr/i8HJNYis6kOV3+ X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This brings back the ops->detach_dev() code that commit 1b932ceddd19 ("iommu: Remove detach_dev callbacks") deleted and turns it into an IDENTITY domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 39 +++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index a503ed758ec302..9d7b9d8b4386d4 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -387,6 +387,44 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev return 0; } +static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) +{ + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + struct qcom_iommu_domain *qcom_domain; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); + unsigned int i; + + if (domain == identity_domain || !domain) + return 0; + + qcom_domain = to_qcom_iommu_domain(domain); + if (WARN_ON(!qcom_domain->iommu)) + return -EINVAL; + + pm_runtime_get_sync(qcom_iommu->dev); + for (i = 0; i < fwspec->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + + /* Disable the context bank: */ + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + + ctx->domain = NULL; + } + pm_runtime_put_sync(qcom_iommu->dev); + return 0; +} + +static struct iommu_domain_ops qcom_iommu_identity_ops = { + .attach_dev = qcom_iommu_identity_attach, +}; + +static struct iommu_domain qcom_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &qcom_iommu_identity_ops, +}; + static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -553,6 +591,7 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) } static const struct iommu_ops qcom_iommu_ops = { + .identity_domain = &qcom_iommu_identity_domain, .capable = qcom_iommu_capable, .domain_alloc = qcom_iommu_domain_alloc, .probe_device = qcom_iommu_probe_device, From patchwork Mon May 1 18:02:58 2023 Content-Type: text/plain; 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Also reverts commit 584d334b1393 ("iommu/ipmmu-vmsa: Remove ipmmu_utlb_disable()") Signed-off-by: Jason Gunthorpe --- drivers/iommu/ipmmu-vmsa.c | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 9f64c5c9f5b90a..de958e411a92e0 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -298,6 +298,18 @@ static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, mmu->utlb_ctx[utlb] = domain->context_id; } +/* + * Disable MMU translation for the microTLB. + */ +static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, + unsigned int utlb) +{ + struct ipmmu_vmsa_device *mmu = domain->mmu; + + ipmmu_imuctr_write(mmu, utlb, 0); + mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; +} + static void ipmmu_tlb_flush_all(void *cookie) { struct ipmmu_vmsa_domain *domain = cookie; @@ -630,6 +642,36 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, return 0; } +static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) +{ + struct iommu_domain *io_domain = iommu_get_domain_for_dev(dev); + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct ipmmu_vmsa_domain *domain; + unsigned int i; + + if (io_domain == identity_domain || !io_domain) + return 0; + + domain = to_vmsa_domain(io_domain); + for (i = 0; i < fwspec->num_ids; ++i) + ipmmu_utlb_disable(domain, fwspec->ids[i]); + + /* + * TODO: Optimize by disabling the context when no device is attached. + */ + return 0; +} + +static struct iommu_domain_ops ipmmu_iommu_identity_ops = { + .attach_dev = ipmmu_iommu_identity_attach, +}; + +static struct iommu_domain ipmmu_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &ipmmu_iommu_identity_ops, +}; + static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, phys_addr_t paddr, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -848,6 +890,7 @@ static struct iommu_group *ipmmu_find_group(struct device *dev) } static const struct iommu_ops ipmmu_ops = { + .identity_domain = &ipmmu_iommu_identity_domain, .domain_alloc = ipmmu_domain_alloc, .probe_device = ipmmu_probe_device, .release_device = ipmmu_release_device, From patchwork Mon May 1 18:02:59 2023 Content-Type: text/plain; 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Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index aecc7d154f28ee..e4b9f728002403 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -753,6 +753,28 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, return ret; } +static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) +{ + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + + if (domain == identity_domain || !domain) + return 0; + + mtk_iommu_config(data, dev, false, 0); + return 0; +} + +static struct iommu_domain_ops mtk_iommu_identity_ops = { + .attach_dev = mtk_iommu_identity_attach, +}; + +static struct iommu_domain mtk_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &mtk_iommu_identity_ops, +}; + static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -971,6 +993,7 @@ static void mtk_iommu_get_resv_regions(struct device *dev, } static const struct iommu_ops mtk_iommu_ops = { + .identity_domain = &mtk_iommu_identity_domain, .domain_alloc = mtk_iommu_domain_alloc, .probe_device = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, From patchwork Mon May 1 18:03:00 2023 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tF5tcXscjLgH79dYnfpvwZgjdz8i5v9K7+yNa6DW5rAroFsyApssQuX7PhUqriIKWzjiorodDoVaJOSO086lcAj5SNLeOdN+9h2nLxoLvOq5XQCbiEy/3aEBp4iwH22IzkjBX586Pi6ocXiFTlzIaocs7wAghjmk++YRu7f6YjE/y4Bdygf27gW+DR2mYdFF88joJ1CvE8BffP3kC063Y2zh4m0beTLkATtK8POjcv2PnCgHSpVil8Ubj2eXPwZPo5dL8F5JL6+2/I7g2ILhWrGDUv3zrXioUJ4TBRcAMpCquoxxilMNiFSCOQWNQSfLu8RJNGu1uOQI6huEEPFAB3QvSCWtzYa81Ur2j+8dmtGQB3ISVBoxwKwzkH2VwL8DXuO5acpYWbbc3NOwrJz0MKvpLFuPAxkNrwAAqeeT1I6ZaLgIcB59MV8ExWjW6XRG9P67rCHdysN411RCdQJjHfmFcYl9DzFsA67cW9iWIid2y/sPTOTWS427w/OOC5eUxpwUoLAfsy5i+f0oK+zBLDaSPWm6/7xkE34oTSUIQdAmFkL7Z1bbvtJrMb0L+9qwT4MyeeTf0IIQ6FB8qaRsdTBEj0FgOo1axXowzyXUykvs4sFIjgOgO5ID8S41LQPDj1aNI9E1e/puMULzHAjty8YI7I/1I3dzgJhYuhWVYGM8+ZdVd8ATp2QtloqId+FbmkqKgiQmypq4wfe1b+bGdjXdwAcG0d+7d1PfK2vSHBvhc14VWIYhgq2uAnk1f6VrR1uaYi38dAoPkzGDXJDDy/MjzbWGuLSPU6l33pybjn0HA4cxNd7m3wJ6eFHLHpO1xOsiramYEvdO3ZIYY3Kidb722EMqj15zSAyN7WeAuLJvKsvXt+utusXiCutoBoKztys921ru6rMNIK7dgwySsLigjkf1Qf/+yP4dcn8aH8G8nuVe0Npgl1wJidrBiNEw1tE9bHcEosa4jem2krWZw55i44i1GBPHbvjczgBN3sX6JvsrLMVR5VFvlKlgy3680CDyb4iLkzYft4qnWackgLIYUBM1NnM+XGYVm2ue7oq4jLxmJQfAK0+ZdRwwxKYwZNIztnGgq76blT1/Cku33cCgZh33HXEk/BK74gEVejQMa3wFwxCjdOibt2vN9KHRO9i9moJyCKNXPy3xk1KQuCKRA72dzJi+xjzsTL1kI29X61lMlciabu73/jC+dcDsnYRKXe13IReCZs5yE2QGhRnNbQme5oBUJCEeY05/cLFsbLC/YLvVDtDmlL7QJxBDmrEvhuMGJlO0V3EONCFe8yZU+sBKd8/32r68wXvXNoa23U4GTjT88OPPn+X5Tu6pzn/PPw34sYV43iuHCUQA1jApgnkzEPJ3eCX22Fk7SepUkkhoQh9lRmm8fxaf+9Q9g1ieQzNJx3Cz0lzCs4mIisAi/2S58l8p0p5gPVw4D7CIOF/91bUjc06tt3b6wGDkaQ/8gnd1NGrEMnPtfR17bMXU2RSlhEASa7L9Xm5UQdN8jQzCpvOi4Qq2cXgCg2kNpKGFkQHioOmEsM7Yp3UgqbN0XYramJGTxHAZ/J00VTtI/JjqMVvYi+Pbr4Hzreda X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2a4153af-b8d6-478f-7ebe-08db4a6e50d5 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:06.8138 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9QdpPvODeB9lqC5SbDgoXdAphJ9eygw24UQ4DHBn3L7znTILaOb23+CSAzTiDxv/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This brings back the ops->detach_dev() code that commit 1b932ceddd19 ("iommu: Remove detach_dev callbacks") deleted and turns it into an IDENTITY domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sun50i-iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 74c5cb93e90027..15fd62d360778f 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -772,6 +772,26 @@ static void sun50i_iommu_detach_device(struct iommu_domain *domain, sun50i_iommu_detach_domain(iommu, sun50i_domain); } +static int sun50i_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) +{ + struct sun50i_iommu *iommu = dev_iommu_priv_get(dev); + + if (iommu->domain == identity_domain || !iommu->domain) + return 0; + sun50i_iommu_detach_device(iommu->domain, dev); + return 0; +} + +static struct iommu_domain_ops sun50i_iommu_identity_ops = { + .attach_dev = sun50i_iommu_identity_attach, +}; + +static struct iommu_domain sun50i_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &sun50i_iommu_identity_ops, +}; + static int sun50i_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { @@ -827,6 +847,7 @@ static int sun50i_iommu_of_xlate(struct device *dev, } static const struct iommu_ops sun50i_iommu_ops = { + .identity_domain = &sun50i_iommu_identity_domain, .pgsize_bitmap = SZ_4K, .device_group = sun50i_iommu_device_group, .domain_alloc = sun50i_iommu_domain_alloc, From patchwork Mon May 1 18:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B4DFC88C84 for ; Mon, 1 May 2023 18:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232708AbjEASDW (ORCPT ); Mon, 1 May 2023 14:03:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232658AbjEASDR (ORCPT ); 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The following table explains what each driver supports and what the resulting default_domain will be: ops->defaut_domain IDENTITY DMA PLATFORM v ARM32 dma-iommu ARCH amd/iommu.c Y Y N/A either apple-dart.c Y Y N/A either arm-smmu.c Y Y IDENTITY either qcom_iommu.c G Y IDENTITY either arm-smmu-v3.c Y Y N/A either exynos-iommu.c G Y IDENTITY either fsl_pamu_domain.c Y Y N/A N/A PLATFORM intel/iommu.c Y Y N/A either ipmmu-vmsa.c G Y IDENTITY either msm_iommu.c G IDENTITY N/A mtk_iommu.c G Y IDENTITY either mtk_iommu_v1.c G IDENTITY N/A omap-iommu.c G IDENTITY N/A rockchip-iommu.c G Y IDENTITY either s390-iommu.c Y Y N/A N/A PLATFORM sprd-iommu.c Y N/A DMA sun50i-iommu.c G Y IDENTITY either tegra-gart.c Y Y PLATFORM PLATFORM tegra-smmu.c G Y Y IDENTITY IDENTITY virtio-iommu.c Y Y N/A either * G means ops->identity_domain is used * N/A means the driver will not compile in this configuration ARM32 drivers, except for tegra-gart, select an IDENTITY default domain through either the ops->identity_domain or directly requesting an IDENTIY domain through alloc_domain(). tegra-gart will use its weird PLATFORM domain. In ARM64 mode tegra-smmu will still block the use of dma-iommu.c and forces an IDENTITY domain. S390 uses a PLATFORM domain to represent when the dma_ops are set to the s390 iommu code. fsl_pamu uses a PLATFORM domain. The x86 drivers continue unchanged. After this patch group->default_domain is only NULL for a short period during bus iommu probing while all the groups are constituted. Otherwise it is always !NULL. This completes changing the iommu subsystem driver contract to a system where the current iommu_domain always represents some form of translation and the driver is continuously asserting a definable translation mode. It resolves the confusion that the original ops->detach_dev() caused around what translation, exactly, is the IOMMU performing after detach. There were at least three different answers to that question in the tree, they are all now clearly named with domain types. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index fb646765a87f47..f20a031e2910b2 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1655,14 +1655,18 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) return __iommu_group_alloc_default_domain(bus, group, req_type); /* - * ARM32 drivers supporting CONFIG_ARM_DMA_USE_IOMMU can declare an - * identity_domain and it becomes their default domain. Later on - * ARM_DMA_USE_IOMMU will install its UNMANAGED domain. + * If ARM32 CONFIG_ARM_DMA_USE_IOMMU is enabled and the driver doesn't + * use the ops->default_domain override, install an IDENTITY domain as + * the default domain. Later on ARM_DMA_USE_IOMMU will install its + * UNMANAGED domain. */ - if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) && - bus->iommu_ops->identity_domain) + if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) { + static_assert(!(IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) && + IS_ENABLED(CONFIG_IOMMU_DMA))); + return __iommu_group_alloc_default_domain( bus, group, IOMMU_DOMAIN_IDENTITY); + } /* The driver gave no guidance on what type to use, try the default */ dom = __iommu_group_alloc_default_domain(bus, group, iommu_def_domain_type); @@ -2848,18 +2852,9 @@ static int iommu_setup_default_domain(struct iommu_group *group, if (req_type < 0) return -EINVAL; - /* - * There are still some drivers which don't support default domains, so - * we ignore the failure and leave group->default_domain NULL. - */ dom = iommu_group_alloc_default_domain(group, req_type); - if (!dom) { - /* Once in default_domain mode we never leave */ - if (group->default_domain) - return -ENODEV; - group->default_domain = NULL; - return 0; - } + if (!dom) + return -ENODEV; if (group->default_domain == dom) return 0; From patchwork Mon May 1 18:03:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1325C7EE29 for ; Mon, 1 May 2023 18:03:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231372AbjEASD3 (ORCPT ); Mon, 1 May 2023 14:03:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232711AbjEASDW (ORCPT ); Mon, 1 May 2023 14:03:22 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2056.outbound.protection.outlook.com [40.107.94.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A18E1701; 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Mon, 1 May 2023 18:03:13 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:13 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 18/20] iommu: Add ops->domain_alloc_paging() Date: Mon, 1 May 2023 15:03:02 -0300 Message-Id: <18-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BL0PR03CA0003.namprd03.prod.outlook.com (2603:10b6:208:2d::16) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: ca9fdfe8-e21b-4fcb-d55e-08db4a6e5153 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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More critically, this allows us to sweep out all the IOMMU_DOMAIN_UNMANAGED and IOMMU_DOMAIN_DMA checks from a lot of the drivers, simplifying what is going on in the code and ultimately removing the now-unused special cases in drivers where they did not support IOMMU_DOMAIN_DMA. domain_alloc_paging() should return a struct iommu_domain that is functionally compatible with ARM_DMA_USE_IOMMU, dma-iommu.c and iommufd. Be forwards looking and pass in a 'struct device *' argument. We can provide this when allocating the default_domain. No drivers will look at this. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 40 ++++++++++++++++++++++++---------------- include/linux/iommu.h | 2 ++ 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index f20a031e2910b2..fee417df8f195d 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -93,6 +93,7 @@ static int iommu_bus_notifier(struct notifier_block *nb, unsigned long action, void *data); static void iommu_release_device(struct device *dev); static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, + struct device *dev, unsigned type); static int __iommu_attach_device(struct iommu_domain *domain, struct device *dev); @@ -1618,12 +1619,12 @@ static int iommu_get_def_domain_type(struct device *dev) } static struct iommu_domain * -__iommu_group_alloc_default_domain(struct bus_type *bus, +__iommu_group_alloc_default_domain(struct group_device *gdev, struct iommu_group *group, int req_type) { if (group->default_domain && group->default_domain->type == req_type) return group->default_domain; - return __iommu_domain_alloc(bus, req_type); + return __iommu_domain_alloc(gdev->dev->bus, gdev->dev, req_type); } /* @@ -1633,9 +1634,9 @@ __iommu_group_alloc_default_domain(struct bus_type *bus, static struct iommu_domain * iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) { - struct bus_type *bus = - list_first_entry(&group->devices, struct group_device, list) - ->dev->bus; + struct group_device *gdev = + list_first_entry(&group->devices, struct group_device, list); + const struct iommu_ops *ops = dev_iommu_ops(gdev->dev); struct iommu_domain *dom; lockdep_assert_held(&group->mutex); @@ -1645,14 +1646,15 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) * domain. This should always be either an IDENTITY or PLATFORM domain. * Do not use in new drivers. */ - if (bus->iommu_ops->default_domain) { + if (ops->default_domain) { if (req_type) return ERR_PTR(-EINVAL); - return bus->iommu_ops->default_domain; + return ops->default_domain; } if (req_type) - return __iommu_group_alloc_default_domain(bus, group, req_type); + return __iommu_group_alloc_default_domain(gdev, group, + req_type); /* * If ARM32 CONFIG_ARM_DMA_USE_IOMMU is enabled and the driver doesn't @@ -1665,18 +1667,19 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) IS_ENABLED(CONFIG_IOMMU_DMA))); return __iommu_group_alloc_default_domain( - bus, group, IOMMU_DOMAIN_IDENTITY); + gdev, group, IOMMU_DOMAIN_IDENTITY); } /* The driver gave no guidance on what type to use, try the default */ - dom = __iommu_group_alloc_default_domain(bus, group, iommu_def_domain_type); + dom = __iommu_group_alloc_default_domain(gdev, group, + iommu_def_domain_type); if (dom) return dom; /* Otherwise IDENTITY and DMA_FQ defaults will try DMA */ if (iommu_def_domain_type == IOMMU_DOMAIN_DMA) return NULL; - dom = __iommu_group_alloc_default_domain(bus, group, IOMMU_DOMAIN_DMA); + dom = __iommu_group_alloc_default_domain(gdev, group, IOMMU_DOMAIN_DMA); if (!dom) return NULL; @@ -1930,6 +1933,7 @@ void iommu_set_fault_handler(struct iommu_domain *domain, EXPORT_SYMBOL_GPL(iommu_set_fault_handler); static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, + struct device *dev, unsigned type) { struct iommu_domain *domain; @@ -1940,7 +1944,11 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, if (type == IOMMU_DOMAIN_IDENTITY && bus->iommu_ops->identity_domain) return bus->iommu_ops->identity_domain; - domain = bus->iommu_ops->domain_alloc(type); + if ((type == IOMMU_DOMAIN_UNMANAGED || type == IOMMU_DOMAIN_DMA) && + bus->iommu_ops->domain_alloc_paging) + domain = bus->iommu_ops->domain_alloc_paging(dev); + else + domain = bus->iommu_ops->domain_alloc(type); if (!domain) return NULL; @@ -1964,7 +1972,7 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, struct iommu_domain *iommu_domain_alloc(struct bus_type *bus) { - return __iommu_domain_alloc(bus, IOMMU_DOMAIN_UNMANAGED); + return __iommu_domain_alloc(bus, NULL, IOMMU_DOMAIN_UNMANAGED); } EXPORT_SYMBOL_GPL(iommu_domain_alloc); @@ -3079,15 +3087,15 @@ static int __iommu_group_alloc_blocking_domain(struct iommu_group *group) if (group->blocking_domain) return 0; - group->blocking_domain = - __iommu_domain_alloc(dev->dev->bus, IOMMU_DOMAIN_BLOCKED); + group->blocking_domain = __iommu_domain_alloc(dev->dev->bus, dev->dev, + IOMMU_DOMAIN_BLOCKED); if (!group->blocking_domain) { /* * For drivers that do not yet understand IOMMU_DOMAIN_BLOCKED * create an empty domain instead. */ group->blocking_domain = __iommu_domain_alloc( - dev->dev->bus, IOMMU_DOMAIN_UNMANAGED); + dev->dev->bus, dev->dev, IOMMU_DOMAIN_UNMANAGED); if (!group->blocking_domain) return -EINVAL; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f6a28ab78e607e..cc9aff2d213eec 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -227,6 +227,7 @@ struct iommu_iotlb_gather { * struct iommu_ops - iommu ops and capabilities * @capable: check capability * @domain_alloc: allocate iommu domain + * @domain_alloc_paging: Allocate an IOMMU_DOMAIN_UNMANAGED * @probe_device: Add device to iommu driver handling * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU @@ -258,6 +259,7 @@ struct iommu_ops { /* Domain allocation and freeing by the iommu driver */ struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); 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Mon, 1 May 2023 18:03:12 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:12 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 19/20] iommu: Convert simple drivers with DOMAIN_DMA to domain_alloc_paging() Date: Mon, 1 May 2023 15:03:03 -0300 Message-Id: <19-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BL0PR03CA0024.namprd03.prod.outlook.com (2603:10b6:208:2d::37) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: 0678eb25-4a8c-4033-c662-08db4a6e5121 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nlQVRfokKJt3mNfglpqhx9Q7pSE5cLZvulShYnwyTmH/K1x8zu70XHzEnBcHCj7gAqfLZeMjCxZL3KCAb4Vr1gPSNTPsIm+yPba6IXdbTkDy1XKqwxOZ45RrigG3vFH7qRsbIYuKTVb+w3HbQBAryI3XA5jSkllGyVsBVqlxplO5IL9UoV84CsrC47C7HmmEDcCrGDkChMeZHM7rzEDtS1Tzmxe1mSwVVJpZFQEVjC4WSmB3XiDyj2aMqsJkMBm16Ain75/kc5ilivJt1fqNBV7HxQcpfgi+bXpby2CIZbS1Ki082jbdb/6ayc/+S3ZOqSjSqY2NPWMX0jwrPy1J+LsMRPCdGLikJMZp2/+e3Nd4XF89jJ5T+cGT/QpdiITG6gs1Pb6SyOzwvrzH9n8y/xJ2hvgmMg2G9hsBd6SItRmeiRVtDoq+cxkvO/RR0VInyEDFPPyn5py9QeGtTVK+pDnA7lRa8Dm0/iI4AApwXblmpf9IHhMLSNvqp7ceuZ3SZrr5pUx2vP8n5mnrT/INK+Ea5+tIzdKeChkks7vPL2QCa0pRPMjITwgF959A2HMrmQ4AFzSoYubcFAIxcw7xwj+usROiBae6sMZORrKoDJKfPbogie3RzftYm9drNpoLFriqilKRCcFFl1v1CCxGKdzjnwMHflOF3TIOa3YV4c67G23X59Asp6c84oMk8iVijYw6lmfDmQwjrYWCYpj4OGmpCkQc8DdI8S/J5h9tbNe7HYfrSLdggs68YjoccaHjzvETqmLt+zzOxYCcBlrGuZwF26JQW6LWV0lGILW6yTbMHoOPA9w5ri9Q0R5ad5iHAjM/saMo/vkjZXXfPvotHS675rSZITaSXNeKGtxMMyqKd7QJaFmMP3ad6TOPWCJiAXAuNx0qe0Re7v7wD+ydQIPOUwz0TJDQcQ/b3uaLww5wa8E2DbNvbJd7yO6V89h1QHrzXwLGQ88ngL0pvRgV3pkZVd9Ku2bh875DmZdSUJeRoWuDhMeUouNwWy8VMuvShU27d7x2ZLOR1fCZBklvch5UPAUaWi/32dTSIsuFzNUwpi/bZhncAfVFqUEtyR56JwPL1AKpmGav4t7gtiqwL/OIAAMmcdSeqgu+1aFFjSiT2IXRqdOV8ZkZU2Aj35ctlu6wd+6n6NKqIpnhcgZD9yWFv9JIiVOxyv428KHKmSSzYDnqxMAfIKiVPGr/JSreEwAKQSGF38GIDuUuFHoOkMXtj9e9uXAH7o/CBOET7apDEbep50h2ir87FZrjQc8TEfHHfgUfaYHf2efodbJQsS3WjWhRO3pjnPHrffB9X8sq5f9DR4l77S6357cW9powNPfcg/avSeqlfosArK0SRYCatt7PzpEp+v6n3HJIMtxfpra4aZecRoOnLVbLQKTInrI/iiF0F+DU2uCrXjWTJfLWWPOAOfAVem08wtcQKXYE3b39zt2zc2zZIywPumrXl+SkHO/BtGQH38Wa47IM2rOkBJ/s6cTt8YYVPs4W/3JPIYjWxNtWlKfFBA6eNeCXM1FyF55c0L4soukMfUqmZsiCQBneH/TTiHtE0t3hCgzt10H9Fs2vA/08VhkD5rcY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0678eb25-4a8c-4033-c662-08db4a6e5121 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:07.3669 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: N1V2ZyUEwHbhSeEYF6BIuSVdjC71NgIZEf4zaGwhwPrBNqFB2nH6xcFsQO9vUWKg X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These drivers are all trivially converted since the function is only called if the domain type is going to be IOMMU_DOMAIN_UNMANAGED/DMA. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 6 ++---- drivers/iommu/exynos-iommu.c | 7 ++----- drivers/iommu/ipmmu-vmsa.c | 7 ++----- drivers/iommu/mtk_iommu.c | 7 ++----- drivers/iommu/rockchip-iommu.c | 7 ++----- drivers/iommu/sprd-iommu.c | 7 ++----- drivers/iommu/sun50i-iommu.c | 9 +++------ drivers/iommu/tegra-smmu.c | 7 ++----- 8 files changed, 17 insertions(+), 40 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 9d7b9d8b4386d4..a2140fdc65ed58 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -319,12 +319,10 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, return ret; } -static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type) +static struct iommu_domain *qcom_iommu_domain_alloc_paging(struct device *dev) { struct qcom_iommu_domain *qcom_domain; - if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) - return NULL; /* * Allocate the domain and initialise some of its data structures. * We can't really do anything meaningful until we've added a @@ -593,7 +591,7 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) static const struct iommu_ops qcom_iommu_ops = { .identity_domain = &qcom_iommu_identity_domain, .capable = qcom_iommu_capable, - .domain_alloc = qcom_iommu_domain_alloc, + .domain_alloc_paging = qcom_iommu_domain_alloc_paging, .probe_device = qcom_iommu_probe_device, .device_group = generic_device_group, .of_xlate = qcom_iommu_of_xlate, diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 6ff7901103948a..2af0a735f3dc2c 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -887,7 +887,7 @@ static inline void exynos_iommu_set_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) DMA_TO_DEVICE); } -static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) +static struct iommu_domain *exynos_iommu_domain_alloc_paging(struct device *dev) { struct exynos_iommu_domain *domain; dma_addr_t handle; @@ -896,9 +896,6 @@ static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) /* Check if correct PTE offsets are initialized */ BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); - if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - domain = kzalloc(sizeof(*domain), GFP_KERNEL); if (!domain) return NULL; @@ -1474,7 +1471,7 @@ static int exynos_iommu_of_xlate(struct device *dev, static const struct iommu_ops exynos_iommu_ops = { .identity_domain = &exynos_identity_domain, - .domain_alloc = exynos_iommu_domain_alloc, + .domain_alloc_paging = exynos_iommu_domain_alloc_paging, .device_group = generic_device_group, .probe_device = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index de958e411a92e0..27d36347e0fced 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -566,13 +566,10 @@ static irqreturn_t ipmmu_irq(int irq, void *dev) * IOMMU Operations */ -static struct iommu_domain *ipmmu_domain_alloc(unsigned type) +static struct iommu_domain *ipmmu_domain_alloc_paging(struct device *dev) { struct ipmmu_vmsa_domain *domain; - if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) - return NULL; - domain = kzalloc(sizeof(*domain), GFP_KERNEL); if (!domain) return NULL; @@ -891,7 +888,7 @@ static struct iommu_group *ipmmu_find_group(struct device *dev) static const struct iommu_ops ipmmu_ops = { .identity_domain = &ipmmu_iommu_identity_domain, - .domain_alloc = ipmmu_domain_alloc, + .domain_alloc_paging = ipmmu_domain_alloc_paging, .probe_device = ipmmu_probe_device, .release_device = ipmmu_release_device, .probe_finalize = ipmmu_probe_finalize, diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index e4b9f728002403..e0bb10adc62967 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -667,13 +667,10 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, return 0; } -static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) +static struct iommu_domain *mtk_iommu_domain_alloc_paging(struct device *dev) { struct mtk_iommu_domain *dom; - if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - dom = kzalloc(sizeof(*dom), GFP_KERNEL); if (!dom) return NULL; @@ -994,7 +991,7 @@ static void mtk_iommu_get_resv_regions(struct device *dev, static const struct iommu_ops mtk_iommu_ops = { .identity_domain = &mtk_iommu_identity_domain, - .domain_alloc = mtk_iommu_domain_alloc, + .domain_alloc_paging = mtk_iommu_domain_alloc_paging, .probe_device = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, .device_group = mtk_iommu_device_group, diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 9e1296a856ac4c..24a2a09fea5503 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1071,13 +1071,10 @@ static int rk_iommu_attach_device(struct iommu_domain *domain, return ret; } -static struct iommu_domain *rk_iommu_domain_alloc(unsigned type) +static struct iommu_domain *rk_iommu_domain_alloc_paging(struct device *dev) { struct rk_iommu_domain *rk_domain; - if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) - return NULL; - if (!dma_dev) return NULL; @@ -1200,7 +1197,7 @@ static int rk_iommu_of_xlate(struct device *dev, static const struct iommu_ops rk_iommu_ops = { .identity_domain = &rk_identity_domain, - .domain_alloc = rk_iommu_domain_alloc, + .domain_alloc_paging = rk_iommu_domain_alloc_paging, .probe_device = rk_iommu_probe_device, .release_device = rk_iommu_release_device, .device_group = rk_iommu_device_group, diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 39e34fdeccda78..af68b3a2c123ab 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -133,13 +133,10 @@ sprd_iommu_pgt_size(struct iommu_domain *domain) SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32); } -static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type) +static struct iommu_domain *sprd_iommu_domain_alloc_paging(struct device *dev) { struct sprd_iommu_domain *dom; - if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - dom = kzalloc(sizeof(*dom), GFP_KERNEL); if (!dom) return NULL; @@ -419,7 +416,7 @@ static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) static const struct iommu_ops sprd_iommu_ops = { - .domain_alloc = sprd_iommu_domain_alloc, + .domain_alloc_paging = sprd_iommu_domain_alloc_paging, .probe_device = sprd_iommu_probe_device, .device_group = sprd_iommu_device_group, .of_xlate = sprd_iommu_of_xlate, diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 15fd62d360778f..2831398ea2ca71 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -667,14 +667,11 @@ static phys_addr_t sun50i_iommu_iova_to_phys(struct iommu_domain *domain, sun50i_iova_get_page_offset(iova); } -static struct iommu_domain *sun50i_iommu_domain_alloc(unsigned type) +static struct iommu_domain * +sun50i_iommu_domain_alloc_paging(struct device *paging) { struct sun50i_iommu_domain *sun50i_domain; - if (type != IOMMU_DOMAIN_DMA && - type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - sun50i_domain = kzalloc(sizeof(*sun50i_domain), GFP_KERNEL); if (!sun50i_domain) return NULL; @@ -850,7 +847,7 @@ static const struct iommu_ops sun50i_iommu_ops = { .identity_domain = &sun50i_iommu_identity_domain, .pgsize_bitmap = SZ_4K, .device_group = sun50i_iommu_device_group, - .domain_alloc = sun50i_iommu_domain_alloc, + .domain_alloc_paging = sun50i_iommu_domain_alloc_paging, .of_xlate = sun50i_iommu_of_xlate, .probe_device = sun50i_iommu_probe_device, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 7c301a732db2c0..115e51442df5c1 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -272,13 +272,10 @@ static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) clear_bit(id, smmu->asids); } -static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) +static struct iommu_domain *tegra_smmu_domain_alloc_paging(struct device *dev) { struct tegra_smmu_as *as; - if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) - return NULL; - as = kzalloc(sizeof(*as), GFP_KERNEL); if (!as) return NULL; @@ -986,7 +983,7 @@ static const struct iommu_ops tegra_smmu_ops = { */ .default_domain = &tegra_smmu_identity_domain, .identity_domain = &tegra_smmu_identity_domain, - .domain_alloc = tegra_smmu_domain_alloc, + .domain_alloc_paging = tegra_smmu_domain_alloc_paging, .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, .of_xlate = tegra_smmu_of_xlate, From patchwork Mon May 1 18:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13227789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97DABC7EE32 for ; Mon, 1 May 2023 18:03:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232764AbjEASDc (ORCPT ); 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by IA1PR12MB6457.namprd12.prod.outlook.com (2603:10b6:208:3ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.30; Mon, 1 May 2023 18:03:14 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6340.030; Mon, 1 May 2023 18:03:14 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Matthias Brugger , Matthew Rosato , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Niklas Schnelle , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Kevin Tian , Nicolin Chen , Steven Price Subject: [PATCH 20/20] iommu: Convert remaining simple drivers to domain_alloc_paging() Date: Mon, 1 May 2023 15:03:04 -0300 Message-Id: <20-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v1-21cc72fcfb22+a7a-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR06CA0022.namprd06.prod.outlook.com (2603:10b6:208:23d::27) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|IA1PR12MB6457:EE_ X-MS-Office365-Filtering-Correlation-Id: e9159dc7-1166-4bb7-4957-08db4a6e5169 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4JU62A81EJU7zMj/Keu2ufqUsCCHhVVJpF+Pamijl6PURRdBu4s+2e63+IueoZpPciqr9C4+5LR+7/b4CEQ4NAPaa2SKqKCw5WF3jamir9Lk0FiV5eSLVemP74BnhzIuzcund+UErIvE49IY+sDrQCcj8/Xys04zCwTcBeO4HkiDdDgjNS3KcQgsabBN+B1h2KH+wrBEOuOyBsV5DarFvf9qsOuFJPKHLyFmeiFMHnTSI7R7OqlqWXg0Ob6BFqhWAr+RMXLojpsNUf9dbsdJJwcn0yiqzX9y70VmlYmXd2Y9+M3u+BnInlOPgF4Gx+H1ppzwE8Zw5ZGeh31SbUG9k7JowgRbbSpfyscFQcA7qsboD7rxJ+JEXG4DgfYGTrPsNvYFesuBK3fDt3SxJ3i6eaz8dFE1tXdaPC/XSMt7UXrshgcqFbG71d7/r5V8FIyYTXVIkAWfVo/jyvb4hE8sJHaXyRPDhHjXoUzlGtga8swCqtQnpmyaztgXBpYGuKzfwnXw6JJTthI5+vjqjH04/Vm43xlzzUn9nS0gMV4CDpCMcceQfvzrsVPmxmVLwOGdpoBjOl2PX0ZevoV89OpFY+7d1hUxOTw08RcYY8QoUihiTpMCFmRA4KFSxKIMsmL2krtP3xa31utaQPyfV9f17Hh2ti9/cmRf9HGoJPIQ4hWvmhVovOkKGawEsHVe0TBnwkk0TREbmGGSouCNxG5o9KuTr2rfhGBZ2avdiIXBEfve3W3LMAlJVf+SIVPy+EEetElvmYNFmGcnGJqXXKaespX1LU6OzvhQ+mVZt+fhaxoOnArZhUBxICF2t8BXmsciqcITKgzdcwryDuRxNqmve0MaXqCJ79/TFcUinCN3l7PL1dU0hBvOmqj8q1c6IWaf71AzbgogX5XjAUKK2KBr6/5pYsf1llzm5/bkNXrRwMnXsnRVUNV67M5FcLe1M185dZIB79F+5tRjUFQMKgvW/E/eTkPq5PLcffRgEEy8Oc7gwFEzdiGdrB48Ieud9pA/odOCEvFNB0R5AVZRpDNepnEiwzelLZh5R70PDlRurJVmuG+Whv2ML81Vw49ZqQDg3qe7bMvep8WAiJ5OrZ6XWqT3pqM2ZRHO8Z6SuG754Z6aOrAaRcABJjUc+gDdd5eQ+zfsn8qeZgTcqYa6ChJG2krZb0dS3aXgjSMbtf4h4JP12T3oHqqciz/UPnmvuv4YxddlvQFhG5DLZxaWkK2VUBE1CYWEpjMJZl3cvfkRuInYh3rY2OW2Qzqwkag3x+gosDmcGa2Dse0ogdjyBaEJ6b0XoaY4BJEGhkwJ3Lg8/rfZBnCmLqwQOH5mAnychUIrzFsT00D9hqIFtMOSvOBOd2Y1jCLXRenLd6hOQWgDWS+QPMpBaPhDL7ibU4KcilW2G3BWOOPhn6WWSo29uO7pP727yg1wjuwryWcmH4tMR1Lv/DK44zrSZW24LtrnCV7TKGgU4VgP7KlYOtcHAibFmnw5Gz2Oo6e5viP8NuAzSGw8qBkt2pOqBKdizqaRaPh1AW/rAsii9Az7w4ICI693lo88nXjU6Rdu/5jt97UogS0hoj0eK7d1xE+GhHKhxCCP X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e9159dc7-1166-4bb7-4957-08db4a6e5169 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:07.7860 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oLSLcaEVCPUEJVqvMvCNlVEL0My5KVFiW57R4zcjfzz4kErlGQzumMXXeWQJ48IC X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These drivers don't support IOMMU_DOMAIN_DMA, so this commit effectively allows them to support that mode. The prior work to require default_domains makes this safe because every one of these drivers is either compilation incompatible with dma-iommu.c, or already establishing a default_domain. In both cases alloc_domain() will never be called with IOMMU_DOMAIN_DMA for these drivers so it is safe to drop the test. Removing these tests clarifies that the domain allocation path is only about the functionality of a paging domain and has nothing to do with policy of how the paging domain is used for UNMANAGED/DMA/DMA_FQ. Signed-off-by: Jason Gunthorpe Acked-by: Niklas Schnelle # s390 --- drivers/iommu/fsl_pamu_domain.c | 7 ++----- drivers/iommu/msm_iommu.c | 7 ++----- drivers/iommu/mtk_iommu_v1.c | 7 ++----- drivers/iommu/omap-iommu.c | 7 ++----- drivers/iommu/s390-iommu.c | 7 ++----- drivers/iommu/tegra-gart.c | 7 ++----- 6 files changed, 12 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 4c65f1adfe7511..641e89f7d7f444 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -192,13 +192,10 @@ static void fsl_pamu_domain_free(struct iommu_domain *domain) kmem_cache_free(fsl_pamu_domain_cache, dma_domain); } -static struct iommu_domain *fsl_pamu_domain_alloc(unsigned type) +static struct iommu_domain *fsl_pamu_domain_alloc_paging(struct device *dev) { struct fsl_dma_domain *dma_domain; - if (type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - dma_domain = kmem_cache_zalloc(fsl_pamu_domain_cache, GFP_KERNEL); if (!dma_domain) return NULL; @@ -473,7 +470,7 @@ static struct iommu_device *fsl_pamu_probe_device(struct device *dev) static const struct iommu_ops fsl_pamu_ops = { .default_domain = &fsl_pamu_platform_domain, .capable = fsl_pamu_capable, - .domain_alloc = fsl_pamu_domain_alloc, + .domain_alloc_paging = fsl_pamu_domain_alloc_paging, .probe_device = fsl_pamu_probe_device, .device_group = fsl_pamu_device_group, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 26ed81cfeee897..a163cee0b7242d 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -302,13 +302,10 @@ static void __program_context(void __iomem *base, int ctx, SET_M(base, ctx, 1); } -static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) +static struct iommu_domain *msm_iommu_domain_alloc_paging(struct device *dev) { struct msm_priv *priv; - if (type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) goto fail_nomem; @@ -691,7 +688,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) static struct iommu_ops msm_iommu_ops = { .identity_domain = &msm_iommu_identity_domain, - .domain_alloc = msm_iommu_domain_alloc, + .domain_alloc_paging = msm_iommu_domain_alloc_paging, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, .pgsize_bitmap = MSM_IOMMU_PGSIZES, diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index 7c0c1d50df5f75..67e044c1a7d93b 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -270,13 +270,10 @@ static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data) return 0; } -static struct iommu_domain *mtk_iommu_v1_domain_alloc(unsigned type) +static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev) { struct mtk_iommu_v1_domain *dom; - if (type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - dom = kzalloc(sizeof(*dom), GFP_KERNEL); if (!dom) return NULL; @@ -585,7 +582,7 @@ static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) static const struct iommu_ops mtk_iommu_v1_ops = { .identity_domain = &mtk_iommu_v1_identity_domain, - .domain_alloc = mtk_iommu_v1_domain_alloc, + .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging, .probe_device = mtk_iommu_v1_probe_device, .probe_finalize = mtk_iommu_v1_probe_finalize, .release_device = mtk_iommu_v1_release_device, diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 34340ef15241bc..fcf99bd195b32e 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1580,13 +1580,10 @@ static struct iommu_domain omap_iommu_identity_domain = { .ops = &omap_iommu_identity_ops, }; -static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) +static struct iommu_domain *omap_iommu_domain_alloc_paging(struct device *dev) { struct omap_iommu_domain *omap_domain; - if (type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); if (!omap_domain) return NULL; @@ -1748,7 +1745,7 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) static const struct iommu_ops omap_iommu_ops = { .identity_domain = &omap_iommu_identity_domain, - .domain_alloc = omap_iommu_domain_alloc, + .domain_alloc_paging = omap_iommu_domain_alloc_paging, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, diff --git a/drivers/iommu/s390-iommu.c b/drivers/iommu/s390-iommu.c index f0c867c57a5b9b..5695ad71d60e24 100644 --- a/drivers/iommu/s390-iommu.c +++ b/drivers/iommu/s390-iommu.c @@ -39,13 +39,10 @@ static bool s390_iommu_capable(struct device *dev, enum iommu_cap cap) } } -static struct iommu_domain *s390_domain_alloc(unsigned domain_type) +static struct iommu_domain *s390_domain_alloc_paging(struct device *dev) { struct s390_domain *s390_domain; - if (domain_type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - s390_domain = kzalloc(sizeof(*s390_domain), GFP_KERNEL); if (!s390_domain) return NULL; @@ -447,7 +444,7 @@ void zpci_destroy_iommu(struct zpci_dev *zdev) static const struct iommu_ops s390_iommu_ops = { .default_domain = &s390_iommu_platform_domain, .capable = s390_iommu_capable, - .domain_alloc = s390_domain_alloc, + .domain_alloc_paging = s390_domain_alloc_paging, .probe_device = s390_iommu_probe_device, .release_device = s390_iommu_release_device, .device_group = generic_device_group, diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index 09865889ff2480..b90801dddef413 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -167,13 +167,10 @@ static struct iommu_domain gart_iommu_platform_domain = { .ops = &gart_iommu_platform_ops, }; -static struct iommu_domain *gart_iommu_domain_alloc(unsigned type) +static struct iommu_domain *gart_iommu_domain_alloc_paging(struct device *dev) { struct iommu_domain *domain; - if (type != IOMMU_DOMAIN_UNMANAGED) - return NULL; - domain = kzalloc(sizeof(*domain), GFP_KERNEL); if (domain) { domain->geometry.aperture_start = gart_handle->iovmm_base; @@ -294,7 +291,7 @@ static void gart_iommu_sync(struct iommu_domain *domain, static const struct iommu_ops gart_iommu_ops = { .default_domain = &gart_iommu_platform_domain, - .domain_alloc = gart_iommu_domain_alloc, + .domain_alloc_paging = gart_iommu_domain_alloc_paging, .probe_device = gart_iommu_probe_device, .device_group = generic_device_group, .pgsize_bitmap = GART_IOMMU_PGSIZES,