From patchwork Mon May 1 19:20:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Andryuk X-Patchwork-Id: 13227913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79453C77B7C for ; Mon, 1 May 2023 19:21:18 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.528062.820617 (Exim 4.92) (envelope-from ) id 1ptZ56-00034r-75; Mon, 01 May 2023 19:21:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 528062.820617; Mon, 01 May 2023 19:21:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ56-00034k-3J; Mon, 01 May 2023 19:21:04 +0000 Received: by outflank-mailman (input) for mailman id 528062; Mon, 01 May 2023 19:21:03 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ55-0002np-CQ for xen-devel@lists.xenproject.org; Mon, 01 May 2023 19:21:03 +0000 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [2607:f8b0:4864:20::730]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4f87efd6-e855-11ed-b225-6b7b168915f2; Mon, 01 May 2023 21:21:02 +0200 (CEST) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-75131c2997bso1448687285a.1 for ; Mon, 01 May 2023 12:21:02 -0700 (PDT) Received: from pm2-ws13.praxislan02.com (207-172-141-204.s8906.c3-0.slvr-cbr1.lnh-slvr.md.cable.rcncustomer.com. [207.172.141.204]) by smtp.gmail.com with ESMTPSA id x20-20020a0ce0d4000000b0061927ddb043sm2012307qvk.80.2023.05.01.12.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 May 2023 12:21:01 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4f87efd6-e855-11ed-b225-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682968862; x=1685560862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7VFwxnOVM/nUJWo2+kFJfbzF53GX8dfaVA+R5Uyazpc=; b=fxt+FrecoN8NG22EJ/cAh7e8No5T6QNfq9reDEVzQ7EdqNL/B6JjLggYYDL8/2v9gw rqD/WLcw8nkbQ1SUKcI+20o+Tu/W9Uiz5MTfrNtY9z5uam7qXqGBya8azNCJXqFE08Xk kbLvDoQ58GUkDwEw8Oc527I9EEPhPMQfZU+xCLzjQ1YGwAqpbGUbQaOEkMYGsHJIXH1L ySUDH5HHSwLUWEP9aC89yK74HssrIkNPdaGDzaXZuAOB0Sej6K3TDScZC/zTqYlii53O rIDA4MvVDlT7jnNZ9kdGxQgRPZdyo56FQJRUOrLxOE1Wr3NdZYkx/ZvxbQriRsaVfWG3 ku3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682968862; x=1685560862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7VFwxnOVM/nUJWo2+kFJfbzF53GX8dfaVA+R5Uyazpc=; b=ZIfSwEFvebKWOzBAKg16cOISPs987j4sF+asXIsJaX/a5mlyTPTWd+X8ZoA6SrYOWf RzfId430GKKBf3oLhNDV5YfRkXqf77NBIu/Bk6zjHlia6YmFOCPiFds5Us1Ep95BS+xw MrJ3JFpv/RnpYAUowWU86riJkJjaf/u/oc6NXicqFwfGmb+q9VhC/P2uWoWcYpf7nj13 Jzdq6TYSz+tTbxcwAozk6lwaVv86Q1qh4XeRezihMiXXUi35K++sCcabjuaE1migZfoF SGGEvtQPZVcTY993ZxjD8CD7JnUHGLqTTi7WMWzzto1b/cgQ6iIdwzZx+amYYGzgGwm6 m+Qg== X-Gm-Message-State: AC+VfDyN6RQlOMvETukC083AAehwduDtpfEQDdC9aKGyygQh2JdYznoE GYqNURPzOfOg9nGzTv3iYR4= X-Google-Smtp-Source: ACHHUZ7GV+m0SaqcaVilE9mZSkNpsz96YrsDMORzgTpHu95CZ/am2ZJKlVW9lI3rEQAcEmBuuBN5wQ== X-Received: by 2002:a05:6214:c8c:b0:5ef:512d:2d47 with SMTP id r12-20020a0562140c8c00b005ef512d2d47mr1231450qvr.19.1682968861656; Mon, 01 May 2023 12:21:01 -0700 (PDT) From: Jason Andryuk To: xen-devel@lists.xenproj, xen-devel@lists.xenproject.org Cc: Jason Andryuk , Jan Beulich Subject: [PATCH v3 01/14] cpufreq: Allow restricting to internal governors only Date: Mon, 1 May 2023 15:20:32 -0400 Message-Id: <20230501192045.87377-2-jandryuk@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501192045.87377-1-jandryuk@gmail.com> References: <20230501192045.87377-1-jandryuk@gmail.com> MIME-Version: 1.0 For hwp, the standard governors are not usable, and only the internal one is applicable. Add the cpufreq_governor_internal boolean to indicate when an internal governor, like hwp-internal, will be used. This is set during presmp_initcall, so that it can suppress governor registration during initcall. Only a governor with a name containing "-internal" will be allowed in that case. This way, the unuseable governors are not registered, so the internal one is the only one returned to userspace. This means incompatible governors won't be advertised to userspace. Signed-off-by: Jason Andryuk Acked-by: Jan Beulich --- v3: Switch to initdata Add Jan Acked-by Commit message s/they/the/ typo Don't register hwp-internal when running non-hwp - Marek v2: Switch to "-internal" Add blank line in header --- xen/drivers/cpufreq/cpufreq.c | 8 ++++++++ xen/include/acpi/cpufreq/cpufreq.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 2321c7dd07..7bd81680da 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -56,6 +56,7 @@ struct cpufreq_dom { }; static LIST_HEAD_READ_MOSTLY(cpufreq_dom_list_head); +bool __initdata cpufreq_governor_internal; struct cpufreq_governor *__read_mostly cpufreq_opt_governor; LIST_HEAD_READ_MOSTLY(cpufreq_governor_list); @@ -121,6 +122,13 @@ int __init cpufreq_register_governor(struct cpufreq_governor *governor) if (!governor) return -EINVAL; + if (cpufreq_governor_internal && + strstr(governor->name, "-internal") == NULL) + return -EINVAL; + + if (!cpufreq_governor_internal && strstr(governor->name, "-internal")) + return -EINVAL; + if (__find_governor(governor->name) != NULL) return -EEXIST; diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index 35dcf21e8f..0da32ef519 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -114,6 +114,8 @@ extern struct cpufreq_governor cpufreq_gov_userspace; extern struct cpufreq_governor cpufreq_gov_performance; extern struct cpufreq_governor cpufreq_gov_powersave; +extern bool cpufreq_governor_internal; + extern struct list_head cpufreq_governor_list; extern int cpufreq_register_governor(struct cpufreq_governor *governor); From patchwork Mon May 1 19:20:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Andryuk X-Patchwork-Id: 13227914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CDA2C7EE21 for ; Mon, 1 May 2023 19:21:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.528063.820627 (Exim 4.92) (envelope-from ) id 1ptZ5A-0003MU-D4; Mon, 01 May 2023 19:21:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 528063.820627; Mon, 01 May 2023 19:21:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5A-0003ML-AI; Mon, 01 May 2023 19:21:08 +0000 Received: by outflank-mailman (input) for mailman id 528063; Mon, 01 May 2023 19:21:06 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ58-0002np-O4 for xen-devel@lists.xenproject.org; Mon, 01 May 2023 19:21:06 +0000 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [2607:f8b0:4864:20::730]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 518ff36a-e855-11ed-b225-6b7b168915f2; Mon, 01 May 2023 21:21:06 +0200 (CEST) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-74fb8677a36so133678885a.0 for ; Mon, 01 May 2023 12:21:06 -0700 (PDT) Received: from pm2-ws13.praxislan02.com (207-172-141-204.s8906.c3-0.slvr-cbr1.lnh-slvr.md.cable.rcncustomer.com. [207.172.141.204]) by smtp.gmail.com with ESMTPSA id x20-20020a0ce0d4000000b0061927ddb043sm2012307qvk.80.2023.05.01.12.21.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 May 2023 12:21:04 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 518ff36a-e855-11ed-b225-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682968865; x=1685560865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=txBzmZlgf2a5ZApasbIDD2P8VUrWanxh/ZCZKapkSd4=; b=hnzzQkqw6iB4TnpMVolsM/d8tA0cLpu0rYq2RmzA5nHVBJa6VHBWbPjqIW0uCmQTUp sTHTPdiaSED7oKPvQeLQsKAATgCljdsn+MCz/RG6kH2ypD7ZqbfMoY6R0HGTi4r8sbJa vLXsFsL7O59YaDIhrpdY8gTEK7MrfC07APLJ70wAJkXqatxHLhrAJYYx5RT+v3jM+9mF 9rPC6jdrwvxBkIzcvDFk0czEXPAxtnVqYbEwo01XNdS6hA8AhE7gWz0u4GUIzitKoSib slFFJidmyr7rrVuZnj5teD6sjEbvDofZD+sEdBlTlhwKt1Ce80m/sho+QJMXIot4qpnK l7sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682968865; x=1685560865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=txBzmZlgf2a5ZApasbIDD2P8VUrWanxh/ZCZKapkSd4=; b=V8vp370i1PknhVmIhkzfuvNks4vnELh2lTUgXZVLmBlvtvuGO6lL8vZLUmez9X2CT6 2Vf54AU+OJhx1xUUySHYqZSrVBCn4OGXYIxaP5hAIJbJTpIb4pFfBYY9Mo7OEllaMAZc Tx5gAFITi17+vSIu5NAt4VNtsEEJjvLMlRzueRxVb59RU/WQ1cQZq1N4SnCf5hRiK4L3 442dV7SbSJRs4uldLLv31Tx+UYFfUuvG8jHGJyp77jV5V9Xx8DNfOUPUjt7+86JCTDwy PcYYcMc8BgNCQZ/XFhg2B2rlXygXyraPU5S5MLz9yxFhAwUL7g3MBT6snvLI8IBTLemp 6IAQ== X-Gm-Message-State: AC+VfDwluYVv3DIRT/UivgmMNO+rRj8OeSLjyF5l6jSsZ3OBWjzFWqi/ TsAwtVnwhLWdbAcI079ZKQI= X-Google-Smtp-Source: ACHHUZ417cxCd/vqsbSp93kURkQVEsMZjpcjAt0WtKYiNB7H5wmUcdd/cQhBwm4ZtrgjNj2q+ozWzw== X-Received: by 2002:a05:6214:c4c:b0:5ef:83cf:91c2 with SMTP id r12-20020a0562140c4c00b005ef83cf91c2mr1729663qvj.45.1682968865210; Mon, 01 May 2023 12:21:05 -0700 (PDT) From: Jason Andryuk To: xen-devel@lists.xenproj, xen-devel@lists.xenproject.org Cc: Jason Andryuk , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 02/14] cpufreq: Add perf_freq to cpuinfo Date: Mon, 1 May 2023 15:20:33 -0400 Message-Id: <20230501192045.87377-3-jandryuk@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501192045.87377-1-jandryuk@gmail.com> References: <20230501192045.87377-1-jandryuk@gmail.com> MIME-Version: 1.0 acpi-cpufreq scales the aperf/mperf measurements by max_freq, but HWP needs to scale by base frequency. Settings max_freq to base_freq "works" but the code is not obvious, and returning values to userspace is tricky. Add an additonal perf_freq member which is used for scaling aperf/mperf measurements. Signed-off-by: Jason Andryuk Acked-by: Jan Beulich --- v3: Add Jan's Ack I don't like this, but it seems the best way to re-use the common aperf/mperf code. The other option would be to add wrappers that then do the acpi vs. hwp scaling. --- xen/arch/x86/acpi/cpufreq/cpufreq.c | 2 +- xen/drivers/cpufreq/utility.c | 1 + xen/include/acpi/cpufreq/cpufreq.h | 3 +++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c index 2e0067fbe5..6c70d04395 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -316,7 +316,7 @@ unsigned int get_measured_perf(unsigned int cpu, unsigned int flag) else perf_percent = 0; - return policy->cpuinfo.max_freq * perf_percent / 100; + return policy->cpuinfo.perf_freq * perf_percent / 100; } static unsigned int cf_check get_cur_freq_on_cpu(unsigned int cpu) diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c index 9eb7ecedcd..6831f62851 100644 --- a/xen/drivers/cpufreq/utility.c +++ b/xen/drivers/cpufreq/utility.c @@ -236,6 +236,7 @@ int cpufreq_frequency_table_cpuinfo(struct cpufreq_policy *policy, policy->min = policy->cpuinfo.min_freq = min_freq; policy->max = policy->cpuinfo.max_freq = max_freq; + policy->cpuinfo.perf_freq = max_freq; policy->cpuinfo.second_max_freq = second_max_freq; if (policy->min == ~0) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index 0da32ef519..a06aa92f62 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -37,6 +37,9 @@ extern struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS]; struct cpufreq_cpuinfo { unsigned int max_freq; unsigned int second_max_freq; /* P1 if Turbo Mode is on */ + unsigned int perf_freq; /* Scaling freq for aperf/mpref. + acpi-cpufreq uses max_freq, but HWP uses + base_freq.*/ unsigned int min_freq; unsigned int transition_latency; /* in 10^(-9) s = nanoseconds */ }; From patchwork Mon May 1 19:20:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Andryuk X-Patchwork-Id: 13227915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D46CC77B73 for ; Mon, 1 May 2023 19:21:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.528064.820637 (Exim 4.92) (envelope-from ) id 1ptZ5D-0003eO-Nh; Mon, 01 May 2023 19:21:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 528064.820637; Mon, 01 May 2023 19:21:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5D-0003eF-K7; Mon, 01 May 2023 19:21:11 +0000 Received: by outflank-mailman (input) for mailman id 528064; Mon, 01 May 2023 19:21:10 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5C-0002np-B7 for xen-devel@lists.xenproject.org; Mon, 01 May 2023 19:21:10 +0000 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [2607:f8b0:4864:20::735]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 53a88cf9-e855-11ed-b225-6b7b168915f2; Mon, 01 May 2023 21:21:09 +0200 (CEST) Received: by mail-qk1-x735.google.com with SMTP id af79cd13be357-7515631b965so673368285a.0 for ; Mon, 01 May 2023 12:21:09 -0700 (PDT) Received: from pm2-ws13.praxislan02.com (207-172-141-204.s8906.c3-0.slvr-cbr1.lnh-slvr.md.cable.rcncustomer.com. [207.172.141.204]) by smtp.gmail.com with ESMTPSA id x20-20020a0ce0d4000000b0061927ddb043sm2012307qvk.80.2023.05.01.12.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 May 2023 12:21:07 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 53a88cf9-e855-11ed-b225-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682968869; x=1685560869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H9MXL508WAYhYYKIHs8d77jkKwZyoTe/WztjxZedAQ8=; b=rq0DvyOB5DfwmfNuwRvzir/PEUW4Q7Y7tqorFvzYUK9HQUsaW9yTveOdaSqHQszeGL jiHsrz5gRbbu3FwfmQLHNbPYDkloR8iXpYmZVMUNv2hNSzj2hJXttzAZO8x07fI705gn jEjQ0VogRFH3rkilyFMTeqorC6HRMiwrrdxRzNpgb/+UO1MRDIOj5z9QG6Z4oXYiBO19 pjtMBMhUGnFJh8mxInOdnvtei4CDIzG9sBwjryXnb6D0yA5/VK4QjvlalXEMDkEC8QcR LDYdb/AzkiKUFK1+YA8RUoc8TmDoG93/ulnV+j4qPQ5kzJhPSQCdGnQXYqSlLZjtIUXl Qzeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682968869; x=1685560869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H9MXL508WAYhYYKIHs8d77jkKwZyoTe/WztjxZedAQ8=; b=U0ezniXveMf1m1cRbCjB7AkO45yWgq1pvxcN7SuYUWKwpXLcAtAaY1g9hyikCgNUi/ dF0vqvLQyxeUvQXK3nlRyxMnQr157eU4/xRetceDVFptrZfjHY66M3SjHajrXCvqjle8 DIC8pvOFxbY9+vhTd2+qxMPFZ1k6Az4nkDNpWVz9rnqwKunBpmYSCg3xrYXh+0j3YZBQ 6vwVGpS1ejaRZVw6KV2mY8q+HRxoIqsV/TJHulx46RJJJvDW1xXlgzUwcMyShQ1a8x/K N+UXwH9C0Ca5UmWhfu7Ush7FmaVc6bMMhxIAkTdwfS7nPTIziAB+H/ku0Ru1zSDX99FB I0Zg== X-Gm-Message-State: AC+VfDxvdOinF02xc+MIvacBMiF9feDAUoDYFTTTXtNMAwSd6bBNkhZV WpOfR5ekxOLY4jg3G0SquUo= X-Google-Smtp-Source: ACHHUZ52fJMB7p3+z00UEHeNT6H5lQjNgXa9HJUz0dTy7X0df51pnNMHSDMMqDjFDxxrpToBKZMY8g== X-Received: by 2002:a05:6214:23cc:b0:572:6e81:ae9c with SMTP id hr12-20020a05621423cc00b005726e81ae9cmr1857350qvb.1.1682968868683; Mon, 01 May 2023 12:21:08 -0700 (PDT) From: Jason Andryuk To: xen-devel@lists.xenproj, xen-devel@lists.xenproject.org Cc: Jason Andryuk , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 03/14] cpufreq: Export intel_feature_detect Date: Mon, 1 May 2023 15:20:34 -0400 Message-Id: <20230501192045.87377-4-jandryuk@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501192045.87377-1-jandryuk@gmail.com> References: <20230501192045.87377-1-jandryuk@gmail.com> MIME-Version: 1.0 Export feature_detect as intel_feature_detect so it can be re-used by HWP. Signed-off-by: Jason Andryuk --- v3: Remove void * cast when calling intel_feature_detect v2: export intel_feature_detect with typed pointer Move intel_feature_detect to acpi/cpufreq/cpufreq.h since the declaration now contains struct cpufreq_policy *. --- xen/arch/x86/acpi/cpufreq/cpufreq.c | 8 ++++++-- xen/include/acpi/cpufreq/cpufreq.h | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c index 6c70d04395..f1cc473b4f 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -339,9 +339,8 @@ static unsigned int cf_check get_cur_freq_on_cpu(unsigned int cpu) return extract_freq(get_cur_val(cpumask_of(cpu)), data); } -static void cf_check feature_detect(void *info) +void intel_feature_detect(struct cpufreq_policy *policy) { - struct cpufreq_policy *policy = info; unsigned int eax; eax = cpuid_eax(6); @@ -353,6 +352,11 @@ static void cf_check feature_detect(void *info) } } +static void cf_check feature_detect(void *info) +{ + intel_feature_detect(info); +} + static unsigned int check_freqs(const cpumask_t *mask, unsigned int freq, struct acpi_cpufreq_data *data) { diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index a06aa92f62..0f334d2a43 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -243,4 +243,6 @@ int write_userspace_scaling_setspeed(unsigned int cpu, unsigned int freq); void cpufreq_dbs_timer_suspend(void); void cpufreq_dbs_timer_resume(void); +void intel_feature_detect(struct cpufreq_policy *policy); + #endif /* __XEN_CPUFREQ_PM_H__ */ From patchwork Mon May 1 19:20:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Andryuk X-Patchwork-Id: 13227917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E1FDC77B73 for ; Mon, 1 May 2023 19:21:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.528065.820647 (Exim 4.92) (envelope-from ) id 1ptZ5K-00041W-2F; Mon, 01 May 2023 19:21:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 528065.820647; Mon, 01 May 2023 19:21:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5J-00041N-TM; Mon, 01 May 2023 19:21:17 +0000 Received: by outflank-mailman (input) for mailman id 528065; Mon, 01 May 2023 19:21:16 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5I-0003yM-91 for xen-devel@lists.xenproject.org; Mon, 01 May 2023 19:21:16 +0000 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [2607:f8b0:4864:20::f2d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 559e417b-e855-11ed-8611-37d641c3527e; Mon, 01 May 2023 21:21:13 +0200 (CEST) Received: by mail-qv1-xf2d.google.com with SMTP id 6a1803df08f44-61b5a6865dfso8720006d6.3 for ; Mon, 01 May 2023 12:21:13 -0700 (PDT) Received: from pm2-ws13.praxislan02.com (207-172-141-204.s8906.c3-0.slvr-cbr1.lnh-slvr.md.cable.rcncustomer.com. [207.172.141.204]) by smtp.gmail.com with ESMTPSA id x20-20020a0ce0d4000000b0061927ddb043sm2012307qvk.80.2023.05.01.12.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 May 2023 12:21:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 559e417b-e855-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682968872; x=1685560872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hym2Jx5Z8r7rrhqAfu+8xxIV/nnrCdXHwFgph7V69FQ=; b=fGoIO+6qsbtKMFPSgN0i4Zavvb5MTnhhdqp8CeKrIMwrWVUoGzsS5GUMU3+Vf/BqaK vwExJ3rn+DHp4vhn7EgJIimziO/yBOwa9nYWdkh9s2/iGTkofXrSa2J3+pJQVNEi70vQ 9NoO/vP3pduE9AZow9+Q+ioOJRnST09uH6SvlQQOhIftyDKMET4CLUxaeV0aQPuOYnHW JByxXuaAkZf8rc6KIGViImcm3TCKJwiKT/wjVmLGWLl4npF/XU3/cPhAo3jQTwctqHfj XAeyll9kEcP3rK6l0/CWTUG24Y3NObIfxdL0RryyhEGH41d8fWxJ+/xDoXWUs3qOj3ux 1qkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682968872; x=1685560872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hym2Jx5Z8r7rrhqAfu+8xxIV/nnrCdXHwFgph7V69FQ=; b=eLUNg4WDMCt7yT6IdEEbWtdKHNXmPUOZRmtqnsm7MCn+qZm3U+rTyyXXQBAKtbNOUH IWBL2WqgEbHaGK45z55iqv4vFctMC0YrgcZmlaUvxgXAeomHoxQrJK9LFTGl07TCJ9+i n4LJ1gLlvoKKmTjP1FJRVD/n9oqjvDLyhSHZOfn/cy+5vGOVRpm8TyEFui74vWzbs/pq Qvune/P06c7AHGuwrPlIvrlt6gjBY0BWySQARKY71byPzgM3/RuG/lg4nrK1lA3XrPdX p1i/kB2RToR44Pj0jExsiuRxE9Lut3CF8Oz8C4lXKkRnPxEU6ppmb6xmFli64n+3pc5D GFbQ== X-Gm-Message-State: AC+VfDxLNGdowL6tHAhU5RdiRVqmcDCJNfA/uWZxkyfZA/Q0EtqRci7g RMMAk7boPh/OnXejiq3qhPQ= X-Google-Smtp-Source: ACHHUZ681CkprnN+PnfFwou1vy3oW/3SYrpP7yKOkM9VljtTjTR/9pSDCq4Yp2i9BWpKWV0sPzdLVQ== X-Received: by 2002:ad4:5aeb:0:b0:61a:43f0:7305 with SMTP id c11-20020ad45aeb000000b0061a43f07305mr1682385qvh.35.1682968871742; Mon, 01 May 2023 12:21:11 -0700 (PDT) From: Jason Andryuk To: xen-devel@lists.xenproj, xen-devel@lists.xenproject.org Cc: Jason Andryuk , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v3 04/14] cpufreq: Add Hardware P-State (HWP) driver Date: Mon, 1 May 2023 15:20:35 -0400 Message-Id: <20230501192045.87377-5-jandryuk@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501192045.87377-1-jandryuk@gmail.com> References: <20230501192045.87377-1-jandryuk@gmail.com> MIME-Version: 1.0 From the Intel SDM: "Hardware-Controlled Performance States (HWP), which autonomously selects performance states while utilizing OS supplied performance guidance hints." Enable HWP to run in autonomous mode by poking the correct MSRs. cpufreq=xen:hwp enables and cpufreq=xen:hwp=0 disables. The same for hdc. There is no interface to configure - xen_sysctl_pm_op/xenpm will be to be extended to configure in subsequent patches. It will run with the default values, which should be the default 0x80 (out of 0x0-0xff) energy/performance preference. Unscientific powertop measurement of an mostly idle, customized OpenXT install: A 10th gen 6-core laptop showed battery discharge drop from ~9.x to ~7.x watts. A 8th gen 4-core laptop dropped from ~10 to ~9 Power usage depends on many factors, especially display brightness, but this does show an power saving in balanced mode when CPU utilization is low. HWP isn't compatible with an external governor - it doesn't take explicit frequency requests. Therefore a minimal internal governor, hwp-internal, is also added as a placeholder. While adding to the xen-command-line.pandoc entry, un-nest verbose from minfreq. They are independent. Signed-off-by: Jason Andryuk --- We disable on cpuid_level < 0x16. cpuid(0x16) is used to get the cpu frequencies for calculating the APERF/MPERF. Without it, things would still work, but the averge cpufrequency output would be wrong. My 8th & 10th gen test systems both report: (XEN) HWP: 1 notify: 1 act_window: 1 energy_perf: 1 pkg_level: 0 peci: 0 (XEN) HWP: Hardware Duty Cycling (HDC) supported (XEN) HWP: HW_FEEDBACK not supported IA32_ENERGY_PERF_BIAS has not been tested. For cpufreq=xen:hwp, placing the option inside the governor wouldn't work. Users would have to select the hwp-internal governor to turn off hwp support. hwp-internal isn't usable without hwp, and users wouldn't be able to select a different governor. That doesn't matter while hwp defaults off, but it would if or when hwp defaults to enabled. We can't use parse_boolean() since it requires a single name=val string and cpufreq_handle_common_option is provided two strings. Use parse_bool() and manual handle no-hwp. Write to disable the interrupt - the linux pstate driver does this. We don't use the interrupts, so we can just turn them off. We aren't ready to handle them, so we don't want any. Unclear if this is necessary. SDM says it's default disabled. FAST_IA32_HWP_REQUEST was removed in v2. The check in v1 was wrong, it's a model specific feature and the CPUID bit is only available after enabling via the MSR. Support was untested since I don't have hardware with the feature. Writes are expected to be infrequent, so just leave it out. --- v2: Alphabetize headers Re-work driver registration name hwp_drv_data anonymous union "hw" Drop hwp_verbose_cont style cleanups Condense hwp_governor switch hwp_cpufreq_target remove .raw from hwp_req assignment Use typed-pointer in a few functions Pass type to xzalloc Add HWP_ENERGY_PERF_BALANCE/IA32_ENERGY_BIAS_BALANCE defines Add XEN_HWP_GOVERNOR define for "hwp-internal" Capitalize CPUID and MSR defines Change '_' to '-' for energy-perf & act-window Read-modify-write MSRs updates Use FAST_IA32_HWP_REQUEST_MSR_ENABLE define constify pointer in hwp_set_misc_turbo Add space after non-fallthrough break in governor switch Add IA32_ENERGY_BIAS_MASK define Check CPUID_PM_LEAK for energy bias when needed Fail initialization with curr_req = -1 Fold hwp_read_capabilities into hwp_init_msrs Add command line cpufreq=xen:hwp Add command line cpufreq=xen:hdc Use per_cpu for hwp_drv_data pointers Move hwp_energy_perf_bias call into hwp_write_request energy_perf 0 is valid, so hwp_energy_perf_bias cannot be skipped Ensure we don't generate interrupts Remove Fast Write of Uncore MSR Initialize hwp_drv_data from curr_req Use SPDX line instead of license text in hwp.c v3: Add cf_check to cpufreq_gov_hwp_init() - Marek Print cpuid_level with %#x - Marek --- docs/misc/xen-command-line.pandoc | 8 +- xen/arch/x86/acpi/cpufreq/Makefile | 1 + xen/arch/x86/acpi/cpufreq/cpufreq.c | 5 +- xen/arch/x86/acpi/cpufreq/hwp.c | 506 ++++++++++++++++++++++ xen/arch/x86/include/asm/cpufeature.h | 13 +- xen/arch/x86/include/asm/msr-index.h | 13 + xen/drivers/cpufreq/cpufreq.c | 32 ++ xen/include/acpi/cpufreq/cpufreq.h | 3 + xen/include/acpi/cpufreq/processor_perf.h | 3 + xen/include/public/sysctl.h | 1 + 10 files changed, 581 insertions(+), 4 deletions(-) create mode 100644 xen/arch/x86/acpi/cpufreq/hwp.c diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index e0b89b7d33..aaa31f444b 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -499,7 +499,7 @@ If set, force use of the performance counters for oprofile, rather than detectin available support. ### cpufreq -> `= none | {{ | xen } [:[powersave|performance|ondemand|userspace][,][,[][,[verbose]]]]} | dom0-kernel` +> `= none | {{ | xen } [:[powersave|performance|ondemand|userspace][,][,[]][,[]][,[]][,[verbose]]]} | dom0-kernel` > Default: `xen` @@ -510,6 +510,12 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels. * `` and `` are integers which represent max and min processor frequencies respectively. * `verbose` option can be included as a string or also as `verbose=` +* `` is a boolean to enable Hardware-Controlled Performance States (HWP) + on supported Intel hardware. HWP is a Skylake+ feature which provides better + CPU power management. The default is disabled. +* `` is a boolean to enable Hardware Duty Cycling (HDC). HDC enables the + processor to autonomously force physical package components into idle state. + The default is enabled, but the option only applies when `` is enabled. ### cpuid (x86) > `= List of comma separated booleans` diff --git a/xen/arch/x86/acpi/cpufreq/Makefile b/xen/arch/x86/acpi/cpufreq/Makefile index f75da9b9ca..db83aa6b14 100644 --- a/xen/arch/x86/acpi/cpufreq/Makefile +++ b/xen/arch/x86/acpi/cpufreq/Makefile @@ -1,2 +1,3 @@ obj-y += cpufreq.o +obj-y += hwp.o obj-y += powernow.o diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c index f1cc473b4f..56816b1aee 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -642,7 +642,10 @@ static int __init cf_check cpufreq_driver_init(void) switch ( boot_cpu_data.x86_vendor ) { case X86_VENDOR_INTEL: - ret = cpufreq_register_driver(&acpi_cpufreq_driver); + if ( hwp_available() ) + ret = hwp_register_driver(); + else + ret = cpufreq_register_driver(&acpi_cpufreq_driver); break; case X86_VENDOR_AMD: diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hwp.c new file mode 100644 index 0000000000..57f13867d3 --- /dev/null +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -0,0 +1,506 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * hwp.c cpufreq driver to run Intel Hardware P-States (HWP) + * + * Copyright (C) 2021 Jason Andryuk + */ + +#include +#include +#include +#include +#include +#include +#include + +static bool feature_hwp; +static bool feature_hwp_notification; +static bool feature_hwp_activity_window; +static bool feature_hwp_energy_perf; +static bool feature_hwp_pkg_level_ctl; +static bool feature_hwp_peci; + +static bool feature_hdc; + +__initdata bool opt_cpufreq_hwp = false; +__initdata bool opt_cpufreq_hdc = true; + +#define HWP_ENERGY_PERF_BALANCE 0x80 +#define IA32_ENERGY_BIAS_BALANCE 0x7 +#define IA32_ENERGY_BIAS_MAX_POWERSAVE 0xf +#define IA32_ENERGY_BIAS_MASK 0xf + +union hwp_request +{ + struct + { + uint64_t min_perf:8; + uint64_t max_perf:8; + uint64_t desired:8; + uint64_t energy_perf:8; + uint64_t activity_window:10; + uint64_t package_control:1; + uint64_t reserved:16; + uint64_t activity_window_valid:1; + uint64_t energy_perf_valid:1; + uint64_t desired_valid:1; + uint64_t max_perf_valid:1; + uint64_t min_perf_valid:1; + }; + uint64_t raw; +}; + +struct hwp_drv_data +{ + union + { + uint64_t hwp_caps; + struct + { + uint64_t highest:8; + uint64_t guaranteed:8; + uint64_t most_efficient:8; + uint64_t lowest:8; + uint64_t reserved:32; + } hw; + }; + union hwp_request curr_req; + uint16_t activity_window; + uint8_t minimum; + uint8_t maximum; + uint8_t desired; + uint8_t energy_perf; +}; +DEFINE_PER_CPU_READ_MOSTLY(struct hwp_drv_data *, hwp_drv_data); + +#define hwp_err(...) printk(XENLOG_ERR __VA_ARGS__) +#define hwp_info(...) printk(XENLOG_INFO __VA_ARGS__) +#define hwp_verbose(...) \ +({ \ + if ( cpufreq_verbose ) \ + printk(XENLOG_DEBUG __VA_ARGS__); \ +}) + +static int cf_check hwp_governor(struct cpufreq_policy *policy, + unsigned int event) +{ + int ret; + + if ( policy == NULL ) + return -EINVAL; + + switch ( event ) + { + case CPUFREQ_GOV_START: + case CPUFREQ_GOV_LIMITS: + ret = 0; + break; + + case CPUFREQ_GOV_STOP: + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static struct cpufreq_governor hwp_cpufreq_governor = +{ + .name = XEN_HWP_GOVERNOR, + .governor = hwp_governor, +}; + +static int __init cf_check cpufreq_gov_hwp_init(void) +{ + return cpufreq_register_governor(&hwp_cpufreq_governor); +} +__initcall(cpufreq_gov_hwp_init); + +bool __init hwp_available(void) +{ + unsigned int eax, ecx, unused; + bool use_hwp; + + if ( boot_cpu_data.cpuid_level < CPUID_PM_LEAF ) + { + hwp_verbose("cpuid_level (%#x) lacks HWP support\n", + boot_cpu_data.cpuid_level); + return false; + } + + if ( boot_cpu_data.cpuid_level < 0x16 ) + { + hwp_info("HWP disabled: cpuid_level %#x < 0x16 lacks CPU freq info\n", + boot_cpu_data.cpuid_level); + return false; + } + + cpuid(CPUID_PM_LEAF, &eax, &unused, &ecx, &unused); + + if ( !(eax & CPUID6_EAX_HWP_ENERGY_PERFORMANCE_PREFERENCE) && + !(ecx & CPUID6_ECX_IA32_ENERGY_PERF_BIAS) ) + { + hwp_verbose("HWP disabled: No energy/performance preference available"); + return false; + } + + feature_hwp = eax & CPUID6_EAX_HWP; + feature_hwp_notification = eax & CPUID6_EAX_HWP_NOTIFICATION; + feature_hwp_activity_window = eax & CPUID6_EAX_HWP_ACTIVITY_WINDOW; + feature_hwp_energy_perf = + eax & CPUID6_EAX_HWP_ENERGY_PERFORMANCE_PREFERENCE; + feature_hwp_pkg_level_ctl = eax & CPUID6_EAX_HWP_PACKAGE_LEVEL_REQUEST; + feature_hwp_peci = eax & CPUID6_EAX_HWP_PECI; + + hwp_verbose("HWP: %d notify: %d act-window: %d energy-perf: %d pkg-level: %d peci: %d\n", + feature_hwp, feature_hwp_notification, + feature_hwp_activity_window, feature_hwp_energy_perf, + feature_hwp_pkg_level_ctl, feature_hwp_peci); + + if ( !feature_hwp ) + return false; + + feature_hdc = eax & CPUID6_EAX_HDC; + + hwp_verbose("HWP: Hardware Duty Cycling (HDC) %ssupported%s\n", + feature_hdc ? "" : "not ", + feature_hdc ? opt_cpufreq_hdc ? ", enabled" : ", disabled" + : ""); + + feature_hdc = feature_hdc && opt_cpufreq_hdc; + + hwp_verbose("HWP: HW_FEEDBACK %ssupported\n", + (eax & CPUID6_EAX_HW_FEEDBACK) ? "" : "not "); + + use_hwp = feature_hwp && opt_cpufreq_hwp; + cpufreq_governor_internal = use_hwp; + + if ( use_hwp ) + hwp_info("Using HWP for cpufreq\n"); + + return use_hwp; +} + +static void hdc_set_pkg_hdc_ctl(bool val) +{ + uint64_t msr; + + if ( rdmsr_safe(MSR_IA32_PKG_HDC_CTL, msr) ) + { + hwp_err("error rdmsr_safe(MSR_IA32_PKG_HDC_CTL)\n"); + + return; + } + + if ( val ) + msr |= IA32_PKG_HDC_CTL_HDC_PKG_ENABLE; + else + msr &= ~IA32_PKG_HDC_CTL_HDC_PKG_ENABLE; + + if ( wrmsr_safe(MSR_IA32_PKG_HDC_CTL, msr) ) + hwp_err("error wrmsr_safe(MSR_IA32_PKG_HDC_CTL): %016lx\n", msr); +} + +static void hdc_set_pm_ctl1(bool val) +{ + uint64_t msr; + + if ( rdmsr_safe(MSR_IA32_PM_CTL1, msr) ) + { + hwp_err("error rdmsr_safe(MSR_IA32_PM_CTL1)\n"); + + return; + } + + if ( val ) + msr |= IA32_PM_CTL1_HDC_ALLOW_BLOCK; + else + msr &= ~IA32_PM_CTL1_HDC_ALLOW_BLOCK; + + if ( wrmsr_safe(MSR_IA32_PM_CTL1, msr) ) + hwp_err("error wrmsr_safe(MSR_IA32_PM_CTL1): %016lx\n", msr); +} + +static void hwp_get_cpu_speeds(struct cpufreq_policy *policy) +{ + uint32_t base_khz, max_khz, bus_khz, edx; + + cpuid(0x16, &base_khz, &max_khz, &bus_khz, &edx); + + /* aperf/mperf scales base. */ + policy->cpuinfo.perf_freq = base_khz * 1000; + policy->cpuinfo.min_freq = base_khz * 1000; + policy->cpuinfo.max_freq = max_khz * 1000; + policy->min = base_khz * 1000; + policy->max = max_khz * 1000; + policy->cur = 0; +} + +static void cf_check hwp_init_msrs(void *info) +{ + struct cpufreq_policy *policy = info; + struct hwp_drv_data *data = this_cpu(hwp_drv_data); + uint64_t val; + + /* + * Package level MSR, but we don't have a good idea of packages here, so + * just do it everytime. + */ + if ( rdmsr_safe(MSR_IA32_PM_ENABLE, val) ) + { + hwp_err("CPU%u: error rdmsr_safe(MSR_IA32_PM_ENABLE)\n", policy->cpu); + data->curr_req.raw = -1; + return; + } + + /* Ensure we don't generate interrupts */ + if ( feature_hwp_notification ) + wrmsr_safe(MSR_IA32_HWP_INTERRUPT, 0); + + hwp_verbose("CPU%u: MSR_IA32_PM_ENABLE: %016lx\n", policy->cpu, val); + if ( !(val & IA32_PM_ENABLE_HWP_ENABLE) ) + { + val |= IA32_PM_ENABLE_HWP_ENABLE; + if ( wrmsr_safe(MSR_IA32_PM_ENABLE, val) ) + { + hwp_err("CPU%u: error wrmsr_safe(MSR_IA32_PM_ENABLE, %lx)\n", + policy->cpu, val); + data->curr_req.raw = -1; + return; + } + } + + if ( rdmsr_safe(MSR_IA32_HWP_CAPABILITIES, data->hwp_caps) ) + { + hwp_err("CPU%u: error rdmsr_safe(MSR_IA32_HWP_CAPABILITIES)\n", + policy->cpu); + data->curr_req.raw = -1; + return; + } + + if ( rdmsr_safe(MSR_IA32_HWP_REQUEST, data->curr_req.raw) ) + { + hwp_err("CPU%u: error rdmsr_safe(MSR_IA32_HWP_REQUEST)\n", policy->cpu); + data->curr_req.raw = -1; + return; + } + + if ( !feature_hwp_energy_perf ) { + if ( rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, val) ) + { + hwp_err("error rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS)\n"); + data->curr_req.raw = -1; + + return; + } + + data->energy_perf = val & IA32_ENERGY_BIAS_MASK; + } + + /* + * Check for APERF/MPERF support in hardware + * also check for boost/turbo support + */ + intel_feature_detect(policy); + + if ( feature_hdc ) + { + hdc_set_pkg_hdc_ctl(true); + hdc_set_pm_ctl1(true); + } + + hwp_get_cpu_speeds(policy); +} + +static int cf_check hwp_cpufreq_verify(struct cpufreq_policy *policy) +{ + struct hwp_drv_data *data = per_cpu(hwp_drv_data, policy->cpu); + + if ( !feature_hwp_energy_perf && data->energy_perf ) + { + if ( data->energy_perf > IA32_ENERGY_BIAS_MAX_POWERSAVE ) + { + hwp_err("energy_perf %d exceeds IA32_ENERGY_PERF_BIAS range 0-15\n", + data->energy_perf); + + return -EINVAL; + } + } + + if ( !feature_hwp_activity_window && data->activity_window ) + { + hwp_err("HWP activity window not supported\n"); + + return -EINVAL; + } + + return 0; +} + +/* val 0 - highest performance, 15 - maximum energy savings */ +static void hwp_energy_perf_bias(const struct hwp_drv_data *data) +{ + uint64_t msr; + uint8_t val = data->energy_perf; + + ASSERT(val <= IA32_ENERGY_BIAS_MAX_POWERSAVE); + + if ( rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, msr) ) + { + hwp_err("error rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS)\n"); + + return; + } + + msr &= ~IA32_ENERGY_BIAS_MASK; + msr |= val; + + if ( wrmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, msr) ) + hwp_err("error wrmsr_safe(MSR_IA32_ENERGY_PERF_BIAS): %016lx\n", msr); +} + +static void cf_check hwp_write_request(void *info) +{ + struct cpufreq_policy *policy = info; + struct hwp_drv_data *data = this_cpu(hwp_drv_data); + union hwp_request hwp_req = data->curr_req; + + BUILD_BUG_ON(sizeof(union hwp_request) != sizeof(uint64_t)); + if ( wrmsr_safe(MSR_IA32_HWP_REQUEST, hwp_req.raw) ) + { + hwp_err("CPU%u: error wrmsr_safe(MSR_IA32_HWP_REQUEST, %lx)\n", + policy->cpu, hwp_req.raw); + rdmsr_safe(MSR_IA32_HWP_REQUEST, data->curr_req.raw); + } + + if ( !feature_hwp_energy_perf ) + hwp_energy_perf_bias(data); + +} + +static int cf_check hwp_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int cpu = policy->cpu; + struct hwp_drv_data *data = per_cpu(hwp_drv_data, cpu); + /* Zero everything to ensure reserved bits are zero... */ + union hwp_request hwp_req = { .raw = 0 }; + + /* .. and update from there */ + hwp_req.min_perf = data->minimum; + hwp_req.max_perf = data->maximum; + hwp_req.desired = data->desired; + if ( feature_hwp_energy_perf ) + hwp_req.energy_perf = data->energy_perf; + if ( feature_hwp_activity_window ) + hwp_req.activity_window = data->activity_window; + + if ( hwp_req.raw == data->curr_req.raw ) + return 0; + + data->curr_req = hwp_req; + + hwp_verbose("CPU%u: wrmsr HWP_REQUEST %016lx\n", cpu, hwp_req.raw); + on_selected_cpus(cpumask_of(cpu), hwp_write_request, policy, 1); + + return 0; +} + +static int cf_check hwp_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + unsigned int cpu = policy->cpu; + struct hwp_drv_data *data; + + data = xzalloc(struct hwp_drv_data); + if ( !data ) + return -ENOMEM; + + if ( cpufreq_opt_governor ) + printk(XENLOG_WARNING + "HWP: governor \"%s\" is incompatible with hwp. Using default \"%s\"\n", + cpufreq_opt_governor->name, hwp_cpufreq_governor.name); + policy->governor = &hwp_cpufreq_governor; + + per_cpu(hwp_drv_data, cpu) = data; + + on_selected_cpus(cpumask_of(cpu), hwp_init_msrs, policy, 1); + + if ( data->curr_req.raw == -1 ) + { + hwp_err("CPU%u: Could not initialize HWP properly\n", cpu); + XFREE(per_cpu(hwp_drv_data, cpu)); + return -ENODEV; + } + + data->minimum = data->curr_req.min_perf; + data->maximum = data->curr_req.max_perf; + data->desired = data->curr_req.desired; + /* the !feature_hwp_energy_perf case was handled in hwp_init_msrs(). */ + if ( feature_hwp_energy_perf ) + data->energy_perf = data->curr_req.energy_perf; + + hwp_verbose("CPU%u: IA32_HWP_CAPABILITIES: %016lx\n", cpu, data->hwp_caps); + + hwp_verbose("CPU%u: rdmsr HWP_REQUEST %016lx\n", cpu, data->curr_req.raw); + + return 0; +} + +static int cf_check hwp_cpufreq_cpu_exit(struct cpufreq_policy *policy) +{ + XFREE(per_cpu(hwp_drv_data, policy->cpu)); + + return 0; +} + +/* + * The SDM reads like turbo should be disabled with MSR_IA32_PERF_CTL and + * PERF_CTL_TURBO_DISENGAGE, but that does not seem to actually work, at least + * with my HWP testing. MSR_IA32_MISC_ENABLE and MISC_ENABLE_TURBO_DISENGAGE + * is what Linux uses and seems to work. + */ +static void cf_check hwp_set_misc_turbo(void *info) +{ + const struct cpufreq_policy *policy = info; + uint64_t msr; + + if ( rdmsr_safe(MSR_IA32_MISC_ENABLE, msr) ) + { + hwp_err("CPU%u: error rdmsr_safe(MSR_IA32_MISC_ENABLE)\n", policy->cpu); + + return; + } + + if ( policy->turbo == CPUFREQ_TURBO_ENABLED ) + msr &= ~MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE; + else + msr |= MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE; + + if ( wrmsr_safe(MSR_IA32_MISC_ENABLE, msr) ) + hwp_err("CPU%u: error wrmsr_safe(MSR_IA32_MISC_ENABLE): %016lx\n", + policy->cpu, msr); +} + +static int cf_check hwp_cpufreq_update(int cpuid, struct cpufreq_policy *policy) +{ + on_selected_cpus(cpumask_of(cpuid), hwp_set_misc_turbo, policy, 1); + + return 0; +} + +static const struct cpufreq_driver __initconstrel hwp_cpufreq_driver = +{ + .name = "hwp-cpufreq", + .verify = hwp_cpufreq_verify, + .target = hwp_cpufreq_target, + .init = hwp_cpufreq_cpu_init, + .exit = hwp_cpufreq_cpu_exit, + .update = hwp_cpufreq_update, +}; + +int __init hwp_register_driver(void) +{ + return cpufreq_register_driver(&hwp_cpufreq_driver); +} diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 4140ec0938..f2ff1d5fde 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -46,8 +46,17 @@ extern struct cpuinfo_x86 boot_cpu_data; #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) -#define CPUID_PM_LEAF 6 -#define CPUID6_ECX_APERFMPERF_CAPABILITY 0x1 +#define CPUID_PM_LEAF 6 +#define CPUID6_EAX_HWP (_AC(1, U) << 7) +#define CPUID6_EAX_HWP_NOTIFICATION (_AC(1, U) << 8) +#define CPUID6_EAX_HWP_ACTIVITY_WINDOW (_AC(1, U) << 9) +#define CPUID6_EAX_HWP_ENERGY_PERFORMANCE_PREFERENCE (_AC(1, U) << 10) +#define CPUID6_EAX_HWP_PACKAGE_LEVEL_REQUEST (_AC(1, U) << 11) +#define CPUID6_EAX_HDC (_AC(1, U) << 13) +#define CPUID6_EAX_HWP_PECI (_AC(1, U) << 16) +#define CPUID6_EAX_HW_FEEDBACK (_AC(1, U) << 19) +#define CPUID6_ECX_APERFMPERF_CAPABILITY 0x1 +#define CPUID6_ECX_IA32_ENERGY_PERF_BIAS 0x8 /* CPUID level 0x00000001.edx */ #define cpu_has_fpu 1 diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index fa771ed0b5..a2a22339e4 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -151,6 +151,13 @@ #define MSR_PKRS 0x000006e1 +#define MSR_IA32_PM_ENABLE 0x00000770 +#define IA32_PM_ENABLE_HWP_ENABLE (_AC(1, ULL) << 0) + +#define MSR_IA32_HWP_CAPABILITIES 0x00000771 +#define MSR_IA32_HWP_INTERRUPT 0x00000773 +#define MSR_IA32_HWP_REQUEST 0x00000774 + #define MSR_X2APIC_FIRST 0x00000800 #define MSR_X2APIC_LAST 0x000008ff @@ -165,6 +172,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_IA32_PKG_HDC_CTL 0x00000db0 +#define IA32_PKG_HDC_CTL_HDC_PKG_ENABLE (_AC(1, ULL) << 0) +#define MSR_IA32_PM_CTL1 0x00000db1 +#define IA32_PM_CTL1_HDC_ALLOW_BLOCK (_AC(1, ULL) << 0) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) @@ -500,6 +512,7 @@ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) +#define MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE (1ULL << 38) #define MSR_IA32_TSC_DEADLINE 0x000006E0 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 7bd81680da..9470eb7230 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -565,6 +565,38 @@ static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy) static int __init cpufreq_handle_common_option(const char *name, const char *val) { + if (!strcmp(name, "hdc")) { + if (val) { + int ret = parse_bool(val, NULL); + if (ret != -1) { + opt_cpufreq_hdc = ret; + return 1; + } + } else { + opt_cpufreq_hdc = true; + return 1; + } + } else if (!strcmp(name, "no-hdc")) { + opt_cpufreq_hdc = false; + return 1; + } + + if (!strcmp(name, "hwp")) { + if (val) { + int ret = parse_bool(val, NULL); + if (ret != -1) { + opt_cpufreq_hwp = ret; + return 1; + } + } else { + opt_cpufreq_hwp = true; + return 1; + } + } else if (!strcmp(name, "no-hwp")) { + opt_cpufreq_hwp = false; + return 1; + } + if (!strcmp(name, "maxfreq") && val) { usr_max_freq = simple_strtoul(val, NULL, 0); return 1; diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index 0f334d2a43..29a712a4f1 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -245,4 +245,7 @@ void cpufreq_dbs_timer_resume(void); void intel_feature_detect(struct cpufreq_policy *policy); +extern bool opt_cpufreq_hwp; +extern bool opt_cpufreq_hdc; + #endif /* __XEN_CPUFREQ_PM_H__ */ diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h index d8a1ba68a6..b751ca4937 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -7,6 +7,9 @@ #define XEN_PX_INIT 0x80000000 +bool hwp_available(void); +int hwp_register_driver(void); + int powernow_cpufreq_init(void); unsigned int powernow_register_driver(void); unsigned int get_measured_perf(unsigned int cpu, unsigned int flag); diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 2b24d6bfd0..b448f13b75 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -292,6 +292,7 @@ struct xen_ondemand { uint32_t up_threshold; }; +#define XEN_HWP_GOVERNOR "hwp-internal" /* * cpufreq para name of this structure named * same as sysfs file name of native linux From patchwork Mon May 1 19:20:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Andryuk X-Patchwork-Id: 13227916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87DE8C7EE24 for ; Mon, 1 May 2023 19:21:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.528066.820656 (Exim 4.92) (envelope-from ) id 1ptZ5L-0004K9-Ej; Mon, 01 May 2023 19:21:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 528066.820656; Mon, 01 May 2023 19:21:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5L-0004Jy-Bi; Mon, 01 May 2023 19:21:19 +0000 Received: by outflank-mailman (input) for mailman id 528066; Mon, 01 May 2023 19:21:18 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ptZ5J-0003yM-Vk for xen-devel@lists.xenproject.org; Mon, 01 May 2023 19:21:17 +0000 Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [2607:f8b0:4864:20::732]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 57a16940-e855-11ed-8611-37d641c3527e; Mon, 01 May 2023 21:21:16 +0200 (CEST) Received: by mail-qk1-x732.google.com with SMTP id af79cd13be357-74cebbb7bc5so275654785a.3 for ; Mon, 01 May 2023 12:21:16 -0700 (PDT) Received: from pm2-ws13.praxislan02.com (207-172-141-204.s8906.c3-0.slvr-cbr1.lnh-slvr.md.cable.rcncustomer.com. [207.172.141.204]) by smtp.gmail.com with ESMTPSA id x20-20020a0ce0d4000000b0061927ddb043sm2012307qvk.80.2023.05.01.12.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 May 2023 12:21:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 57a16940-e855-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682968875; x=1685560875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hA8U/InM9EEJxsTtEJ4pQE8Dle8MV2Sm7m6DjaGLFBw=; b=alyW1WnDxf9gWpn/iywDsDjWYtiNrb58353i+DD9++Cpa7YDvVl5EOnhjOr7qgZ6B0 RWo7oakWLr32hdtu25e0yXhddgGem81Abc9u1tiXk5BSZKu9Wn4LnZnWqohDt7U0OIRP 1Vwij9eGmo0DPTDjtZAwVPzsmENXo5NCzFBn/pjPxkfGWiKoaKf2iMk1WNC0jNaA7qWV 5fkIkwLkHB2hIGp6CrRnnNLwyp+Sw/3+BpQifdRz+2gZsR4C4IEGgAwG74R7Qe73+Joe 6nZzkXBWog45V7Zpne/TjUOKDbRKSCzjxi67JcYxqhIWy/iklXt+xS1d0TB15rJvRp0s 7//A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682968875; x=1685560875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hA8U/InM9EEJxsTtEJ4pQE8Dle8MV2Sm7m6DjaGLFBw=; b=TV5WbagDmYG46TWa0zSQzYbBrHe77J89qcyOIBUz0gUDwJktRj9fNkg5SHYC5b7a0Q TtaRRqW2TtQ58O0ffKPQAVeasdCM93z4H9EOtUIRLxxHgpDFDbvvYWURkhYTiI86FvAb tt6SnTSa0oPWgp5yCD/0qObyhzYT/i3dCyKL6FlEqGHkrczypp8M91JyYpn9Ac7PQDyQ TVUezSWCS73RjRt/GK2Wi9bSbQ0nLvUjyx9rLkuzsuH1KOlVh7/1GV+T0KE7ap3w2o5G 1SXPdD5wh/0JGamIYlzogbnmWs0D2w9R6vmdZZE+h9u4obiAbsA3Fvu2C12X7GlCVTt4 SVBg== X-Gm-Message-State: AC+VfDx9ah8A7JlM4jEGXY8MXpgaz980oA3gO4S4uDmAgGUqJEdSFAu3 uEwnBK6uzL5rLubheIVipRQ= X-Google-Smtp-Source: ACHHUZ7Si1N+KuQIyeuzpeF6TE80Hpb0MgsDrxMePO6KWSxcK6U33V2aUW4c9/8oenuaGAK3spl/eQ== X-Received: by 2002:a05:6214:2a49:b0:5f5:51c4:fca5 with SMTP id jf9-20020a0562142a4900b005f551c4fca5mr1614591qvb.49.1682968875262; Mon, 01 May 2023 12:21:15 -0700 (PDT) From: Jason Andryuk To: xen-devel@lists.xenproj, xen-devel@lists.xenproject.org Cc: Jason Andryuk , Wei Liu , Anthony PERARD Subject: [PATCH v3 05/14] xenpm: Change get-cpufreq-para output for internal Date: Mon, 1 May 2023 15:20:36 -0400 Message-Id: <20230501192045.87377-6-jandryuk@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501192045.87377-1-jandryuk@gmail.com> References: <20230501192045.87377-1-jandryuk@gmail.com> MIME-Version: 1.0 When using HWP, some of the returned data is not applicable. In that case, we should just omit it to avoid confusing the user. So switch to printing the base and turbo frequencies since those are relevant to HWP. Similarly, stop printing the CPU frequencies since those do not apply. Signed-off-by: Jason Andryuk --- v2: Use full governor name XEN_HWP_GOVERNOR to change output Style fixes --- tools/misc/xenpm.c | 41 +++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 1bb6187e56..ce8d7644d0 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -711,6 +711,7 @@ void start_gather_func(int argc, char *argv[]) /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) { + bool internal = strstr(p_cpufreq->scaling_governor, XEN_HWP_GOVERNOR); int i; printf("cpu id : %d\n", cpuid); @@ -720,10 +721,15 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) printf(" %d", p_cpufreq->affected_cpus[i]); printf("\n"); - printf("cpuinfo frequency : max [%u] min [%u] cur [%u]\n", - p_cpufreq->cpuinfo_max_freq, - p_cpufreq->cpuinfo_min_freq, - p_cpufreq->cpuinfo_cur_freq); + if ( internal ) + printf("cpuinfo frequency : base [%u] turbo [%u]\n", + p_cpufreq->cpuinfo_min_freq, + p_cpufreq->cpuinfo_max_freq); + else + printf("cpuinfo frequency : max [%u] min [%u] cur [%u]\n", + p_cpufreq->cpuinfo_max_freq, + p_cpufreq->cpuinfo_min_freq, + p_cpufreq->cpuinfo_cur_freq); printf("scaling_driver : %s\n", p_cpufreq->scaling_driver); @@ -750,19 +756,22 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) p_cpufreq->u.ondemand.up_threshold); } - printf("scaling_avail_freq :"); - for ( i = 0; i < p_cpufreq->freq_num; i++ ) - if ( p_cpufreq->scaling_available_frequencies[i] == - p_cpufreq->scaling_cur_freq ) - printf(" *%d", p_cpufreq->scaling_available_frequencies[i]); - else - printf(" %d", p_cpufreq->scaling_available_frequencies[i]); - printf("\n"); + if ( !internal ) + { + printf("scaling_avail_freq :"); + for ( i = 0; i < p_cpufreq->freq_num; i++ ) + if ( p_cpufreq->scaling_available_frequencies[i] == + p_cpufreq->scaling_cur_freq ) + printf(" *%d", p_cpufreq->scaling_available_frequencies[i]); + else + printf(" %d", p_cpufreq->scaling_available_frequencies[i]); + printf("\n"); - printf("scaling frequency : max [%u] min [%u] cur [%u]\n", - p_cpufreq->scaling_max_freq, - p_cpufreq->scaling_min_freq, - p_cpufreq->scaling_cur_freq); + printf("scaling frequency : max [%u] min [%u] cur [%u]\n", + p_cpufreq->scaling_max_freq, + p_cpufreq->scaling_min_freq, + p_cpufreq->scaling_cur_freq); + } printf("turbo mode : %s\n", p_cpufreq->turbo_enabled ? "enabled" : "disabled or n/a");