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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id j8-20020adff008000000b002f6176cc6desm31715295wro.110.2023.05.02.11.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 11:57:46 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH 1/3] target/openrisc: Allow fpcsr access in user mode Date: Tue, 2 May 2023 19:57:29 +0100 Message-Id: <20230502185731.3543420-2-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230502185731.3543420-1-shorne@gmail.com> References: <20230502185731.3543420-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=shorne@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per OpenRISC spec 1.4 FPCSR can be read and written in user mode. Update mtspr and mfspr helpers to support this by moving the is_user check into the helper. There is a logic change here to no longer throw an illegal instruction exception when executing mtspr/mfspr in user mode. The illegal instruction exception is not part of the spec, so this should be OK. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 45 +++++++++++++++++----- target/openrisc/translate.c | 72 ++++++++++++++++-------------------- 2 files changed, 67 insertions(+), 50 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ec145960e3..8a0259c710 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -29,17 +29,37 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) +static inline bool is_user(CPUOpenRISCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->sr & SR_SM) == 0; +#endif +} + void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = env_archcpu(env); +#ifndef CONFIG_USER_ONLY CPUState *cs = env_cpu(env); target_ulong mr; int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + cpu_set_fpcsr(env, rb); + return; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -187,12 +207,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_openrisc_timer_update(cpu); qemu_mutex_unlock_iothread(); break; -#endif - - case TO_SPR(0, 20): /* FPCSR */ - cpu_set_fpcsr(env, rb); - break; } +#endif } target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, @@ -204,10 +220,22 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, OpenRISCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); int idx; +#else + OpenRISCCPU *cpu = env_archcpu(env); #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + return env->fpcsr; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 0): /* VR */ return env->vr; @@ -324,11 +352,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, cpu_openrisc_count_update(cpu); qemu_mutex_unlock_iothread(); return cpu_openrisc_count_get(cpu); -#endif - - case TO_SPR(0, 20): /* FPCSR */ - return env->fpcsr; } +#endif /* for rd is passed in, if rd unchanged, just keep it back. */ return rd; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 76e53c78d4..43ba0cc1ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - check_r0_write(dc, a->d); - - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr = tcg_temp_new(); - - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); - } - dc->base.is_jmp = DISAS_EXIT; - } + TCGv spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); - } - return true; -} - -static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) -{ - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr; + check_r0_write(dc, a->d); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - /* For SR, we will need to exit the TB to recognize the new - * exception state. For NPC, in theory this counts as a branch - * (although the SPR only exists for use by an ICE). Save all - * of the cpu state first, allowing it to be overwritten. - */ + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp = DISAS_EXIT; + } + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); + return true; +} + +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) +{ + TCGv spr = tcg_temp_new(); - spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); } + /* + * For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); return true; } From patchwork Tue May 2 18:57:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13229230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82A89C7EE22 for ; Tue, 2 May 2023 18:58:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ptvCF-00053g-0T; Tue, 02 May 2023 14:57:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ptvCD-00052q-58 for qemu-devel@nongnu.org; Tue, 02 May 2023 14:57:53 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ptvCB-0002BS-L6 for qemu-devel@nongnu.org; Tue, 02 May 2023 14:57:52 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3062db220a3so1767423f8f.0 for ; Tue, 02 May 2023 11:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683053869; x=1685645869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XWQ/Z9BlPUubmldvNXKKW220gK42PZJS+hO6IM/QHuo=; b=hPf05h8ARyAkMITsL8o91UOAv2cXi1iHPKQpXrC41Cao96Zy1UnWm+nUuSw4n3i8NT JJEc8Y1BxYPQg3h0kULgoNFOES8Lv7BKm8r1AKRY+qVW38a2zNkhbKCozciHS+3uQym+ iq8oXc0kK+PvepCL68bnrpeRLD/Uq2pU/AwoyejUtaQ23Any4hmCUvoZNAksJcAP4s1f Xb0Cd0epBxVsSEbAQYZ5c6xx1AYB2FXFcujkM/2gNKq6e1oZ2xpW98LwhkqHWdc7nvO7 hTJLYXkR8Jbx/eZsvHfLQQbBqTZsU/GiFD0nWwC0C25sJaxjgZ98DbAcucaTypEXwLpS moPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683053869; x=1685645869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XWQ/Z9BlPUubmldvNXKKW220gK42PZJS+hO6IM/QHuo=; b=HahFAXhxnxtuMdn+HkveAlRtpNNdPv/SE+Zgy960tls3hnYkF7kBF6sretY4XllCXZ GIDVK7JNW6W3VrGwsmXNeNnx/HZ0AZNCl+zHUDBLfxX7X9vUuWcEVcijOXjkH8lwkmmx k9qp93c3dGhyCdINQU6aDnBweNQcj2JNIJuJog/CPk7NTilvly3g2IzOsn6EbvyzkWxt E4bclvH/347a3PjQahNc6OWqOwhskQgsn6TFbKSDxC3c4Yo5yN94lTz+Ytc7WLhspAcK MQ0lP5U6nCkbOI963qOZ8rGGJv0JD9C+aEqtyp7BIgUcoJIFntn1kb2IKzlfYSUp8LEw X/NQ== X-Gm-Message-State: AC+VfDyIyEDC7QfTJ+EKCE1kOzy9QCNR77qneRqmLErBJQ3mqRYr+OIf HPgU00yMymL+lnta3ccSha09uCGGxzY= X-Google-Smtp-Source: ACHHUZ5lhNppFFW3mrxRZ4Oz09TQIfOQGSIfePGoH7teb8eXrs1LQ0d4RmyrG/zLHGtpq4h3Jb9uUA== X-Received: by 2002:a5d:634e:0:b0:2fa:6929:eb81 with SMTP id b14-20020a5d634e000000b002fa6929eb81mr14018614wrw.31.1683053868763; Tue, 02 May 2023 11:57:48 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id m6-20020a5d6246000000b002feea065cc9sm31656202wrv.111.2023.05.02.11.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 11:57:48 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH 2/3] target/openrisc: Set PC to cpu state on FPU exception Date: Tue, 2 May 2023 19:57:30 +0100 Message-Id: <20230502185731.3543420-3-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230502185731.3543420-1-shorne@gmail.com> References: <20230502185731.3543420-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=shorne@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Store the PC to ensure the correct value can be read in the exception handler. Signed-off-by: Stafford Horne --- target/openrisc/fpu_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index f9e34fa2cc..1feebb9ac7 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" #include "fpu/softfloat.h" @@ -55,6 +56,9 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) if (tmp) { env->fpcsr |= tmp; if (env->fpcsr & FPCSR_FPEE) { + CPUState *cs = env_cpu(env); + + cpu_restore_state(cs, GETPC()); helper_exception(env, EXCP_FPE); } } From patchwork Tue May 2 18:57:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13229231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E94A8C77B78 for ; Tue, 2 May 2023 18:58:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ptvCG-00053v-2S; Tue, 02 May 2023 14:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ptvCD-00053F-Ic for qemu-devel@nongnu.org; Tue, 02 May 2023 14:57:53 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ptvCB-0002BY-Vp for qemu-devel@nongnu.org; Tue, 02 May 2023 14:57:53 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-2f6401ce8f8so2624738f8f.3 for ; Tue, 02 May 2023 11:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683053870; x=1685645870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jEF1qi6MMuB+c4HTiM42q+lLMXcDmiJq+W9maCZXnaA=; b=kDBHiS6FPPfleL2cXIDNRnVtSgSb+9dLs6tuBIuhecfoD2tL0SQrTJjrbz6rK2IrZF eWyWPOCTkF/UhEsGuH9PlUW/XFWSDDqmxJ9WMhQfQCuAmtCzUSm8VCFF1eX229r6lPFf zWpXa/Cm8zOiMRK6w7KNK1ahXt3xP+Grb2y4xBUH+SXK/wX514GJm6+j+rN86W1g4M12 9ofy4klE3UV83KQJoRiSv2X2d0ZJybE9SdLLybjW9RvG/r3ElmxQJapSgUXQx/sYSUSi 4CXNZsPDZtd20+kbHHu/LOceGk9bmYZ2SNLLG1P/F4G1vI/xhz7b1cxlVPVZJ7uFufQE Lngg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683053870; x=1685645870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jEF1qi6MMuB+c4HTiM42q+lLMXcDmiJq+W9maCZXnaA=; b=WjayGhSnleFZqVrlfEnmtrjFzKRdTHM7mRbLi5el2EKH+oxudKqguCPt2dVbStqFYN UuZuWDX3JA/4E0J3AGc47uuaxLKtgHhUB5+hXsMVXqXB0U1oXWiaK+ziK2GGCS+CklmE Nes687Nytlk3flIpCe3cY2wJqpM885oon4jwlahEWwjV5ZTzlBvyfPR1kIHaadMTcaVN i5SlonwYGBo0NMKgz9G4/e1R6PfN/xNjUPVN+XH1MRr/IFtDdmtIKuhhChNOAkpPRAlN REOueWiI+vY+j/nRmPlfTeoYiHSUHGdRszuJL3+vTjFN0ac5+F53LfCYCcjRAijJNHhu RP6A== X-Gm-Message-State: AC+VfDwZT+hiJV5yY5HbGZGnDLJBn8VNWUB/Xi4tBnE/IKrA0l0QPGPO NeFie+2ynAWPVc3P3BKHQcOI8if1onU= X-Google-Smtp-Source: ACHHUZ4S3dfBdfy774H5DOYO04fbZftVf7nnvy1feT14LQdwK+lxJm6piyX4Alhews/LsFoB0ERmbw== X-Received: by 2002:a5d:460f:0:b0:2d8:47c7:7b50 with SMTP id t15-20020a5d460f000000b002d847c77b50mr11827686wrq.1.1683053869896; Tue, 02 May 2023 11:57:49 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id u12-20020adfdd4c000000b0030635735a57sm3073320wrm.60.2023.05.02.11.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 11:57:49 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Date: Tue, 2 May 2023 19:57:31 +0100 Message-Id: <20230502185731.3543420-4-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230502185731.3543420-1-shorne@gmail.com> References: <20230502185731.3543420-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shorne@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..cdbff26fb5 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,10 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); + set_default_nan_mode(1, &cpu->env.fp_status); + set_float_detect_tininess(float_tininess_before_rounding, + &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000;