From patchwork Thu May 4 09:46:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Pouliquen X-Patchwork-Id: 13230972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 895E0C7EE21 for ; Thu, 4 May 2023 09:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pcVkUMpddjg0+sW6tbD4st0NjCFjqQ1QD0U4M99xpbc=; b=T+mIU2YvCde2D9 akUoISF8qjR7YMHX7rXACX38iiTtbFwq3bu6RHNnT4hcit8xvr7zlqeio2aY/Cjp288JOAhDIotdB bxOC3oOUvHvOfg+2pq6OrwlyTaXDHrvvkkLpPMkBSpHTSZBVpK9JFjEteHaGi8ZK0pbSEQHI/4D4m nN4rKyIFwTNcErn5jB1YVOK+ho0GRJKUu8TuDKl8MoIkydDvCzo5TZpPYb5At7tYA11NvAJGDOxyk LFrLNhaN3nmr8kwEuF1mmhqesXmX50hAHYJL9joCv843yetE5e04rLPx1xYkHsm3ADQGO9NULtsjc WQiD80EQjmwWylusxNqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1puVYb-007K3u-34; Thu, 04 May 2023 09:47:25 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1puVYV-007JzD-32 for linux-arm-kernel@lists.infradead.org; Thu, 04 May 2023 09:47:23 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3448eebR015762; Thu, 4 May 2023 11:46:54 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=AM1K4/BQXW0CuUZYLo3aJkmKe0XEgpleRDfLVkoedAI=; b=uZOIRkdOTl99BF7eO1RBUF+TjGa6A4pXBpyM1jSFlXg54mSviWfc87P4dl1Zub+BOJcx LMm+MHRQf57uvLtzs192j1NuQw0zqdB/URdPLvH6GcMPkMt2wpsWNMwDTJkm++BcuC3/ tlN6woxZWCb0zVkjn/udU+WgItBp/M5yg5C+B5+rsFkAAMwtDJX4LErIZUjCTseLVgeL vUdQxB/H27zwpL0giZyIh2ok5ME/+ZvwU+9YWnryqMWHaX0MxvAG5bizPq7LhkNm/7c9 o6e9Qt6q/VWoQmYg7IcMhuCc8uC7ZzGdRdTX5Z9n0UOLblXsyhNp67n5J/wbbk28A3ZW iA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3qc6uw9tde-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 May 2023 11:46:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 85370100034; Thu, 4 May 2023 11:46:52 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7BC0E214D07; Thu, 4 May 2023 11:46:52 +0200 (CEST) Received: from localhost (10.201.21.213) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 4 May 2023 11:46:52 +0200 From: Arnaud Pouliquen To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , Alexandre Torgue CC: , , , , , Arnaud Pouliquen Subject: [PATCH v2 1/4] dt-bindings: remoteproc: st,stm32-rproc: Rework reset declarations Date: Thu, 4 May 2023 11:46:38 +0200 Message-ID: <20230504094641.870378-2-arnaud.pouliquen@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> References: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.213] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-04_06,2023-05-03_01,2023-02-09_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_024720_481019_A03E2425 X-CRM114-Status: GOOD ( 18.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the introduction of the SCMI (System Control and Management Interface), it is now possible to use the SCMI to handle the hold boot instead of a dedicated SMC call. As consequence two configurations are possible: - without SCMI server on OP-TEE: use the Linux rcc reset service and use syscon for the MCU hold boot - With SCMI server on OP-TEE: use the SCMI reset service for both the MCU reset and the MCU hold boot. This patch: - make optional and deprecated the use of the property st,syscfg-tz which was used to check if the trusted Zone was enable to use scm call, to manage the hold boot. The reset controller phandle is used instead to select the configurations. - make st,syscfg-holdboot optional - adds properties check on resets definitions. - adds an example of the SCMI reset service usage. Signed-off-by: Arnaud Pouliquen --- Updates vs previous version: - do not suppress "st,syscfg-tz" property to keep legacy compatibility but set it as deprecated - remove "reset-name" from requested property for legacy compatibility --- .../bindings/remoteproc/st,stm32-rproc.yaml | 42 ++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 66b1e3efdaa3..93105d174279 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -25,7 +25,14 @@ properties: maxItems: 3 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + items: + - const: mcu_rst + - const: hold_boot + minItems: 1 st,syscfg-holdboot: description: remote processor reset hold boot @@ -37,6 +44,7 @@ properties: - description: The field mask of the hold boot st,syscfg-tz: + deprecated: true description: Reference to the system configuration which holds the RCC trust zone mode $ref: "/schemas/types.yaml#/definitions/phandle-array" @@ -135,22 +143,46 @@ required: - compatible - reg - resets - - st,syscfg-holdboot - - st,syscfg-tz + +allOf: + - if: + properties: + reset-names: + not: + contains: + const: hold_boot + then: + required: + - st,syscfg-holdboot + else: + properties: + st,syscfg-holdboot: false additionalProperties: false examples: - | #include - m4_rproc: m4@10000000 { + m4_rproc_example1: m4@10000000 { compatible = "st,stm32mp1-m4"; reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; + }; + - | + #include + m4_rproc_example2: m4@10000000 { + compatible = "st,stm32mp1-m4"; + reg = <0x10000000 0x40000>, + <0x30000000 0x40000>, + <0x38000000 0x10000>; + resets = <&scmi MCU_R>, <&scmi MCU_HOLD_BOOT_R>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; }; From patchwork Thu May 4 09:46:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Pouliquen X-Patchwork-Id: 13230973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A734C7EE22 for ; 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Thu, 04 May 2023 11:46:54 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C0DC0100038; Thu, 4 May 2023 11:46:53 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B91D82138F9; Thu, 4 May 2023 11:46:53 +0200 (CEST) Received: from localhost (10.201.21.213) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 4 May 2023 11:46:53 +0200 From: Arnaud Pouliquen To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , Alexandre Torgue CC: , , , , , Arnaud Pouliquen Subject: [PATCH v2 2/4] remoteproc: stm32: Allow hold boot management by the SCMI reset controller Date: Thu, 4 May 2023 11:46:39 +0200 Message-ID: <20230504094641.870378-3-arnaud.pouliquen@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> References: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.213] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-04_06,2023-05-03_01,2023-02-09_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_024720_462829_5CDB0324 X-CRM114-Status: GOOD ( 25.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The hold boot can be managed by the SCMI controller as a reset. If the "hold_boot" reset is defined in the device tree, use it. Else use the syscon controller directly to access to the register. The support of the SMC call is deprecated but kept for legacy support. Signed-off-by: Arnaud Pouliquen --- Updates vs previous version - keep support of the "st,syscfg-tz" property for legacy compatibility - rename secured_soc in hold_boot_smc for readability - add comments to explain hold boot management. - update commit message --- drivers/remoteproc/stm32_rproc.c | 78 +++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 21 deletions(-) diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c index 7d782ed9e589..e9cf24274345 100644 --- a/drivers/remoteproc/stm32_rproc.c +++ b/drivers/remoteproc/stm32_rproc.c @@ -79,6 +79,7 @@ struct stm32_mbox { struct stm32_rproc { struct reset_control *rst; + struct reset_control *hold_boot_rst; struct stm32_syscon hold_boot; struct stm32_syscon pdds; struct stm32_syscon m4_state; @@ -88,7 +89,7 @@ struct stm32_rproc { struct stm32_rproc_mem *rmems; struct stm32_mbox mb[MBOX_NB_MBX]; struct workqueue_struct *workqueue; - bool secured_soc; + bool hold_boot_smc; void __iomem *rsc_va; }; @@ -401,13 +402,28 @@ static int stm32_rproc_set_hold_boot(struct rproc *rproc, bool hold) struct arm_smccc_res smc_res; int val, err; + /* + * Three ways to manage the hold boot + * - using SCMI: the hold boot is managed as a reset, + * - using Linux(no SCMI): the hold boot is managed as a syscon register + * - using SMC call (deprecated): use SMC reset interface + */ + val = hold ? HOLD_BOOT : RELEASE_BOOT; - if (IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) && ddata->secured_soc) { + if (ddata->hold_boot_rst) { + /* Use the SCMI reset controller */ + if (!hold) + err = reset_control_deassert(ddata->hold_boot_rst); + else + err = reset_control_assert(ddata->hold_boot_rst); + } else if (IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) && ddata->hold_boot_smc) { + /* Use the SMC call */ arm_smccc_smc(STM32_SMC_RCC, STM32_SMC_REG_WRITE, hold_boot.reg, val, 0, 0, 0, 0, &smc_res); err = smc_res.a0; } else { + /* Use syscon */ err = regmap_update_bits(hold_boot.map, hold_boot.reg, hold_boot.mask, val); } @@ -705,34 +721,54 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev, dev_info(dev, "wdg irq registered\n"); } - ddata->rst = devm_reset_control_get_by_index(dev, 0); + ddata->rst = devm_reset_control_get_optional(dev, "mcu_rst"); + if (!ddata->rst) { + /* Try legacy fallback method: get it by index */ + ddata->rst = devm_reset_control_get_by_index(dev, 0); + } if (IS_ERR(ddata->rst)) return dev_err_probe(dev, PTR_ERR(ddata->rst), "failed to get mcu_reset\n"); /* - * if platform is secured the hold boot bit must be written by - * smc call and read normally. - * if not secure the hold boot bit could be read/write normally + * Three ways to manage the hold boot + * - using SCMI: the hold boot is managed as a reset + * The DT "reset-mames" property should be defined with 2 items: + * reset-names = "mcu_rst", "hold_boot"; + * - using SMC call (deprecated): use SMC reset interface + * The DT "reset-mames" property is optional, "st,syscfg-tz" is required + * - default(no SCMI, no SMC): the hold boot is managed as a syscon register + * The DT "reset-mames" property is optional, "st,syscfg-holdboot" is required */ - err = stm32_rproc_get_syscon(np, "st,syscfg-tz", &tz); - if (err) { - dev_err(dev, "failed to get tz syscfg\n"); - return err; - } - err = regmap_read(tz.map, tz.reg, &tzen); - if (err) { - dev_err(dev, "failed to read tzen\n"); - return err; + ddata->hold_boot_rst = devm_reset_control_get_optional(dev, "hold_boot"); + if (IS_ERR(ddata->hold_boot_rst)) { + if (PTR_ERR(ddata->hold_boot_rst) == -EPROBE_DEFER) + return PTR_ERR(ddata->hold_boot_rst); + ddata->hold_boot_rst = NULL; + } + + if (!ddata->hold_boot_rst && IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)) { + /* Manage the MCU_BOOT using SMC call */ + err = stm32_rproc_get_syscon(np, "st,syscfg-tz", &tz); + if (!err) { + err = regmap_read(tz.map, tz.reg, &tzen); + if (err) { + dev_err(dev, "failed to read tzen\n"); + return err; + } + ddata->hold_boot_smc = tzen & tz.mask; + } } - ddata->secured_soc = tzen & tz.mask; - err = stm32_rproc_get_syscon(np, "st,syscfg-holdboot", - &ddata->hold_boot); - if (err) { - dev_err(dev, "failed to get hold boot\n"); - return err; + if (!ddata->hold_boot_rst && !ddata->hold_boot_smc) { + /* Default: hold boot manage it through the syscon controller */ + err = stm32_rproc_get_syscon(np, "st,syscfg-holdboot", + &ddata->hold_boot); + if (err) { + dev_err(dev, "failed to get hold boot\n"); + return err; + } } err = stm32_rproc_get_syscon(np, "st,syscfg-pdds", &ddata->pdds); From patchwork Thu May 4 09:46:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Pouliquen X-Patchwork-Id: 13230971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B517C77B7C for ; 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Thu, 04 May 2023 11:47:09 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 984E810002A; Thu, 4 May 2023 11:46:55 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 90BE62138F9; Thu, 4 May 2023 11:46:55 +0200 (CEST) Received: from localhost (10.201.21.213) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 4 May 2023 11:46:54 +0200 From: Arnaud Pouliquen To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , Alexandre Torgue CC: , , , , , Arnaud Pouliquen Subject: [PATCH v2 3/4] ARM: dts: stm32: Update reset declarations Date: Thu, 4 May 2023 11:46:40 +0200 Message-ID: <20230504094641.870378-4-arnaud.pouliquen@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> References: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.213] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-04_06,2023-05-03_01,2023-02-09_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_024720_468377_7CA2A05E X-CRM114-Status: GOOD ( 16.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since the introduction of the SCMI for the management of the MCU hold boot in OP-TEE, management of the hold boot by SMC call is deprecated. - Clean the st,syscfg-tz which allows to determine if the trust zone is enable. - Add reset-names properties to be able to differentiate the MCU reset and the MCU HOLD BOOT. Signed-off-by: Arnaud Pouliquen --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4e437d3f2ed6..25626797db94 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1820,8 +1820,8 @@ m4_rproc: m4@10000000 { <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; From patchwork Thu May 4 09:46:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Pouliquen X-Patchwork-Id: 13230975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CFA3C7EE21 for ; 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Thu, 04 May 2023 11:46:56 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 20A50100034; Thu, 4 May 2023 11:46:56 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 18B882138F9; Thu, 4 May 2023 11:46:56 +0200 (CEST) Received: from localhost (10.201.21.213) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 4 May 2023 11:46:55 +0200 From: Arnaud Pouliquen To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , Alexandre Torgue CC: , , , , , Arnaud Pouliquen Subject: [PATCH v2 4/4] ARM: dts: stm32: fix m4_rproc references to use SCMI Date: Thu, 4 May 2023 11:46:41 +0200 Message-ID: <20230504094641.870378-5-arnaud.pouliquen@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> References: <20230504094641.870378-1-arnaud.pouliquen@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.213] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-04_06,2023-05-03_01,2023-02-09_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_024720_463093_AE5B8E38 X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fixes stm32mp15*-scmi DTS files introduced in [1]: This patch fixes the node which uses the MCU reset and adds the missing HOLD_BOOT which is also handled by the SCMI reset service. This change cannot be applied as a fix on commit [1], the management of the hold boot impacts also the stm32_rproc driver. [1] 'commit 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)")' Signed-off-by: Arnaud Pouliquen --- arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 6 ++++-- arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 6 ++++-- arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 6 ++++-- arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 6 ++++-- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts index e539cc80bef8..134788e64265 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -55,8 +55,10 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts index 97e4f94b0a24..c42e658debfb 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -61,8 +61,10 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts index 9cf0a44d2f47..7a56ff2d4185 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -60,8 +60,10 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts index 3b9dd6f4ccc9..119874dd91e4 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -66,8 +66,10 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc {