From patchwork Sat May 6 00:58:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBEEFC77B7C for ; Sat, 6 May 2023 00:58:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1AD710E110; Sat, 6 May 2023 00:58:18 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5962610E0EF for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=6oW85SpGDfDfq6pKZoK8SOv1j6IpvbASX/75vVHhjTQ=; b=WiuDyQVYwhsKGiR1yEGXhnR8eUI7zlv410xOm8B/sd7/mCuYmHCm/tGh u7cMgmUwl/DrA2JN/6c8VdsX+4P8bZN7nDk5yvVxhU2N+ltIzInTvA3gQ DkwRwh8QbIZHlIEnlfNnKcfvz/JStCoyFTKXe0d0tPfUaAXQgKhfOxd3L JO4YQ+6L+oEYDpZ0XwdT069uJN+9lHlA5NXqj+QRlVtELUsDSvf1KDQa4 uoz/IpvI8HDORdpSeIwwtwBMeOqML1gqraXAl6Yk5QWiFs++0KQRiSCh1 cDoXGBpX414UYItaGu8M5uaFp8qEGzGpZRIfTz9dn6ZTfL7xnyNJvcObO w==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408311" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408311" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326027" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326027" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:16 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:11 -0700 Message-Id: <20230506005816.1891043-2-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Given how the metrics are already exported, we also need to run sampling over engines from all GTs. Problem of GT frequencies is left for later. Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 7ece883a7d95..67fa6cd77529 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -10,6 +10,7 @@ #include "gt/intel_engine_pm.h" #include "gt/intel_engine_regs.h" #include "gt/intel_engine_user.h" +#include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_gt_regs.h" #include "gt/intel_rc6.h" @@ -414,8 +415,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) struct drm_i915_private *i915 = container_of(hrtimer, struct drm_i915_private, pmu.timer); struct i915_pmu *pmu = &i915->pmu; - struct intel_gt *gt = to_gt(i915); unsigned int period_ns; + struct intel_gt *gt; + unsigned int i; ktime_t now; if (!READ_ONCE(pmu->timer_enabled)) @@ -431,8 +433,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) * grabbing the forcewake. However the potential error from timer call- * back delay greatly dominates this so we keep it simple. */ - engines_sample(gt, period_ns); - frequency_sample(gt, period_ns); + + for_each_gt(gt, i915, i) { + engines_sample(gt, period_ns); + + if (i == 0) /* FIXME */ + frequency_sample(gt, period_ns); + } hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD)); From patchwork Sat May 6 00:58:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1F4DC77B75 for ; Sat, 6 May 2023 00:58:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A817010E0EB; Sat, 6 May 2023 00:58:18 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 707BF10E0EB for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=vSHl0S4PqDkMqUJgW6ktHNSERN24+BULofJ6wFAAtfg=; b=PV5U5whN1zlkwPKYfEHIU8g9h5XnaZ8ei5A5W2ZTRVigvFtPpgmEfbOk rsenFcSLqICojOIa4QLc5j7ax2hDn4iehKAfjOY88sIXtY6JPoeWDNriD cUas66pKapujeemMIBcTpdDa1z/pt1y/wNEKtzk9z4zFKJBS+0PNIhXnS ZIlOZHgs9UYdeHBjgfSo7X2jsWgBPVT+hFQ04eQnaErcl/6naQVukvDTr 8YNzzrbyfFawYWMnNIqn+4YPX2rtkiv0byo39gOhxWw/FmOk0z47A7/UC awAYgy8dSVZC8hQ70eOEM7M/yIKT07JWPb9dGN26lhe9kbNA29Jhh0BRm A==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408312" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408312" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326030" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326030" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:16 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:12 -0700 Message-Id: <20230506005816.1891043-3-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin As we have more and more engines do not waste time sampling the ones no- one is monitoring. Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 67fa6cd77529..ba769f7fc385 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -339,6 +339,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) return; for_each_engine(engine, gt, id) { + if (!engine->pmu.enable) + continue; + if (!intel_engine_pm_get_if_awake(engine)) continue; From patchwork Sat May 6 00:58:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49702C77B75 for ; Sat, 6 May 2023 00:58:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAA6410E14E; Sat, 6 May 2023 00:58:19 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 89AB310E0EF for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ArIGzPohynnaC8RUljIGqfjFtOPmjLk4aQrNdHWxafY=; b=QYulxwVb92SjforLqmATB5PFnGLUzgBdFIXfLNkrITlod40+GMCUYmeM QhsocYx6LZDDJgyFIDTjueUfVR6EiJAISFTXEy/Ibf8ShZmXNMb4A47LJ 7OBmm1KdIxfLUPljKFYZoiy4/LbIp5H7ibGPN4T6vgDJDYL/Uq+pIrV+x fJtkoi2qKZLfUhVAB876gAK4t8Wfj+dJClQw3MAZ61XJ6Yk/nha5e4/w2 0XdunydypZ27UjwbmjvvyP/fFPmVtZAjdL27EYyrGuXX8tC8xErh9RT8u uA4uZGcJ7fjsOgGDsv2Cx+JL0FCOSUKUItV6JBTsOQseMRmXMmELJO3Xu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408313" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408313" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326033" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326033" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:13 -0700 Message-Id: <20230506005816.1891043-4-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Trivial prep work for full multi-tile enablement later. Signed-off-by: Tvrtko Ursulin Signed-off-by: Vinay Belgaumkar Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++-- drivers/gpu/drm/i915/i915_pmu.c | 16 ++++++++-------- drivers/gpu/drm/i915/i915_pmu.h | 9 +++++---- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index e02cb90723ae..c2e69bafd02b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf) intel_rc6_unpark(>->rc6); intel_rps_unpark(>->rps); - i915_pmu_gt_unparked(i915); + i915_pmu_gt_unparked(gt); intel_guc_busyness_unpark(gt); intel_gt_unpark_requests(gt); @@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf) intel_guc_busyness_park(gt); i915_vma_parked(gt); - i915_pmu_gt_parked(i915); + i915_pmu_gt_parked(gt); intel_rps_park(>->rps); intel_rc6_park(>->rc6); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index ba769f7fc385..2b63ee31e1b3 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -217,11 +217,11 @@ static void init_rc6(struct i915_pmu *pmu) } } -static void park_rc6(struct drm_i915_private *i915) +static void park_rc6(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915)); + pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt); pmu->sleep_last = ktime_get_raw(); } @@ -236,16 +236,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) } } -void i915_pmu_gt_parked(struct drm_i915_private *i915) +void i915_pmu_gt_parked(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; if (!pmu->base.event_init) return; spin_lock_irq(&pmu->lock); - park_rc6(i915); + park_rc6(gt); /* * Signal sampling timer to stop if only engine events are enabled and @@ -256,9 +256,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915) spin_unlock_irq(&pmu->lock); } -void i915_pmu_gt_unparked(struct drm_i915_private *i915) +void i915_pmu_gt_unparked(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; if (!pmu->base.event_init) return; diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index c30f43319a78..a686fd7ccedf 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -13,6 +13,7 @@ #include struct drm_i915_private; +struct intel_gt; /* * Non-engine events that we need to track enabled-disabled transition and @@ -151,15 +152,15 @@ int i915_pmu_init(void); void i915_pmu_exit(void); void i915_pmu_register(struct drm_i915_private *i915); void i915_pmu_unregister(struct drm_i915_private *i915); -void i915_pmu_gt_parked(struct drm_i915_private *i915); -void i915_pmu_gt_unparked(struct drm_i915_private *i915); +void i915_pmu_gt_parked(struct intel_gt *gt); +void i915_pmu_gt_unparked(struct intel_gt *gt); #else static inline int i915_pmu_init(void) { return 0; } static inline void i915_pmu_exit(void) {} static inline void i915_pmu_register(struct drm_i915_private *i915) {} static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} -static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {} -static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {} +static inline void i915_pmu_gt_parked(struct intel_gt *gt) {} +static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {} #endif #endif From patchwork Sat May 6 00:58:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB17EC77B75 for ; Sat, 6 May 2023 00:58:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0544710E146; Sat, 6 May 2023 00:58:19 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A12FB10E0EB for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=UMYUXeet1RNO/soUM/cchOMI3c8v/8IDcQKRS5utlkE=; b=Db87WKyvfNKDnu1URwLXtfey3nVGG1WMrzHeIq2hGm7B/EqWZ1iJd1g0 +iTDy4peMvxl3ZqwcqVlICy9C9weejtHBxbEXb9xmmX0DtGIOhGA/qIFu QM4LUdKuyZh0G78NFjwqhtqEi2BEia6FZhU1oCuFRpR1zto80VbBFeg5l 7D4y83ey7xxnNmcljps5v5Tj7gvUtfN0qZkiGB3TRKBldtSDEg/mUnUvd OzMH+JnxiV+vTLY3CyiFr9bsGpI7hRaUvOcAKb9AtbZwHGA+BndVGZqwY ZbQOJw4KlIH/cnPYw1VMcUFeOiXxeg5dTfHtxC1QTOUSqukIH0GPaK63+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408315" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408315" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326036" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326036" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:14 -0700 Message-Id: <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin We do not want to have timers per tile and waste CPU cycles and energy via multiple wake-up sources, for a relatively un-important task of PMU sampling, so keeping a single timer works well. But we also do not want the first GT which goes idle to turn off the timer. Add some reference counting, via a mask of unparked GTs, to solve this. Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 12 ++++++++++-- drivers/gpu/drm/i915/i915_pmu.h | 4 ++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 2b63ee31e1b3..669a42e44082 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt) * Signal sampling timer to stop if only engine events are enabled and * GPU went idle. */ - pmu->timer_enabled = pmu_needs_timer(pmu, false); + pmu->unparked &= ~BIT(gt->info.id); + if (pmu->unparked == 0) + pmu->timer_enabled = pmu_needs_timer(pmu, false); spin_unlock_irq(&pmu->lock); } @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt) /* * Re-enable sampling timer when GPU goes active. */ - __i915_pmu_maybe_start_timer(pmu); + if (pmu->unparked == 0) + __i915_pmu_maybe_start_timer(pmu); + + pmu->unparked |= BIT(gt->info.id); spin_unlock_irq(&pmu->lock); } @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) */ for_each_gt(gt, i915, i) { + if (!(pmu->unparked & BIT(i))) + continue; + engines_sample(gt, period_ns); if (i == 0) /* FIXME */ diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index a686fd7ccedf..3a811266ac6a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -76,6 +76,10 @@ struct i915_pmu { * @lock: Lock protecting enable mask and ref count handling. */ spinlock_t lock; + /** + * @unparked: GT unparked mask. + */ + unsigned int unparked; /** * @timer: Timer for internal i915 PMU sampling. */ From patchwork Sat May 6 00:58:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 111E4C7EE26 for ; Sat, 6 May 2023 00:58:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FB8F10E173; Sat, 6 May 2023 00:58:25 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD5F910E0EF for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=TbzMDB2pXA/qekzm3HaPJFqFmd7cdNBFJzlB0Ej1LAQ=; b=CKuUYeQmLtEvvdeITV/lLwDtTACDVTr9j+n3cXa7Bnd6+/tfSpHydu9m l24HCPiF4afz3yxX9L+weoEE/UsqtZN2UuVhvNf9QzZOXxqciIm4588z1 9617eRFB8XyuoeUvtxoK9HktERUHAzI00gQDHVD2slLZ5sUVxw9442fI3 K92LlnAiTygMQuUr62vGOXh5I4bXblWXcKJGupjVF+OffPo8wSIItl07J sXCuzngXRnN38uMgizKb5R7/MKA1vB4HYyxXf9jUTLxYTaHkNnTSPuU8B K+yFyNuVsPJONUIOqs+B11Yes/X6ULpeiviLjjmE0jIaJHNwznao7WOIv g==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408316" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408316" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326039" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326039" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:15 -0700 Message-Id: <20230506005816.1891043-6-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop FIXME. Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_pmu.c | 150 +++++++++++++++++++++++--------- drivers/gpu/drm/i915/i915_pmu.h | 9 +- include/uapi/drm/i915_drm.h | 17 +++- 3 files changed, 129 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 669a42e44082..12b2f3169abf 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -56,11 +56,21 @@ static bool is_engine_config(u64 config) return config < __I915_PMU_OTHER(0); } +static unsigned int config_gt_id(const u64 config) +{ + return config >> __I915_PMU_GT_SHIFT; +} + +static u64 config_counter(const u64 config) +{ + return config & ~(~0ULL << __I915_PMU_GT_SHIFT); +} + static unsigned int other_bit(const u64 config) { unsigned int val; - switch (config) { + switch (config_counter(config)) { case I915_PMU_ACTUAL_FREQUENCY: val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED; break; @@ -78,15 +88,20 @@ static unsigned int other_bit(const u64 config) return -1; } - return I915_ENGINE_SAMPLE_COUNT + val; + return I915_ENGINE_SAMPLE_COUNT + + config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT + + val; } static unsigned int config_bit(const u64 config) { - if (is_engine_config(config)) + if (is_engine_config(config)) { + GEM_BUG_ON(config_gt_id(config)); + return engine_config_sample(config); - else + } else { return other_bit(config); + } } static u64 config_mask(u64 config) @@ -104,6 +119,18 @@ static unsigned int event_bit(struct perf_event *event) return config_bit(event->attr.config); } +static u64 frequency_enabled_mask(void) +{ + unsigned int i; + u64 mask = 0; + + for (i = 0; i < I915_PMU_MAX_GTS; i++) + mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) | + config_mask(__I915_PMU_REQUESTED_FREQUENCY(i)); + + return mask; +} + static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); @@ -120,9 +147,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) * Mask out all the ones which do not need the timer, or in * other words keep all the ones that could need the timer. */ - enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) | - config_mask(I915_PMU_REQUESTED_FREQUENCY) | - ENGINE_SAMPLE_MASK; + enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK; /* * When the GPU is idle per-engine counters do not need to be @@ -164,9 +189,37 @@ static inline s64 ktime_since_raw(const ktime_t kt) return ktime_to_ns(ktime_sub(ktime_get_raw(), kt)); } +static unsigned int +__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample) +{ + unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample; + + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample)); + + return idx; +} + +static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample) +{ + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; +} + +static void +store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val) +{ + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; +} + +static void +add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul) +{ + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, mul); +} + static u64 get_rc6(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + const unsigned int gt_id = gt->info.id; struct i915_pmu *pmu = &i915->pmu; unsigned long flags; bool awake = false; @@ -181,7 +234,7 @@ static u64 get_rc6(struct intel_gt *gt) spin_lock_irqsave(&pmu->lock, flags); if (awake) { - pmu->sample[__I915_SAMPLE_RC6].cur = val; + store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val); } else { /* * We think we are runtime suspended. @@ -190,14 +243,14 @@ static u64 get_rc6(struct intel_gt *gt) * on top of the last known real value, as the approximated RC6 * counter value. */ - val = ktime_since_raw(pmu->sleep_last); - val += pmu->sample[__I915_SAMPLE_RC6].cur; + val = ktime_since_raw(pmu->sleep_last[gt_id]); + val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6); } - if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur) - val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur; + if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED)) + val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED); else - pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val; + store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val); spin_unlock_irqrestore(&pmu->lock, flags); @@ -207,13 +260,20 @@ static u64 get_rc6(struct intel_gt *gt) static void init_rc6(struct i915_pmu *pmu) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); - intel_wakeref_t wakeref; + struct intel_gt *gt; + unsigned int i; + + for_each_gt(gt, i915, i) { + intel_wakeref_t wakeref; - with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref) { - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915)); - pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = - pmu->sample[__I915_SAMPLE_RC6].cur; - pmu->sleep_last = ktime_get_raw(); + with_intel_runtime_pm(gt->uncore->rpm, wakeref) { + u64 val = __get_rc6(gt); + + store_sample(pmu, i, __I915_SAMPLE_RC6, val); + store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED, + val); + pmu->sleep_last[i] = ktime_get_raw(); + } } } @@ -221,8 +281,8 @@ static void park_rc6(struct intel_gt *gt) { struct i915_pmu *pmu = >->i915->pmu; - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt); - pmu->sleep_last = ktime_get_raw(); + store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt)); + pmu->sleep_last[gt->info.id] = ktime_get_raw(); } static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) @@ -362,34 +422,30 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) } } -static void -add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul) -{ - sample->cur += mul_u32_u32(val, mul); -} - -static bool frequency_sampling_enabled(struct i915_pmu *pmu) +static bool +frequency_sampling_enabled(struct i915_pmu *pmu, unsigned int gt) { return pmu->enable & - (config_mask(I915_PMU_ACTUAL_FREQUENCY) | - config_mask(I915_PMU_REQUESTED_FREQUENCY)); + (config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt)) | + config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt))); } static void frequency_sample(struct intel_gt *gt, unsigned int period_ns) { struct drm_i915_private *i915 = gt->i915; + const unsigned int gt_id = gt->info.id; struct i915_pmu *pmu = &i915->pmu; struct intel_rps *rps = >->rps; - if (!frequency_sampling_enabled(pmu)) + if (!frequency_sampling_enabled(pmu, gt_id)) return; /* Report 0/0 (actual/requested) frequency while parked. */ if (!intel_gt_pm_get_if_awake(gt)) return; - if (pmu->enable & config_mask(I915_PMU_ACTUAL_FREQUENCY)) { + if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) { u32 val; /* @@ -405,12 +461,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) if (!val) val = intel_gpu_freq(rps, rps->cur_freq); - add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT], + add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_ACT, val, period_ns / 1000); } - if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) { - add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ], + if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) { + add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ, intel_rps_get_requested_frequency(rps), period_ns / 1000); } @@ -447,9 +503,7 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) continue; engines_sample(gt, period_ns); - - if (i == 0) /* FIXME */ - frequency_sample(gt, period_ns); + frequency_sample(gt, period_ns); } hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD)); @@ -491,7 +545,12 @@ config_status(struct drm_i915_private *i915, u64 config) { struct intel_gt *gt = to_gt(i915); - switch (config) { + unsigned int gt_id = config_gt_id(config); + + if (gt_id) + return -ENOENT; + + switch (config_counter(config)) { case I915_PMU_ACTUAL_FREQUENCY: if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) /* Requires a mutex for sampling! */ @@ -599,22 +658,27 @@ static u64 __i915_pmu_event_read(struct perf_event *event) val = engine->pmu.sample[sample].cur; } } else { - switch (event->attr.config) { + const unsigned int gt_id = config_gt_id(event->attr.config); + const u64 config = config_counter(event->attr.config); + + switch (config) { case I915_PMU_ACTUAL_FREQUENCY: val = - div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur, + div_u64(read_sample(pmu, gt_id, + __I915_SAMPLE_FREQ_ACT), USEC_PER_SEC /* to MHz */); break; case I915_PMU_REQUESTED_FREQUENCY: val = - div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur, + div_u64(read_sample(pmu, gt_id, + __I915_SAMPLE_FREQ_REQ), USEC_PER_SEC /* to MHz */); break; case I915_PMU_INTERRUPTS: val = READ_ONCE(pmu->irq_count); break; case I915_PMU_RC6_RESIDENCY: - val = get_rc6(to_gt(i915)); + val = get_rc6(i915->gt[gt_id]); break; case I915_PMU_SOFTWARE_GT_AWAKE_TIME: val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915))); diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index 3a811266ac6a..d47846f21ddf 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -38,13 +38,16 @@ enum { __I915_NUM_PMU_SAMPLERS }; +#define I915_PMU_MAX_GTS (4) + /* * How many different events we track in the global PMU mask. * * It is also used to know to needed number of event reference counters. */ #define I915_PMU_MASK_BITS \ - (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT) + (I915_ENGINE_SAMPLE_COUNT + \ + I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT) #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) @@ -124,11 +127,11 @@ struct i915_pmu { * Only global counters are held here, while the per-engine ones are in * struct intel_engine_cs. */ - struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; + struct i915_pmu_sample sample[I915_PMU_MAX_GTS * __I915_NUM_PMU_SAMPLERS]; /** * @sleep_last: Last time GT parked for RC6 estimation. */ - ktime_t sleep_last; + ktime_t sleep_last[I915_PMU_MAX_GTS]; /** * @irq_count: Number of interrupts * diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index dba7c5a5b25e..d5ac1fdeb2b1 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_SEMA(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) +/* + * Top 4 bits of every non-engine counter are GT id. + */ +#define __I915_PMU_GT_SHIFT (60) + +#define ___I915_PMU_OTHER(gt, x) \ + (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ + ((__u64)(gt) << __I915_PMU_GT_SHIFT)) + +#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY +#define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) +#define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) +#define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) +#define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use From patchwork Sat May 6 00:58:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13233208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E846BC77B75 for ; Sat, 6 May 2023 00:58:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 52F7610E15B; Sat, 6 May 2023 00:58:20 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBCD310E0EB for ; Sat, 6 May 2023 00:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683334697; x=1714870697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=4+vr8zbMzYqL5heY0bkNdlkDubypy+O6D4wD0+5OJhI=; b=LnwUDtv8KIMuB5CysWHt4fB/lYHnuGEE3tod/v1X4YsGELNR+ZE9Eb9/ w560y1WT2gb/tUJCjrpAdHtOK994ppM825y8ir+K3QhT2aWk9QDUAInjW 6NdjtHsPawWMebynscNAJWsdJ+sOZaaDVYuN1v5NjZhUO2WxGp/CTgr0r QVfYDsQKLA4UfRfYLQCvp+i7WtrRpSyfNUxgRGjRTbfIExwVh9irZ6tOi 6cSdwQegBXkWTzGOGqh2RKd5P/YU3xN64OznDLpWMLZbXbEQnq6Lx27u2 /0DyZVthuBSDvFsWc1GoVusJeQKxD+4SExiW4z0QfAR0QY/6nBu5+MP50 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="377408317" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="377408317" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10701"; a="767326042" X-IronPort-AV: E=Sophos;i="5.99,253,1677571200"; d="scan'208";a="767326042" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2023 17:58:17 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org, Tvrtko Ursulin , Ashutosh Dixit Date: Fri, 5 May 2023 17:58:16 -0700 Message-Id: <20230506005816.1891043-7-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Start exporting frequency and RC6 counters from all tiles. Existing counters keep their names and config values and new one use the namespace added in the previous patch, with the "-gtN" added to their names. Interrupts counter is an odd one off. Because it is the global device counters (not only GT) we choose not to add per tile versions for now. Signed-off-by: Tvrtko Ursulin Signed-off-by: Aravind Iddamsetty Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 87 ++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 12b2f3169abf..284e5c5b97bb 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -546,8 +546,9 @@ config_status(struct drm_i915_private *i915, u64 config) struct intel_gt *gt = to_gt(i915); unsigned int gt_id = config_gt_id(config); + unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0; - if (gt_id) + if (gt_id > max_gt_id) return -ENOENT; switch (config_counter(config)) { @@ -561,6 +562,8 @@ config_status(struct drm_i915_private *i915, u64 config) return -ENODEV; break; case I915_PMU_INTERRUPTS: + if (gt_id) + return -ENOENT; break; case I915_PMU_RC6_RESIDENCY: if (!gt->rc6.supported) @@ -930,11 +933,20 @@ static const struct attribute_group i915_pmu_cpumask_attr_group = { .attrs = i915_cpumask_attrs, }; -#define __event(__config, __name, __unit) \ +#define __event(__counter, __name, __unit) \ { \ - .config = (__config), \ + .counter = (__counter), \ .name = (__name), \ .unit = (__unit), \ + .global = false, \ +} + +#define __global_event(__counter, __name, __unit) \ +{ \ + .counter = (__counter), \ + .name = (__name), \ + .unit = (__unit), \ + .global = true, \ } #define __engine_event(__sample, __name) \ @@ -973,15 +985,16 @@ create_event_attributes(struct i915_pmu *pmu) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); static const struct { - u64 config; + unsigned int counter; const char *name; const char *unit; + bool global; } events[] = { - __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"), - __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"), - __event(I915_PMU_INTERRUPTS, "interrupts", NULL), - __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"), - __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, "software-gt-awake-time", "ns"), + __event(0, "actual-frequency", "M"), + __event(1, "requested-frequency", "M"), + __global_event(2, "interrupts", NULL), + __event(3, "rc6-residency", "ns"), + __event(4, "software-gt-awake-time", "ns"), }; static const struct { enum drm_i915_pmu_engine_sample sample; @@ -996,12 +1009,17 @@ create_event_attributes(struct i915_pmu *pmu) struct i915_ext_attribute *i915_attr = NULL, *i915_iter; struct attribute **attr = NULL, **attr_iter; struct intel_engine_cs *engine; - unsigned int i; + struct intel_gt *gt; + unsigned int i, j; /* Count how many counters we will be exposing. */ - for (i = 0; i < ARRAY_SIZE(events); i++) { - if (!config_status(i915, events[i].config)) - count++; + for_each_gt(gt, i915, j) { + for (i = 0; i < ARRAY_SIZE(events); i++) { + u64 config = ___I915_PMU_OTHER(j, events[i].counter); + + if (!config_status(i915, config)) + count++; + } } for_each_uabi_engine(engine, i915) { @@ -1031,26 +1049,39 @@ create_event_attributes(struct i915_pmu *pmu) attr_iter = attr; /* Initialize supported non-engine counters. */ - for (i = 0; i < ARRAY_SIZE(events); i++) { - char *str; - - if (config_status(i915, events[i].config)) - continue; - - str = kstrdup(events[i].name, GFP_KERNEL); - if (!str) - goto err; + for_each_gt(gt, i915, j) { + for (i = 0; i < ARRAY_SIZE(events); i++) { + u64 config = ___I915_PMU_OTHER(j, events[i].counter); + char *str; - *attr_iter++ = &i915_iter->attr.attr; - i915_iter = add_i915_attr(i915_iter, str, events[i].config); + if (config_status(i915, config)) + continue; - if (events[i].unit) { - str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name); + if (events[i].global || !HAS_EXTRA_GT_LIST(i915)) + str = kstrdup(events[i].name, GFP_KERNEL); + else + str = kasprintf(GFP_KERNEL, "%s-gt%u", + events[i].name, j); if (!str) goto err; - *attr_iter++ = &pmu_iter->attr.attr; - pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit); + *attr_iter++ = &i915_iter->attr.attr; + i915_iter = add_i915_attr(i915_iter, str, config); + + if (events[i].unit) { + if (events[i].global || !HAS_EXTRA_GT_LIST(i915)) + str = kasprintf(GFP_KERNEL, "%s.unit", + events[i].name); + else + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit", + events[i].name, j); + if (!str) + goto err; + + *attr_iter++ = &pmu_iter->attr.attr; + pmu_iter = add_pmu_attr(pmu_iter, str, + events[i].unit); + } } }