From patchwork Tue May 9 19:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 13236092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C8AAC7EE23 for ; Tue, 9 May 2023 19:11:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D4C410E052; Tue, 9 May 2023 19:11:26 +0000 (UTC) Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22C5710E052 for ; Tue, 9 May 2023 19:11:24 +0000 (UTC) Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-195ffe37d10so541981fac.0 for ; Tue, 09 May 2023 12:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683659483; x=1686251483; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=7SBKSnGQTBkLIjNmdaQUl/gJk+HCRRsXzqznc1iL51k=; b=cZpW8zVQjMSQ4WoBPS9QBcy4qxm/DPFssrv5ZQm8++NC3EvLF/eY6VndM66B7+uVX7 FbTQT5Nnt3ocW70w7jc3qaSZlqiVb1FAlLLY8t733T1c6kBlLArOQa6pBTUTF4kv/6ot 9QkZM7/p90ZzVCYr4W60YNfEIf7X2rBPSLGwtMMTQHY6ikSf6MgeTNcCHHMgs41H4E8q jVQAly2hQMAlVy4KOqbr8nHmDgCxbJjb03H8ugYH96gfzmescTPhMO9CcJS4NGrHEXJd sOyl5X+n2Ebe8yu/l4HtX2UZK9tuqdcNbOiIq+76DF5+TYc+cyYcnd/4AlVtZgYFGwyq T7dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683659483; x=1686251483; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7SBKSnGQTBkLIjNmdaQUl/gJk+HCRRsXzqznc1iL51k=; b=Gq77Y7+t0bSJLT+gTyhXv0U8TqhZctJf4wUKoE0HixyEihvfsPsdM7ZQ9OpP7926Mj XMbrk/Ttv+bszRUHsjs6aJyyj5aTUxWU6I9AsI2E9z7Fxgms6s3t1G6LVTmotSWygjwg y+0jX6xWKhGiv+UHXEfhjfx2kiOqejfyAvRo6j1mItq0gpCccnXHJUm/C6UlVH+1r+VF 8RqVAPRp2HE9lMS3vqMKBIUJuz4pQrMNq82Vr0U4zDKt6XOe03OuiJRnbRYldqQwrwNl q7gK1j4XzAFi75Tycf1CmkHdtxEXsKGm+JUGw6pGQ82AqFj1Phg40hQuocdxM9bOnolk nu9w== X-Gm-Message-State: AC+VfDwLarUElK4jHmngx0baHwZI56fOde/S3r+8iFQ+01l2EZHZZCJ9 CvmoiMkjl4Bg6CJVeldR+gt2dNx5utzCLg== X-Google-Smtp-Source: ACHHUZ7okq0CBstdAFiCtDIdIZh0aPn6yrqa+xXNMaiBiNXOqb43R0HStG8Re0WImLuw/nPHzr1vMQ== X-Received: by 2002:a05:6870:42cb:b0:192:5e53:2e64 with SMTP id z11-20020a05687042cb00b001925e532e64mr8965273oah.1.1683659482861; Tue, 09 May 2023 12:11:22 -0700 (PDT) Received: from fabio-Precision-3551.. ([2804:14c:485:4b69:70eb:d83f:a7c5:b735]) by smtp.gmail.com with ESMTPSA id u1-20020a05687004c100b00192843c21b9sm6358134oam.25.2023.05.09.12.11.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 12:11:22 -0700 (PDT) From: Fabio Estevam To: neil.armstrong@linaro.org Subject: [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities' Date: Tue, 9 May 2023 16:10:58 -0300 Message-Id: <20230509191059.3327960-1-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Fabio Estevam , dri-devel@lists.freedesktop.org, robh+dt@kernel.org, jagan@amarulasolutions.com, krzysztof.kozlowski+dt@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- Changes since v2: - Use video-interfaces.yaml (Rob). .../display/bridge/samsung,mipi-dsim.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index e841659e20cd..dad6d06fbdd9 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -105,6 +105,35 @@ properties: DSI output port node to the panel or the next bridge in the chain. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + oneOf: + - minItems: 1 + maxItems: 4 + uniqueItems: true + items: + enum: [ 1, 2, 3, 4 ] + description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: + minItems: 1 + maxItems: 5 + items: + enum: [ 0, 1 ] + description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + + dependencies: + lane-polarities: [data-lanes] + required: - clock-names - clocks From patchwork Tue May 9 19:10:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 13236093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8A2BC77B75 for ; Tue, 9 May 2023 19:11:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99C4B10E1AB; Tue, 9 May 2023 19:11:29 +0000 (UTC) Received: from mail-oa1-x30.google.com (mail-oa1-x30.google.com [IPv6:2001:4860:4864:20::30]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8286710E3B0 for ; Tue, 9 May 2023 19:11:27 +0000 (UTC) Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-19206edf84cso943123fac.1 for ; Tue, 09 May 2023 12:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683659486; x=1686251486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zELyYYCze1nbjTtSk7q81x5cZykfsQ2b/WZzy8BWGgc=; b=UAupvrpRr+8b2qBjyfmWhCFjnh90mzA+bXw8oM3VcF7pm4OSShQzYLAX0k8kiNhyGw Nh5cr4phaEew88E5VB34rlI6U3n74gtqtR88s+3+HriVZdVGHXJRW55k6eiDbOPNyfU6 udeoJoOQ2SmD3o9cdLSxmgAhf03/H60MiyUE3fSMMLZ05TyLNNv706cSMTq2+gQshtZi GLhsfBjOS3aqJT+40mIIRW1ZG+BnSQd9/gGLYBz2xHvJscrqTYN0KcRbbDOi8AWd9SwL lcQaWPCOwtKk+PxhGH7NjsWHXMaLdfLTDph3R09X4oYXy6fy0FQJyLSL/3bdEHJEqItT VJ9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683659486; x=1686251486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zELyYYCze1nbjTtSk7q81x5cZykfsQ2b/WZzy8BWGgc=; b=lc4SFIK4yd7r/69KCu8AKBRrJ8wxPjXPuvPBtocLH3Yvn2sfBQOVhcQJajbCVKfzYr WMm/4nmxM2HHKWPg3xCTdKEEdqeR4RwSwQG0T/zk6wY3D/q8CF5qP5R59TOfFofGuBFG BvDeHHaekdWObHK0gcBRfHkVjvI/1JMkqOksucO0/P7gDIyo+ltdUUwWFXVjfPCQVO52 SkDzG9k0iiMABey2GQzp0iRq1QqZrO4NVeAN6nRBaNd7W6ulNtOyIQ8JjJkzVtKTQTZg wjzmUC6WKjOJZQY7N5G/9W5tVam5nji4DdQ1E6IxpdINs3LQ3/uG9hayqUqlL4Fv11f/ cacA== X-Gm-Message-State: AC+VfDx/jfKUUqbb2YZg33m3O+0T0Wkxy3tDcysf+TdsXWYMbOcaN24d 2U30wbGbirq+xVnNWF87h88= X-Google-Smtp-Source: ACHHUZ5rvxigYOa0vTbV3CMMwMTZwUdrfr8f25rOjVuOjspnYyt+Loykf1LbuxB5ia41TlGykMwvtg== X-Received: by 2002:a05:6870:42cb:b0:192:5e53:2e64 with SMTP id z11-20020a05687042cb00b001925e532e64mr8965343oah.1.1683659486472; Tue, 09 May 2023 12:11:26 -0700 (PDT) Received: from fabio-Precision-3551.. ([2804:14c:485:4b69:70eb:d83f:a7c5:b735]) by smtp.gmail.com with ESMTPSA id u1-20020a05687004c100b00192843c21b9sm6358134oam.25.2023.05.09.12.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 12:11:25 -0700 (PDT) From: Fabio Estevam To: neil.armstrong@linaro.org Subject: [PATCH v3 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap Date: Tue, 9 May 2023 16:10:59 -0300 Message-Id: <20230509191059.3327960-2-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230509191059.3327960-1-festevam@gmail.com> References: <20230509191059.3327960-1-festevam@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , devicetree@vger.kernel.org, Fabio Estevam , dri-devel@lists.freedesktop.org, robh+dt@kernel.org, jagan@amarulasolutions.com, krzysztof.kozlowski+dt@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Marek Vasut Implement support for DSI clock and data lane DN/DP polarity swap by means of decoding 'lane-polarities' DT property. The controller does support DN/DP swap of clock lane and all data lanes, the controller does not support polarity swap of individual data lane bundles, add a check which verifies all data lanes have the same polarity. This has been validated on an imx8mm board that actually has the MIPI DSI clock lanes inverted. Signed-off-by: Marek Vasut Signed-off-by: Fabio Estevam Reviewed-by: Jagan Teki --- Changes since v2: - None drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++- include/drm/bridge/samsung-dsim.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0a402a85787..5791148e2da2 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -183,6 +183,8 @@ #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) /* DSIM_PLLCTRL */ +#define DSIM_PLL_DPDNSWAP_CLK (1 << 25) +#define DSIM_PLL_DPDNSWAP_DAT (1 << 24) #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN BIT(23) #define DSIM_PLL_P(x, offset) ((x) << (offset)) @@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, reg |= DSIM_FREQ_BAND(band); } + if (dsi->swap_dn_dp_clk) + reg |= DSIM_PLL_DPDNSWAP_CLK; + if (dsi->swap_dn_dp_data) + reg |= DSIM_PLL_DPDNSWAP_DAT; + samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); timeout = 1000; @@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) { struct device *dev = dsi->dev; struct device_node *node = dev->of_node; - int ret; + u32 lane_polarities[5] = { 0 }; + struct device_node *endpoint; + int i, nr_lanes, ret; ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate); @@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) if (ret < 0) return ret; + endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); + nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); + if (nr_lanes > 0 && nr_lanes <= 4) { + /* Polarity 0 is clock lane, 1..4 are data lanes. */ + of_property_read_u32_array(endpoint, "lane-polarities", + lane_polarities, nr_lanes + 1); + for (i = 1; i <= nr_lanes; i++) { + if (lane_polarities[1] != lane_polarities[i]) + DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); + } + if (lane_polarities[0]) + dsi->swap_dn_dp_clk = true; + if (lane_polarities[1]) + dsi->swap_dn_dp_data = true; + } + return 0; } diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index ba5484de2b30..6a37d1e079bf 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -95,6 +95,8 @@ struct samsung_dsim { u32 mode_flags; u32 format; + bool swap_dn_dp_clk; + bool swap_dn_dp_data; int state; struct drm_property *brightness; struct completion completed;